From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 8202F5B34 for ; Fri, 9 Mar 2018 19:41:18 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Mar 2018 10:41:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,446,1515484800"; d="scan'208";a="33761702" Received: from silpixa00381635.ir.intel.com (HELO silpixa00381635.ger.corp.intel.com) ([10.237.222.149]) by orsmga003.jf.intel.com with ESMTP; 09 Mar 2018 10:41:14 -0800 From: Jasvinder Singh To: dev@dpdk.org Cc: cristian.dumitrescu@intel.com Date: Fri, 9 Mar 2018 18:41:13 +0000 Message-Id: <20180309184114.139136-1-jasvinder.singh@intel.com> X-Mailer: git-send-email 2.9.3 Subject: [dpdk-dev] [PATCH 1/2] librte_sched: add post-init pipe profile api X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Mar 2018 18:41:19 -0000 Add new API function to add more pipe configuration profiles post initialization to the set of exisitng profiles specified during the creation of scheduler port. This API removes the current limitation that forces the user to define the full set of pipe profiles as the part of port parameters while port is being created. Signed-off-by: Jasvinder Singh --- lib/librte_sched/rte_sched.c | 141 +++++++++++++++++++++++++++++++++ lib/librte_sched/rte_sched.h | 17 ++++ lib/librte_sched/rte_sched_version.map | 6 ++ 3 files changed, 164 insertions(+) diff --git a/lib/librte_sched/rte_sched.c b/lib/librte_sched/rte_sched.c index 634486c..43728ec 100644 --- a/lib/librte_sched/rte_sched.c +++ b/lib/librte_sched/rte_sched.c @@ -932,6 +932,147 @@ rte_sched_pipe_config(struct rte_sched_port *port, return 0; } +static void +rte_sched_pipe_profile_get(struct rte_sched_port *port, + struct rte_sched_pipe_params *params, + struct rte_sched_pipe_profile *p) +{ + uint32_t i; + + /* Token Bucket */ + if (params->tb_rate == port->rate) { + p->tb_credits_per_period = 1; + p->tb_period = 1; + } else { + double tb_rate = (double) params->tb_rate + / (double) port->rate; + double d = RTE_SCHED_TB_RATE_CONFIG_ERR; + + rte_approx(tb_rate, d, + &p->tb_credits_per_period, &p->tb_period); + } + + p->tb_size = params->tb_size; + + /* Traffic Classes */ + p->tc_period = rte_sched_time_ms_to_bytes(params->tc_period, + port->rate); + + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) + p->tc_credits_per_period[i] + = rte_sched_time_ms_to_bytes(params->tc_period, + params->tc_rate[i]); + +#ifdef RTE_SCHED_SUBPORT_TC_OV + p->tc_ov_weight = params->tc_ov_weight; +#endif + + /* WRR */ + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { + uint32_t wrr_cost[RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS]; + uint32_t lcd, lcd1, lcd2; + uint32_t qindex; + + qindex = i * RTE_SCHED_QUEUES_PER_TRAFFIC_CLASS; + + wrr_cost[0] = params->wrr_weights[qindex]; + wrr_cost[1] = params->wrr_weights[qindex + 1]; + wrr_cost[2] = params->wrr_weights[qindex + 2]; + wrr_cost[3] = params->wrr_weights[qindex + 3]; + + lcd1 = rte_get_lcd(wrr_cost[0], wrr_cost[1]); + lcd2 = rte_get_lcd(wrr_cost[2], wrr_cost[3]); + lcd = rte_get_lcd(lcd1, lcd2); + + wrr_cost[0] = lcd / wrr_cost[0]; + wrr_cost[1] = lcd / wrr_cost[1]; + wrr_cost[2] = lcd / wrr_cost[2]; + wrr_cost[3] = lcd / wrr_cost[3]; + + p->wrr_cost[qindex] = (uint8_t) wrr_cost[0]; + p->wrr_cost[qindex + 1] = (uint8_t) wrr_cost[1]; + p->wrr_cost[qindex + 2] = (uint8_t) wrr_cost[2]; + p->wrr_cost[qindex + 3] = (uint8_t) wrr_cost[3]; + } +} + +int +rte_sched_pipe_profile_add(struct rte_sched_port *port, + struct rte_sched_pipe_params *params, + int32_t *profile_id) +{ + struct rte_sched_pipe_profile pp; + uint32_t i; + + /* Port */ + if (port == NULL) + return -1; + + /* Pipe parameters */ + if (params == NULL) + return -2; + + /* TB rate: non-zero, not greater than port rate */ + if (params->tb_rate == 0 || + params->tb_rate > port->rate) + return -3; + + /* TB size: non-zero */ + if (params->tb_size == 0) + return -4; + + /* TC rate: non-zero, less than pipe rate */ + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { + if (params->tc_rate[i] == 0 || + params->tc_rate[i] > params->tb_rate) + return -5; + } + + /* TC period: non-zero */ + if (params->tc_period == 0) + return -6; + +#ifdef RTE_SCHED_SUBPORT_TC_OV + /* TC3 oversubscription weight: non-zero */ + if (params->tc_ov_weight == 0) + return -7; +#endif + + /* Queue WRR weights: non-zero */ + for (i = 0; i < RTE_SCHED_QUEUES_PER_PIPE; i++) { + if (params->wrr_weights[i] == 0) + return -8; + } + + /* Pipe profiles not exceeds the max limit */ + if (port->n_pipe_profiles >= RTE_SCHED_PIPE_PROFILES_PER_PORT) + return -9; + + memset(&pp, 0, sizeof(struct rte_sched_pipe_profile)); + rte_sched_pipe_profile_get(port, params, &pp); + + /* Pipe profile not exists */ + for (i = 0; i < port->n_pipe_profiles; i++) { + if (memcmp(port->pipe_profiles + i, &pp, sizeof(pp)) == 0) + return -10; + } + + /* Set port params */ + memcpy(port->pipe_profiles + port->n_pipe_profiles, &pp, sizeof(pp)); + + uint32_t pipe_tc3_rate = params->tc_rate[3]; + + if (port->pipe_tc3_rate_max < pipe_tc3_rate) + port->pipe_tc3_rate_max = pipe_tc3_rate; + + *profile_id = port->n_pipe_profiles; + port->n_pipe_profiles += 1; + + rte_sched_port_log_pipe_profile(port, *profile_id); + + return 0; +} + void rte_sched_port_pkt_write(struct rte_mbuf *pkt, uint32_t subport, uint32_t pipe, uint32_t traffic_class, diff --git a/lib/librte_sched/rte_sched.h b/lib/librte_sched/rte_sched.h index 5d2a688..7edccbe 100644 --- a/lib/librte_sched/rte_sched.h +++ b/lib/librte_sched/rte_sched.h @@ -271,6 +271,23 @@ rte_sched_pipe_config(struct rte_sched_port *port, int32_t pipe_profile); /** + * Hierarchical scheduler pipe profile add + * + * @param port + * Handle to port scheduler instance + * @param params + * Pipe configuration parameters + * @param pipe_profile_id + * Set to valid profile id when profile is added successfully. + * @return + * 0 upon success, error code otherwise + */ +int +rte_sched_pipe_profile_add(struct rte_sched_port *port, + struct rte_sched_pipe_params *params, + int32_t *pipe_profile_id); + +/** * Hierarchical scheduler memory footprint size per port * * @param params diff --git a/lib/librte_sched/rte_sched_version.map b/lib/librte_sched/rte_sched_version.map index 3aa159a..b709cf8 100644 --- a/lib/librte_sched/rte_sched_version.map +++ b/lib/librte_sched/rte_sched_version.map @@ -29,3 +29,9 @@ DPDK_2.1 { rte_sched_port_pkt_read_color; } DPDK_2.0; + +DPDK_18.05 { + global: + + rte_sched_pipe_profile_add; +} DPDK_2.1; -- 2.9.3