From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM03-BY2-obe.outbound.protection.outlook.com (mail-by2nam03on0065.outbound.protection.outlook.com [104.47.42.65]) by dpdk.org (Postfix) with ESMTP id C52501B81F for ; Tue, 3 Apr 2018 17:07:49 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=og5yoZr3zmOi5LKaVaF1W96Di/WbYv87FmzzlQrSel0=; b=PEbb6mHFTJ9AhgmJzlnAkXpfhf7hXe/rS8X3zTmW+D6AyFtYzDoKnm/fI9K/n1wvTSoeQ+JW/WpYh/f1CVn/wW4KDNfEmi1RDM/lqYjHz5M6Mxzmdua/dnYBv6/mT1sh9eKKLpwqBFd4cc9Vxwn1ATknhyoj5KTneQvymgns98w= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Jerin.JacobKollanukkaran@cavium.com; Received: from jerin (106.201.49.151) by BN3PR07MB2515.namprd07.prod.outlook.com (2a01:111:e400:7bbf::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.653.12; Tue, 3 Apr 2018 15:07:46 +0000 Date: Tue, 3 Apr 2018 20:37:23 +0530 From: Jerin Jacob To: Olivier Matz Cc: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com Message-ID: <20180403150722.GB15937@jerin> References: <20170630142609.6180-1-olivier.matz@6wind.com> <20180403132644.23729-1-olivier.matz@6wind.com> MIME-Version: 1.0 Content-Type: text/plain; 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The > size of rte_ring structure and the offset of the fields remain > the same on platforms with cache line size = 64B: > > rte_ring = 384 > rte_ring.name = 0 > rte_ring.flags = 32 > rte_ring.memzone = 40 > rte_ring.size = 48 > rte_ring.mask = 52 > rte_ring.prod = 128 > rte_ring.cons = 256 > > But it has an impact on platform where cache line size is 128B: > > rte_ring = 384 -> 768 > rte_ring.name = 0 > rte_ring.flags = 32 > rte_ring.memzone = 40 > rte_ring.size = 48 > rte_ring.mask = 52 > rte_ring.prod = 128 -> 256 Are we leaving TWO cacheline to make sure, HW prefetch don't load the adjust cacheline(consumer)? If so, Will it have impact on those machine where it is 128B Cache line and the HW prefetcher is not loading the next caching explicitly. Right? > rte_ring.cons = 256 -> 512 > > Link: http://dpdk.org/dev/patchwork/patch/25039/ > Suggested-by: Konstantin Ananyev > Signed-off-by: Olivier Matz