From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.droids-corp.org (zoll.droids-corp.org [94.23.50.67]) by dpdk.org (Postfix) with ESMTP id 1BB5DA492 for ; Tue, 3 Apr 2018 17:56:05 +0200 (CEST) Received: from lfbn-lil-1-702-109.w81-254.abo.wanadoo.fr ([81.254.39.109] helo=droids-corp.org) by mail.droids-corp.org with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1f3OIa-0005vy-Eq; Tue, 03 Apr 2018 17:56:42 +0200 Received: by droids-corp.org (sSMTP sendmail emulation); Tue, 03 Apr 2018 17:56:01 +0200 Date: Tue, 3 Apr 2018 17:56:01 +0200 From: Olivier Matz To: Jerin Jacob Cc: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com Message-ID: <20180403155601.rqb7fhu6vggzrh7e@platinum> References: <20170630142609.6180-1-olivier.matz@6wind.com> <20180403132644.23729-1-olivier.matz@6wind.com> <20180403150722.GB15937@jerin> <20180403152517.hsjghkj5z6mauze7@platinum> <20180403153703.GA19072@jerin> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180403153703.GA19072@jerin> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring structure X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Apr 2018 15:56:05 -0000 On Tue, Apr 03, 2018 at 09:07:04PM +0530, Jerin Jacob wrote: > -----Original Message----- > > Date: Tue, 3 Apr 2018 17:25:17 +0200 > > From: Olivier Matz > > To: Jerin Jacob > > CC: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com > > Subject: Re: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring > > structure > > User-Agent: NeoMutt/20170113 (1.7.2) > > > > On Tue, Apr 03, 2018 at 08:37:23PM +0530, Jerin Jacob wrote: > > > -----Original Message----- > > > > Date: Tue, 3 Apr 2018 15:26:44 +0200 > > > > From: Olivier Matz > > > > To: dev@dpdk.org > > > > Subject: [dpdk-dev] [PATCH] ring: relax alignment constraint on ring > > > > structure > > > > X-Mailer: git-send-email 2.11.0 > > > > > > > > The initial objective of > > > > commit d9f0d3a1ffd4 ("ring: remove split cacheline build setting") > > > > was to add an empty cache line betwee, the producer and consumer > > > > data (on platform with cache line size = 64B), preventing from > > > > having them on adjacent cache lines. > > > > > > > > Following discussion on the mailing list, it appears that this > > > > also imposes an alignment constraint that is not required. > > > > > > > > This patch removes the extra alignment constraint and adds the > > > > empty cache lines using padding fields in the structure. The > > > > size of rte_ring structure and the offset of the fields remain > > > > the same on platforms with cache line size = 64B: > > > > > > > > rte_ring = 384 > > > > rte_ring.name = 0 > > > > rte_ring.flags = 32 > > > > rte_ring.memzone = 40 > > > > rte_ring.size = 48 > > > > rte_ring.mask = 52 > > > > rte_ring.prod = 128 > > > > rte_ring.cons = 256 > > > > > > > > But it has an impact on platform where cache line size is 128B: > > > > > > > > rte_ring = 384 -> 768 > > > > rte_ring.name = 0 > > > > rte_ring.flags = 32 > > > > rte_ring.memzone = 40 > > > > rte_ring.size = 48 > > > > rte_ring.mask = 52 > > > > rte_ring.prod = 128 -> 256 > > > > rte_ring.cons = 256 -> 512 > > > > > > Are we leaving TWO cacheline to make sure, HW prefetch don't load > > > the adjust cacheline(consumer)? > > > > > > If so, Will it have impact on those machine where it is 128B Cache line > > > and the HW prefetcher is not loading the next caching explicitly. Right? > > > > The impact on machines that have a 128B cache line is that an unused > > cache line will be added between the producer and consumer data. I > > expect that the impact is positive in case there is a hw prefetcher, and > > null in case there is no such prefetcher. > > It is not NULL, Right? You are loosing 256B for each ring. Is it really that important? > > On machines with 64B cache line, this was already the case. It just > > reduces the alignment constraint. > > Not all the 64B CL machines will have HW prefetch. > > I would recommend to add conditional compilation flags to express HW > prefetch enabled or not? based on that we can decide to reserve > the additional space. By default, in common config, HW prefetch can > be enabled so that it works for almost all cases. The hw prefetcher can be enabled at runtime, so a compilation flag does not seem to be a good idea. Moreover, changing this compilation flag would change the ABI.