From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on0085.outbound.protection.outlook.com [104.47.36.85]) by dpdk.org (Postfix) with ESMTP id 52168A492 for ; Tue, 3 Apr 2018 18:43:18 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=CAVIUMNETWORKS.onmicrosoft.com; s=selector1-cavium-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=4R7HWqRArU0az32XdkmnqGLqzt5h5v/LjGDlz5RPprc=; b=CjZI8mnt0jguE45aXhdhe/6jk8F43bhV/O0sd132h787oEjaI232+2dBx7KenJqyK82cbmeNSEaGjv/r9txjVwyWToDMr5ffkB3nNcvactqz5hDO82riA1J1Td1XRL0lHeQjsxaxoR4AnLRiHKIXv8I9GZsm0aoYZtZ2ws3xXQ0= Received: from jerin (106.200.202.48) by CO2PR07MB2518.namprd07.prod.outlook.com (2603:10b6:102:12::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.631.10; Tue, 3 Apr 2018 16:43:14 +0000 Date: Tue, 3 Apr 2018 22:12:50 +0530 From: Jerin Jacob To: Olivier Matz Cc: dev@dpdk.org, konstantin.ananyev@intel.com, bruce.richardson@intel.com Message-ID: <20180403163254.GB19072@jerin> References: <20170630142609.6180-1-olivier.matz@6wind.com> <20180403132644.23729-1-olivier.matz@6wind.com> <20180403150722.GB15937@jerin> <20180403152517.hsjghkj5z6mauze7@platinum> <20180403153703.GA19072@jerin> <20180403155601.rqb7fhu6vggzrh7e@platinum> MIME-Version: 1.0 Content-Type: text/plain; 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The > > > > > size of rte_ring structure and the offset of the fields remain > > > > > the same on platforms with cache line size = 64B: > > > > > > > > > > rte_ring = 384 > > > > > rte_ring.name = 0 > > > > > rte_ring.flags = 32 > > > > > rte_ring.memzone = 40 > > > > > rte_ring.size = 48 > > > > > rte_ring.mask = 52 > > > > > rte_ring.prod = 128 > > > > > rte_ring.cons = 256 > > > > > > > > > > But it has an impact on platform where cache line size is 128B: > > > > > > > > > > rte_ring = 384 -> 768 > > > > > rte_ring.name = 0 > > > > > rte_ring.flags = 32 > > > > > rte_ring.memzone = 40 > > > > > rte_ring.size = 48 > > > > > rte_ring.mask = 52 > > > > > rte_ring.prod = 128 -> 256 > > > > > rte_ring.cons = 256 -> 512 > > > > > > > > Are we leaving TWO cacheline to make sure, HW prefetch don't load > > > > the adjust cacheline(consumer)? > > > > > > > > If so, Will it have impact on those machine where it is 128B Cache line > > > > and the HW prefetcher is not loading the next caching explicitly. Right? > > > > > > The impact on machines that have a 128B cache line is that an unused > > > cache line will be added between the producer and consumer data. I > > > expect that the impact is positive in case there is a hw prefetcher, and > > > null in case there is no such prefetcher. > > > > It is not NULL, Right? You are loosing 256B for each ring. > > Is it really that important? Pipeline or eventdev SW cases there could more rings in the system. I don't see any downside of having config option which is enabled default. In my view, such config options are good, as in embedded usecases, customers can really fine tune the target for the need. In server usecases, let the default of option be enabled, no harm. > > > > > On machines with 64B cache line, this was already the case. It just > > > reduces the alignment constraint. > > > > Not all the 64B CL machines will have HW prefetch. > > > > I would recommend to add conditional compilation flags to express HW > > prefetch enabled or not? based on that we can decide to reserve > > the additional space. By default, in common config, HW prefetch can > > be enabled so that it works for almost all cases. > > The hw prefetcher can be enabled at runtime, so a compilation flag > does not seem to be a good idea. Moreover, changing this compilation On those Hardwares HW prefetch can be disabled at runtime, it is fine with default config. I was taking about some low end ARM hardware which does not have HW prefetch is not present at all. > flag would change the ABI. ABI is broken anyway, Right? due to size of the structure change.