From: Bruce Richardson <bruce.richardson@intel.com>
To: Rosen Xu <rosen.xu@intel.com>
Cc: dev@dpdk.org, declan.doherty@intel.com, shreyansh.jain@nxp.com,
tianfei.zhang@intel.com, hao.wu@intel.com,
gaetan.rivet@6wind.com
Subject: Re: [dpdk-dev] [RFC 0/5] Intel FPGA BUS
Date: Wed, 4 Apr 2018 10:51:28 +0100 [thread overview]
Message-ID: <20180404095128.GA14376@bricha3-MOBL.ger.corp.intel.com> (raw)
In-Reply-To: <1520609944-120305-1-git-send-email-rosen.xu@intel.com>
On Fri, Mar 09, 2018 at 11:38:59PM +0800, Rosen Xu wrote:
> With Partial Reconfigure(PR) parts of Bitstream, Field Programmable Gate Array(FPGA) not only provides one kinds of accelerator but also provides many types of accelerators at the same time.
>
> How DPDK fully support FPGA?
> - We use Rawdev to provide FPGA PR
> - DPDK Driver will not bind to PCI Device it will bind to FPGA Partial-Bitstream(AFU,Accelerated Function Unit)
> - For the new Device scan, driver probe, we involve Intel FPGA Bus Module
>
> This patchset is base on v18.02.
>
Please always base patches on the latest head of the tree you are
targetting. The patches won't be applied on top of the release, but on top
of the tree!
/Bruce
prev parent reply other threads:[~2018-04-04 9:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-09 15:38 Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 1/5] Add Intel FPGA BUS Command Parse Code Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 2/5] Add Intel FPGA BUS Probe Code Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 3/5] Add Intel FPGA BUS Lib Code Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 4/5] Add Intel FPGA BUS Rawdev Code Rosen Xu
2018-03-09 15:39 ` [dpdk-dev] [RFC 5/5] Add Intel OPAE Share Code Rosen Xu
2018-04-04 9:51 ` Bruce Richardson [this message]
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