From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 76B6B1BC41 for ; Wed, 11 Apr 2018 16:42:57 +0200 (CEST) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Apr 2018 07:42:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,436,1517904000"; d="scan'208";a="219587675" Received: from bricha3-mobl.ger.corp.intel.com ([10.237.221.51]) by fmsmga005.fm.intel.com with SMTP; 11 Apr 2018 07:42:53 -0700 Received: by (sSMTP sendmail emulation); Wed, 11 Apr 2018 15:42:52 +0100 Date: Wed, 11 Apr 2018 15:42:51 +0100 From: Bruce Richardson To: Rafal Kozik Cc: dev@dpdk.org, mw@semihalf.com, mk@semihalf.com, gtzalik@amazon.com, evgenys@amazon.com, matua@amazon.com, igorch@amazon.com, ferruh.yigit@intel.com Message-ID: <20180411144251.GA33124@bricha3-MOBL.ger.corp.intel.com> References: <1523455637-31719-1-git-send-email-rk@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1523455637-31719-1-git-send-email-rk@semihalf.com> Organization: Intel Research and Development Ireland Ltd. User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [PATCH 0/4] support for write combining X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Apr 2018 14:42:57 -0000 On Wed, Apr 11, 2018 at 04:07:13PM +0200, Rafal Kozik wrote: > Support for write combining. > > Rafal Kozik (4): > igb_uio: add wc option > bus/pci: reference driver structure > eal: enable WC during resources mapping > net/ena: enable WC > > drivers/bus/pci/linux/pci_uio.c | 39 ++++++++++++++++++++++++++++----------- > drivers/bus/pci/pci_common.c | 13 ++++++++----- > drivers/bus/pci/rte_bus_pci.h | 2 ++ > drivers/net/ena/ena_ethdev.c | 3 ++- > kernel/linux/igb_uio/igb_uio.c | 17 ++++++++++++++--- > 5 files changed, 54 insertions(+), 20 deletions(-) > Couple of thoughts on this set. You add an option to the kernel module to allow wc to be supported on a device, but when we go to do PCI mapping, we either map the regular resource file or the _wc one. Therefore: 1. Why not always have igb_uio support write-combining since it can be controlled thereafter via userspace mapping one file or another? 2. Why not always map both resource and resource_wc files at the PCI level, and make them available via different pointers to the driver? Then the driver can choose at the per-access level which it wants to use. For example, for init of a device, a driver may do all register access via uncachable memory, and only use the write-combined support for performance-critical parts. [I have a draft patch lying around here somewhere that does something similar to that.] One last question - if using vfio-pci kernel module, do the resource_wc files present the bars as write-combined memory type, or are they uncachable? Regards, /Bruce