From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 1EC661DFD9 for ; Thu, 14 Jun 2018 12:51:56 +0200 (CEST) X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Jun 2018 03:51:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,222,1526367600"; d="scan'208";a="57292720" Received: from bricha3-mobl.ger.corp.intel.com ([10.237.221.107]) by fmsmga002.fm.intel.com with SMTP; 14 Jun 2018 03:51:53 -0700 Received: by (sSMTP sendmail emulation); Thu, 14 Jun 2018 11:51:49 +0100 Date: Thu, 14 Jun 2018 11:51:49 +0100 From: Bruce Richardson To: Xueming Li Cc: Wenzhuo Lu , Jingjing Wu , Bernard Iremonger , dev@dpdk.org, Shahaf Shuler Message-ID: <20180614105148.GF17264@bricha3-MOBL.ger.corp.intel.com> References: <20180526151520.8579-1-xuemingl@mellanox.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180526151520.8579-1-xuemingl@mellanox.com> Organization: Intel Research and Development Ireland Ltd. User-Agent: Mutt/1.10.0 (2018-05-17) Subject: Re: [dpdk-dev] [PATCH] app/testpmd: distribute queues to cores X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Jun 2018 10:51:57 -0000 On Sat, May 26, 2018 at 11:15:20PM +0800, Xueming Li wrote: > Current topology distribute forwarding streams to lcores by port, this > make unbalanced loading when port number larger than 2: > lcore 0: P0Q0->P1Q0, P0Q1->P1Q1 > locre 1: P1Q0->P0Q0, P1Q1->P0Q1 > If only one port has traffic, only one locre get fully loaded and the > other one get no forwarding. Performance is bad as only one core doing > forwarding in such case. > > This patch distributes forwarding streams by queue, try to get streams > of each port handled by different lcore: > lcore 0: P0Q0->P1Q0, P1Q0->P1Q0 > locre 1: P0Q1->P0Q1, P1Q1->P0Q1 > > Signed-off-by: Xueming Li > --- Acked-by: Bruce Richardson