From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id DE5B62BC9; Tue, 17 Jul 2018 23:38:02 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jul 2018 14:38:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,367,1526367600"; d="scan'208";a="65430024" Received: from silpixa00399466.ir.intel.com (HELO silpixa00399466.ger.corp.intel.com) ([10.237.223.220]) by FMSMGA003.fm.intel.com with ESMTP; 17 Jul 2018 14:38:00 -0700 From: Pablo de Lara To: bruce.richardson@intel.com Cc: dev@dpdk.org, Pablo de Lara , stable@dpdk.org Date: Tue, 17 Jul 2018 14:31:50 +0100 Message-Id: <20180717133151.30065-1-pablo.de.lara.guarch@intel.com> X-Mailer: git-send-email 2.14.4 Subject: [dpdk-dev] [PATCH 1/2] test/hash: fix multiwriter with non consecutive cores X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jul 2018 21:38:04 -0000 When non consecutive cores are passed into the test application, the distribution of the keys that each thread needs to insert is not correct, since it assumes that there are no cores skipped between the master core and the worker core. Fixes: be856325cba3 ("hash: add scalable multi-writer insertion with Intel TSX") Cc: stable@dpdk.org Signed-off-by: Pablo de Lara --- test/test/test_hash_multiwriter.c | 41 ++++++++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 5 deletions(-) diff --git a/test/test/test_hash_multiwriter.c b/test/test/test_hash_multiwriter.c index f182f4052..acd6a91ca 100644 --- a/test/test/test_hash_multiwriter.c +++ b/test/test/test_hash_multiwriter.c @@ -48,18 +48,29 @@ static rte_atomic64_t ginsertions; static int use_htm; static int -test_hash_multiwriter_worker(__attribute__((unused)) void *arg) +test_hash_multiwriter_worker(void *arg) { uint64_t i, offset; + uint16_t pos_core; uint32_t lcore_id = rte_lcore_id(); uint64_t begin, cycles; + uint16_t *enabled_core_ids = (uint16_t *)arg; - offset = (lcore_id - rte_get_master_lcore()) - * tbl_multiwriter_test_params.nb_tsx_insertion; + for (pos_core = 0; pos_core < rte_lcore_count(); pos_core++) { + if (enabled_core_ids[pos_core] == lcore_id) + break; + } + + /* + * Calculate offset for entries based on the position of the + * logical core, from the master core (not counting not enabled cores) + */ + offset = pos_core * tbl_multiwriter_test_params.nb_tsx_insertion; printf("Core #%d inserting %d: %'"PRId64" - %'"PRId64"\n", lcore_id, tbl_multiwriter_test_params.nb_tsx_insertion, - offset, offset + tbl_multiwriter_test_params.nb_tsx_insertion); + offset, + offset + tbl_multiwriter_test_params.nb_tsx_insertion - 1); begin = rte_rdtsc_precise(); @@ -88,6 +99,8 @@ test_hash_multiwriter(void) { unsigned int i, rounded_nb_total_tsx_insertion; static unsigned calledCount = 1; + uint16_t enabled_core_ids[RTE_MAX_LCORE]; + uint16_t core_id; uint32_t *keys; uint32_t *found; @@ -159,9 +172,27 @@ test_hash_multiwriter(void) rte_atomic64_init(&ginsertions); rte_atomic64_clear(&ginsertions); + /* Get list of enabled cores */ + i = 0; + for (core_id = 0; core_id < RTE_MAX_LCORE; core_id++) { + if (i == rte_lcore_count()) + break; + + if (rte_lcore_is_enabled(core_id)) { + enabled_core_ids[i] = core_id; + i++; + } + } + + if (i != rte_lcore_count()) { + printf("Number of enabled cores in list is different from " + "number given by rte_lcore_count()\n"); + goto err3; + } + /* Fire all threads. */ rte_eal_mp_remote_launch(test_hash_multiwriter_worker, - NULL, CALL_MASTER); + enabled_core_ids, CALL_MASTER); rte_eal_mp_wait_lcore(); count = rte_hash_count(handle); -- 2.14.4