From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-f68.google.com (mail-wr1-f68.google.com [209.85.221.68]) by dpdk.org (Postfix) with ESMTP id 8A2221AEEE for ; Fri, 24 Aug 2018 19:14:28 +0200 (CEST) Received: by mail-wr1-f68.google.com with SMTP id k5-v6so8058952wre.10 for ; Fri, 24 Aug 2018 10:14:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=y4FV/0aZTrXedV3X4ni+5ItfjC7X+btLY8BTJ7Dphf4=; b=Oa5sOG/yUkEFCLramgI+/UCWxHg/RMpJ5N0+FbAqm0HghHEb5414RuMpKGCeIhYo2n cLtPvV5XxpMMOepZtrNa7Wrm5CEGTRXhFaauab2pGiTT13chkEIYMEvSwQeYGO2ibfD+ IoOf7bbh5fUTjjT44df0CNtw1OztGcmhXWeSZIJRT7KYkOVKtl/1ql52Y8IT+R8phrtQ J7l64SV51H7FvU0JT0ccMm0kmn0dbmV6WyQByBd7eFnWKO+UNgvMGN2W/X/B7WDbqJx/ zWWTZz5wc+n+l67lApNPuSqgS8gtKDX6yX8uoc+iCfFrfBf2yzaHOYkAMe7/RcIpqDDf LSDQ== X-Gm-Message-State: APzg51AhWucc5BczzbKVTCc9aHoDgR6Cq/lsOXzy/lwdV+Zb9HQvxYF3 kUeYfEqLaIKu9o1JZZ5g0xE/MkEo X-Google-Smtp-Source: ANB0VdZNVzuk4MDsjo6U5jiHUGCwEjMYstpTodctbKuVv9pirKw+BoJsBdlMSsxSBVdFMKmTCyQ4RQ== X-Received: by 2002:a5d:6451:: with SMTP id d17-v6mr1709240wrw.64.1535130867781; Fri, 24 Aug 2018 10:14:27 -0700 (PDT) Received: from localhost ([2a01:4b00:f419:6f00:8361:8946:ba2b:d556]) by smtp.gmail.com with ESMTPSA id j6-v6sm5463014wrq.25.2018.08.24.10.14.25 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 24 Aug 2018 10:14:26 -0700 (PDT) From: Luca Boccassi To: dev@dpdk.org Cc: maxime.coquelin@redhat.com, zhihong.wang@intel.com, tiwei.bie@intel.com, bruce.richardson@intel.com, brian.russell@intl.att.com Date: Fri, 24 Aug 2018 18:14:20 +0100 Message-Id: <20180824171420.31246-2-bluca@debian.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180824171420.31246-1-bluca@debian.org> References: <20180820164421.28763-1-bluca@debian.org> <20180824171420.31246-1-bluca@debian.org> Subject: [dpdk-dev] [PATCH v4 2/2] virtio: fix PCI config err handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Aug 2018 17:14:28 -0000 From: Brian Russell In virtio_read_caps and vtpci_msix_detect, rte_pci_read_config returns the number of bytes read from PCI config or < 0 on error. If less than the expected number of bytes are read then log the failure and return rather than carrying on with garbage. Fixes: 6ba1f63b5ab0 ("virtio: support specification 1.0") Signed-off-by: Brian Russell Signed-off-by: Luca Boccassi --- v2: handle additional rte_pci_read_config incomplete reads v3: do not handle rte_pci_read_config of virtio cap, added in v2, as it's less clear what the right thing to do there is v4: do a more robust check - first check what the vendor is, and skip the cap entirely if it's not what we are looking for. drivers/net/virtio/virtio_pci.c | 57 ++++++++++++++++++++++++--------- 1 file changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c index 6bd22e54a6..cfefa9789b 100644 --- a/drivers/net/virtio/virtio_pci.c +++ b/drivers/net/virtio/virtio_pci.c @@ -567,16 +567,30 @@ virtio_read_caps(struct rte_pci_device *dev, struct virtio_hw *hw) } ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST); - if (ret < 0) { - PMD_INIT_LOG(DEBUG, "failed to read pci capability list"); + if (ret != 1) { + PMD_INIT_LOG(DEBUG, + "failed to read pci capability list, ret %d", ret); return -1; } while (pos) { + ret = rte_pci_read_config(dev, &cap, 2, pos); + if (ret != 2) { + PMD_INIT_LOG(DEBUG, + "failed to read pci cap at pos: %x ret %d", + pos, ret); + break; + } + if (cap.cap_vndr != PCI_CAP_ID_MSIX && + cap.cap_vndr != PCI_CAP_ID_VNDR) { + goto next; + } + ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos); - if (ret < 0) { - PMD_INIT_LOG(ERR, - "failed to read pci cap at pos: %x", pos); + if (ret != sizeof(cap)) { + PMD_INIT_LOG(DEBUG, + "failed to read pci cap at pos: %x ret %d", + pos, ret); break; } @@ -689,25 +703,38 @@ enum virtio_msix_status vtpci_msix_detect(struct rte_pci_device *dev) { uint8_t pos; - struct virtio_pci_cap cap; int ret; ret = rte_pci_read_config(dev, &pos, 1, PCI_CAPABILITY_LIST); - if (ret < 0) { - PMD_INIT_LOG(DEBUG, "failed to read pci capability list"); + if (ret != 1) { + PMD_INIT_LOG(DEBUG, + "failed to read pci capability list, ret %d", ret); return VIRTIO_MSIX_NONE; } while (pos) { - ret = rte_pci_read_config(dev, &cap, sizeof(cap), pos); - if (ret < 0) { - PMD_INIT_LOG(ERR, - "failed to read pci cap at pos: %x", pos); + uint8_t cap[2]; + + ret = rte_pci_read_config(dev, cap, sizeof(cap), pos); + if (ret != sizeof(cap)) { + PMD_INIT_LOG(DEBUG, + "failed to read pci cap at pos: %x ret %d", + pos, ret); break; } - if (cap.cap_vndr == PCI_CAP_ID_MSIX) { - uint16_t flags = ((uint16_t *)&cap)[1]; + if (cap[0] == PCI_CAP_ID_MSIX) { + uint16_t flags; + + ret = rte_pci_read_config(dev, &flags, sizeof(flags), + pos + sizeof(cap)); + if (ret != sizeof(flags)) { + PMD_INIT_LOG(DEBUG, + "failed to read pci cap at pos:" + " %x ret %d", pos + sizeof(cap), + ret); + break; + } if (flags & PCI_MSIX_ENABLE) return VIRTIO_MSIX_ENABLED; @@ -715,7 +742,7 @@ vtpci_msix_detect(struct rte_pci_device *dev) return VIRTIO_MSIX_DISABLED; } - pos = cap.cap_next; + pos = cap[1]; } return VIRTIO_MSIX_NONE; -- 2.18.0