From: Shreyansh Jain <shreyansh.jain@nxp.com>
To: dev@dpdk.org, ferruh.yigit@intel.com
Cc: thomas@monjalon.net, Hemant Agrawal <hemant.agrawal@nxp.com>
Subject: [dpdk-dev] [PATCH v2 05/15] crypto/dpaa2_sec: upgarde mc FW APIs to 10.10.0
Date: Wed, 26 Sep 2018 23:34:30 +0530 [thread overview]
Message-ID: <20180926180440.31726-6-shreyansh.jain@nxp.com> (raw)
In-Reply-To: <20180926180440.31726-1-shreyansh.jain@nxp.com>
From: Hemant Agrawal <hemant.agrawal@nxp.com>
This also brings in support to configure the queues
for order restoration.
Signed-off-by: Hemant Agrawal <hemant.agrawal@nxp.com>
---
drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 1 +
drivers/crypto/dpaa2_sec/mc/dpseci.c | 128 ++++++++++++++++++-
drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h | 25 +++-
drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h | 73 ++++++++++-
4 files changed, 218 insertions(+), 9 deletions(-)
diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
index 2a3c61c66..e77039870 100644
--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c
@@ -24,6 +24,7 @@
#include <dpaa2_hw_pvt.h>
#include <dpaa2_hw_dpio.h>
#include <dpaa2_hw_mempool.h>
+#include <fsl_dpopr.h>
#include <fsl_dpseci.h>
#include <fsl_mc_sys.h>
diff --git a/drivers/crypto/dpaa2_sec/mc/dpseci.c b/drivers/crypto/dpaa2_sec/mc/dpseci.c
index de8ca970c..87e0defdc 100644
--- a/drivers/crypto/dpaa2_sec/mc/dpseci.c
+++ b/drivers/crypto/dpaa2_sec/mc/dpseci.c
@@ -6,6 +6,7 @@
*/
#include <fsl_mc_sys.h>
#include <fsl_mc_cmd.h>
+#include <fsl_dpopr.h>
#include <fsl_dpseci.h>
#include <fsl_dpseci_cmd.h>
@@ -116,11 +117,13 @@ int dpseci_create(struct fsl_mc_io *mc_io,
cmd_flags,
dprc_token);
cmd_params = (struct dpseci_cmd_create *)cmd.params;
- for (i = 0; i < DPSECI_PRIO_NUM; i++)
+ for (i = 0; i < 8; i++)
cmd_params->priorities[i] = cfg->priorities[i];
+ for (i = 0; i < 8; i++)
+ cmd_params->priorities2[i] = cfg->priorities[8 + i];
cmd_params->num_tx_queues = cfg->num_tx_queues;
cmd_params->num_rx_queues = cfg->num_rx_queues;
- cmd_params->options = cfg->options;
+ cmd_params->options = cpu_to_le32(cfg->options);
/* send command to mc*/
err = mc_send_command(mc_io, &cmd);
@@ -302,7 +305,7 @@ int dpseci_get_attributes(struct fsl_mc_io *mc_io,
/* retrieve response parameters */
rsp_params = (struct dpseci_rsp_get_attr *)cmd.params;
attr->id = le32_to_cpu(rsp_params->id);
- attr->options = rsp_params->options;
+ attr->options = le32_to_cpu(rsp_params->options);
attr->num_tx_queues = rsp_params->num_tx_queues;
attr->num_rx_queues = rsp_params->num_rx_queues;
@@ -490,6 +493,8 @@ int dpseci_get_sec_attr(struct fsl_mc_io *mc_io,
attr->arc4_acc_num = rsp_params->arc4_acc_num;
attr->des_acc_num = rsp_params->des_acc_num;
attr->aes_acc_num = rsp_params->aes_acc_num;
+ attr->ccha_acc_num = rsp_params->ccha_acc_num;
+ attr->ptha_acc_num = rsp_params->ptha_acc_num;
return 0;
}
@@ -569,6 +574,113 @@ int dpseci_get_api_version(struct fsl_mc_io *mc_io,
return 0;
}
+/**
+ * dpseci_set_opr() - Set Order Restoration configuration.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPSECI object
+ * @index: The queue index
+ * @options: Configuration mode options
+ * can be OPR_OPT_CREATE or OPR_OPT_RETIRE
+ * @cfg: Configuration options for the OPR
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpseci_set_opr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t index,
+ uint8_t options,
+ struct opr_cfg *cfg)
+{
+ struct dpseci_cmd_set_opr *cmd_params;
+ struct mc_command cmd = { 0 };
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_SET_OPR,
+ cmd_flags,
+ token);
+ cmd_params = (struct dpseci_cmd_set_opr *)cmd.params;
+ cmd_params->index = index;
+ cmd_params->options = options;
+ cmd_params->oloe = cfg->oloe;
+ cmd_params->oeane = cfg->oeane;
+ cmd_params->olws = cfg->olws;
+ cmd_params->oa = cfg->oa;
+ cmd_params->oprrws = cfg->oprrws;
+
+ /* send command to mc*/
+ return mc_send_command(mc_io, &cmd);
+}
+
+/**
+ * dpseci_get_opr() - Retrieve Order Restoration config and query.
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPSECI object
+ * @index: The queue index
+ * @cfg: Returned OPR configuration
+ * @qry: Returned OPR query
+ *
+ * Return: '0' on Success; Error code otherwise.
+ */
+int dpseci_get_opr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t index,
+ struct opr_cfg *cfg,
+ struct opr_qry *qry)
+{
+ struct dpseci_rsp_get_opr *rsp_params;
+ struct dpseci_cmd_get_opr *cmd_params;
+ struct mc_command cmd = { 0 };
+ int err;
+
+ /* prepare command */
+ cmd.header = mc_encode_cmd_header(DPSECI_CMDID_GET_OPR,
+ cmd_flags,
+ token);
+ cmd_params = (struct dpseci_cmd_get_opr *)cmd.params;
+ cmd_params->index = index;
+
+ /* send command to mc*/
+ err = mc_send_command(mc_io, &cmd);
+ if (err)
+ return err;
+
+ /* retrieve response parameters */
+ rsp_params = (struct dpseci_rsp_get_opr *)cmd.params;
+ cfg->oloe = rsp_params->oloe;
+ cfg->oeane = rsp_params->oeane;
+ cfg->olws = rsp_params->olws;
+ cfg->oa = rsp_params->oa;
+ cfg->oprrws = rsp_params->oprrws;
+ qry->rip = dpseci_get_field(rsp_params->flags, RIP);
+ qry->enable = dpseci_get_field(rsp_params->flags, OPR_ENABLE);
+ qry->nesn = le16_to_cpu(rsp_params->nesn);
+ qry->ndsn = le16_to_cpu(rsp_params->ndsn);
+ qry->ea_tseq = le16_to_cpu(rsp_params->ea_tseq);
+ qry->tseq_nlis = dpseci_get_field(rsp_params->tseq_nlis, TSEQ_NLIS);
+ qry->ea_hseq = le16_to_cpu(rsp_params->ea_hseq);
+ qry->hseq_nlis = dpseci_get_field(rsp_params->hseq_nlis, HSEQ_NLIS);
+ qry->ea_hptr = le16_to_cpu(rsp_params->ea_hptr);
+ qry->ea_tptr = le16_to_cpu(rsp_params->ea_tptr);
+ qry->opr_vid = le16_to_cpu(rsp_params->opr_vid);
+ qry->opr_id = le16_to_cpu(rsp_params->opr_id);
+
+ return 0;
+}
+
+/**
+ * dpseci_set_congestion_notification() - Set congestion group
+ * notification configuration
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPSECI object
+ * @cfg: congestion notification configuration
+ *
+ * Return: '0' on success, error code otherwise
+ */
int dpseci_set_congestion_notification(
struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
@@ -604,6 +716,16 @@ int dpseci_set_congestion_notification(
return mc_send_command(mc_io, &cmd);
}
+/**
+ * dpseci_get_congestion_notification() - Get congestion group
+ * notification configuration
+ * @mc_io: Pointer to MC portal's I/O object
+ * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
+ * @token: Token of DPSECI object
+ * @cfg: congestion notification configuration
+ *
+ * Return: '0' on success, error code otherwise
+ */
int dpseci_get_congestion_notification(
struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
diff --git a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h
index 12ac005ad..279e8f4d4 100644
--- a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h
+++ b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci.h
@@ -20,7 +20,7 @@ struct fsl_mc_io;
/**
* Maximum number of Tx/Rx priorities per DPSECI object
*/
-#define DPSECI_PRIO_NUM 8
+#define DPSECI_MAX_QUEUE_NUM 16
/**
* All queues considered; see dpseci_set_rx_queue()
@@ -58,7 +58,7 @@ struct dpseci_cfg {
uint32_t options;
uint8_t num_tx_queues;
uint8_t num_rx_queues;
- uint8_t priorities[DPSECI_PRIO_NUM];
+ uint8_t priorities[DPSECI_MAX_QUEUE_NUM];
};
int dpseci_create(struct fsl_mc_io *mc_io,
@@ -259,6 +259,10 @@ int dpseci_get_tx_queue(struct fsl_mc_io *mc_io,
* implemented in this version of SEC.
* @aes_acc_num: The number of copies of the AES module that are
* implemented in this version of SEC.
+ * @ccha_acc_num: The number of copies of the ChaCha20 module that are
+ * implemented in this version of SEC.
+ * @ptha_acc_num: The number of copies of the Poly1305 module that are
+ * implemented in this version of SEC.
**/
struct dpseci_sec_attr {
@@ -279,6 +283,8 @@ struct dpseci_sec_attr {
uint8_t arc4_acc_num;
uint8_t des_acc_num;
uint8_t aes_acc_num;
+ uint8_t ccha_acc_num;
+ uint8_t ptha_acc_num;
};
int dpseci_get_sec_attr(struct fsl_mc_io *mc_io,
@@ -316,6 +322,21 @@ int dpseci_get_api_version(struct fsl_mc_io *mc_io,
uint32_t cmd_flags,
uint16_t *major_ver,
uint16_t *minor_ver);
+
+int dpseci_set_opr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t index,
+ uint8_t options,
+ struct opr_cfg *cfg);
+
+int dpseci_get_opr(struct fsl_mc_io *mc_io,
+ uint32_t cmd_flags,
+ uint16_t token,
+ uint8_t index,
+ struct opr_cfg *cfg,
+ struct opr_qry *qry);
+
/**
* enum dpseci_congestion_unit - DPSECI congestion units
* @DPSECI_CONGESTION_UNIT_BYTES: bytes units
diff --git a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h
index 26cef0f73..af3518a0f 100644
--- a/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h
+++ b/drivers/crypto/dpaa2_sec/mc/fsl_dpseci_cmd.h
@@ -9,22 +9,25 @@
/* DPSECI Version */
#define DPSECI_VER_MAJOR 5
-#define DPSECI_VER_MINOR 1
+#define DPSECI_VER_MINOR 3
/* Command versioning */
#define DPSECI_CMD_BASE_VERSION 1
#define DPSECI_CMD_BASE_VERSION_V2 2
+#define DPSECI_CMD_BASE_VERSION_V3 3
#define DPSECI_CMD_ID_OFFSET 4
#define DPSECI_CMD_V1(id) \
((id << DPSECI_CMD_ID_OFFSET) | DPSECI_CMD_BASE_VERSION)
#define DPSECI_CMD_V2(id) \
((id << DPSECI_CMD_ID_OFFSET) | DPSECI_CMD_BASE_VERSION_V2)
+#define DPSECI_CMD_V3(id) \
+ ((id << DPSECI_CMD_ID_OFFSET) | DPSECI_CMD_BASE_VERSION_V3)
/* Command IDs */
#define DPSECI_CMDID_CLOSE DPSECI_CMD_V1(0x800)
#define DPSECI_CMDID_OPEN DPSECI_CMD_V1(0x809)
-#define DPSECI_CMDID_CREATE DPSECI_CMD_V2(0x909)
+#define DPSECI_CMDID_CREATE DPSECI_CMD_V3(0x909)
#define DPSECI_CMDID_DESTROY DPSECI_CMD_V1(0x989)
#define DPSECI_CMDID_GET_API_VERSION DPSECI_CMD_V1(0xa09)
@@ -37,9 +40,10 @@
#define DPSECI_CMDID_SET_RX_QUEUE DPSECI_CMD_V1(0x194)
#define DPSECI_CMDID_GET_RX_QUEUE DPSECI_CMD_V1(0x196)
#define DPSECI_CMDID_GET_TX_QUEUE DPSECI_CMD_V1(0x197)
-#define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V1(0x198)
+#define DPSECI_CMDID_GET_SEC_ATTR DPSECI_CMD_V2(0x198)
#define DPSECI_CMDID_GET_SEC_COUNTERS DPSECI_CMD_V1(0x199)
-
+#define DPSECI_CMDID_SET_OPR DPSECI_CMD_V1(0x19A)
+#define DPSECI_CMDID_GET_OPR DPSECI_CMD_V1(0x19B)
#define DPSECI_CMDID_SET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x170)
#define DPSECI_CMDID_GET_CONGESTION_NOTIFICATION DPSECI_CMD_V1(0x171)
@@ -63,6 +67,8 @@ struct dpseci_cmd_create {
uint8_t num_rx_queues;
uint8_t pad[6];
uint32_t options;
+ uint32_t pad2;
+ uint8_t priorities2[8];
};
struct dpseci_cmd_destroy {
@@ -152,6 +158,8 @@ struct dpseci_rsp_get_sec_attr {
uint8_t arc4_acc_num;
uint8_t des_acc_num;
uint8_t aes_acc_num;
+ uint8_t ccha_acc_num;
+ uint8_t ptha_acc_num;
};
struct dpseci_rsp_get_sec_counters {
@@ -169,6 +177,63 @@ struct dpseci_rsp_get_api_version {
uint16_t minor;
};
+struct dpseci_cmd_set_opr {
+ uint16_t pad0;
+ uint8_t index;
+ uint8_t options;
+ uint8_t pad1[7];
+ uint8_t oloe;
+ uint8_t oeane;
+ uint8_t olws;
+ uint8_t oa;
+ uint8_t oprrws;
+};
+
+struct dpseci_cmd_get_opr {
+ uint16_t pad;
+ uint8_t index;
+};
+
+#define DPSECI_RIP_SHIFT 0
+#define DPSECI_RIP_SIZE 1
+#define DPSECI_OPR_ENABLE_SHIFT 1
+#define DPSECI_OPR_ENABLE_SIZE 1
+#define DPSECI_TSEQ_NLIS_SHIFT 0
+#define DPSECI_TSEQ_NLIS_SIZE 1
+#define DPSECI_HSEQ_NLIS_SHIFT 0
+#define DPSECI_HSEQ_NLIS_SIZE 1
+
+struct dpseci_rsp_get_opr {
+ uint64_t pad0;
+ /* from LSB: rip:1 enable:1 */
+ uint8_t flags;
+ uint16_t pad1;
+ uint8_t oloe;
+ uint8_t oeane;
+ uint8_t olws;
+ uint8_t oa;
+ uint8_t oprrws;
+ uint16_t nesn;
+ uint16_t pad8;
+ uint16_t ndsn;
+ uint16_t pad2;
+ uint16_t ea_tseq;
+ /* only the LSB */
+ uint8_t tseq_nlis;
+ uint8_t pad3;
+ uint16_t ea_hseq;
+ /* only the LSB */
+ uint8_t hseq_nlis;
+ uint8_t pad4;
+ uint16_t ea_hptr;
+ uint16_t pad5;
+ uint16_t ea_tptr;
+ uint16_t pad6;
+ uint16_t opr_vid;
+ uint16_t pad7;
+ uint16_t opr_id;
+};
+
#define DPSECI_DEST_TYPE_SHIFT 0
#define DPSECI_DEST_TYPE_SIZE 4
#define DPSECI_CG_UNITS_SHIFT 4
--
2.17.1
next prev parent reply other threads:[~2018-09-26 18:05 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-17 10:36 [dpdk-dev] [PATCH 00/11] Upgrade DPAA2 FW and other feature/bug fixes Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 01/11] bus/fslmc: upgrade mc FW APIs to 10.10.0 Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 02/11] bus/fslmc: upgrade qdma " Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 03/11] net/dpaa2: upgrade dpni to " Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 04/11] crypto/dpaa2_sec: upgarde " Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 05/11] bus/fslmc: support memory backed portals with QBMAN 5.0 Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 06/11] bus/fslmc: support 32 enq and deq for LX2 platform Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 07/11] bus/fslmc: disable annotation prefetch for LX2 Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 08/11] net/dpaa2: fix IOVA conversion for congestion memory Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 09/11] net/dpaa2: read hardware provided MAC for DPNI devices Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 10/11] net/dpaa2: add per queue stats get and reset support Shreyansh Jain
2018-09-17 10:36 ` [dpdk-dev] [PATCH 11/11] net/dpaa2: fix VLAN filter enablement Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 00/15] Upgrade DPAA2 FW and other feature/bug fixes Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 01/15] net/dpaa2: fix IOVA conversion for congestion memory Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 02/15] net/dpaa2: fix VLAN filter enablement Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 03/15] bus/fslmc: upgrade mc FW APIs to 10.10.0 Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 04/15] net/dpaa2: upgrade dpni to " Shreyansh Jain
2018-09-26 18:04 ` Shreyansh Jain [this message]
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 06/15] bus/fslmc: support memory backed portals with QBMAN 5.0 Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 07/15] bus/fslmc: support 32 enq and deq for LX2 platform Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 08/15] bus/fslmc: disable annotation prefetch for LX2 Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 09/15] net/dpaa2: read hardware provided MAC for DPNI devices Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 10/15] net/dpaa2: add per queue stats get and reset support Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 11/15] net/dpaa2: update RSS value in mbuf for lx2 platform Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 12/15] net/dpaa2: optimize the fd reset in Tx path Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 13/15] net/dpaa2: enhance the queue memory cleanup routines Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 14/15] net/dpaa2: support MBUF VLAN tci population from HW parser Shreyansh Jain
2018-09-26 18:04 ` [dpdk-dev] [PATCH v2 15/15] net/dpaa2: support Rx checksum offload in slow parsing Shreyansh Jain
2018-10-12 9:32 ` [dpdk-dev] [PATCH v2 00/15] Upgrade DPAA2 FW and other feature/bug fixes Shreyansh Jain
2018-10-12 9:42 ` Shreyansh Jain
2018-10-12 10:16 ` Thomas Monjalon
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 " Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 01/15] net/dpaa2: fix IOVA conversion for congestion memory Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 02/15] net/dpaa2: fix VLAN filter enablement Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 03/15] bus/fslmc: upgrade mc FW APIs to 10.10.0 Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 04/15] net/dpaa2: upgrade dpni to " Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 05/15] crypto/dpaa2_sec: upgarde " Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 06/15] bus/fslmc: support memory backed portals with QBMAN 5.0 Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 07/15] bus/fslmc: support 32 enq and deq for LX2 platform Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 08/15] bus/fslmc: disable annotation prefetch for LX2 Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 09/15] net/dpaa2: read hardware provided MAC for DPNI devices Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 10/15] net/dpaa2: add per queue stats get and reset support Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 11/15] net/dpaa2: update RSS value in mbuf for lx2 platform Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 12/15] net/dpaa2: optimize the fd reset in Tx path Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 13/15] net/dpaa2: enhance the queue memory cleanup routines Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 14/15] net/dpaa2: support MBUF VLAN tci population from HW parser Shreyansh Jain
2018-10-12 10:04 ` [dpdk-dev] [PATCH v3 15/15] net/dpaa2: support Rx checksum offload in slow parsing Shreyansh Jain
2018-10-16 10:24 ` [dpdk-dev] [PATCH v3 00/15] Upgrade DPAA2 FW and other feature/bug fixes Thomas Monjalon
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--in-reply-to=20180926180440.31726-6-shreyansh.jain@nxp.com \
--to=shreyansh.jain@nxp.com \
--cc=dev@dpdk.org \
--cc=ferruh.yigit@intel.com \
--cc=hemant.agrawal@nxp.com \
--cc=thomas@monjalon.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
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Be sure your reply has a Subject: header at the top and a blank line
before the message body.
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