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Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Sep 2018 07:46:37 -0000 This patch introduces the enetc PMD with basic initialisation functions includes probe, teardown, hardware initialisation Signed-off-by: Gagandeep Singh --- config/common_base | 5 + config/common_linuxapp | 5 + drivers/net/Makefile | 1 + drivers/net/enetc/Makefile | 22 ++ drivers/net/enetc/base/enetc_hw.h | 217 +++++++++++++++++ drivers/net/enetc/enetc.h | 90 +++++++ drivers/net/enetc/enetc_ethdev.c | 251 ++++++++++++++++++++ drivers/net/enetc/enetc_logs.h | 40 ++++ drivers/net/enetc/meson.build | 10 + drivers/net/enetc/rte_pmd_enetc_version.map | 4 + drivers/net/meson.build | 1 + mk/rte.app.mk | 1 + 12 files changed, 647 insertions(+) create mode 100644 drivers/net/enetc/Makefile create mode 100644 drivers/net/enetc/base/enetc_hw.h create mode 100644 drivers/net/enetc/enetc.h create mode 100644 drivers/net/enetc/enetc_ethdev.c create mode 100644 drivers/net/enetc/enetc_logs.h create mode 100644 drivers/net/enetc/meson.build create mode 100644 drivers/net/enetc/rte_pmd_enetc_version.map diff --git a/config/common_base b/config/common_base index 4bcbaf923..a7fc48667 100644 --- a/config/common_base +++ b/config/common_base @@ -217,6 +217,11 @@ CONFIG_RTE_LIBRTE_DPAA2_USE_PHYS_IOVA=y CONFIG_RTE_LIBRTE_DPAA2_PMD=n CONFIG_RTE_LIBRTE_DPAA2_DEBUG_DRIVER=n +# +# Compile NXP ENETC PMD Driver +# +CONFIG_RTE_LIBRTE_ENETC_PMD=n + # # Compile burst-oriented Amazon ENA PMD driver # diff --git a/config/common_linuxapp b/config/common_linuxapp index 9c5ea9d89..485e1467d 100644 --- a/config/common_linuxapp +++ b/config/common_linuxapp @@ -44,3 +44,8 @@ CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV=y CONFIG_RTE_LIBRTE_PMD_DPAA2_SEC=y CONFIG_RTE_LIBRTE_PMD_DPAA2_CMDIF_RAWDEV=y CONFIG_RTE_LIBRTE_PMD_DPAA2_QDMA_RAWDEV=y + +# +# NXP ENETC PMD Driver +# +CONFIG_RTE_LIBRTE_ENETC_PMD=y diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 664398de9..3ad436045 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -24,6 +24,7 @@ DIRS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2 endif DIRS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000 DIRS-$(CONFIG_RTE_LIBRTE_ENA_PMD) += ena +DIRS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc DIRS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += enic DIRS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += failsafe DIRS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += fm10k diff --git a/drivers/net/enetc/Makefile b/drivers/net/enetc/Makefile new file mode 100644 index 000000000..519153868 --- /dev/null +++ b/drivers/net/enetc/Makefile @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +include $(RTE_SDK)/mk/rte.vars.mk + +# +# library name +# +LIB = librte_pmd_enetc.a + +CFLAGS += -O3 +CFLAGS += $(WERROR_FLAGS) +EXPORT_MAP := rte_pmd_enetc_version.map +LIBABIVER := 1 + +SRCS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += enetc_ethdev.c + +LDLIBS += -lrte_eal +LDLIBS += -lrte_ethdev +LDLIBS += -lrte_bus_pci + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/net/enetc/base/enetc_hw.h b/drivers/net/enetc/base/enetc_hw.h new file mode 100644 index 000000000..c962b9ca1 --- /dev/null +++ b/drivers/net/enetc/base/enetc_hw.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018 NXP + */ + +#ifndef _ENETC_HW_H_ +#define _ENETC_HW_H_ +#include + +#define BIT(x) ((uint64_t)1 << ((x))) + +/* ENETC device IDs */ +#define ENETC_DEV_ID_VF 0xef00 +#define ENETC_DEV_ID 0xe100 + +/* ENETC register block BAR */ +#define ENETC_BAR_REGS 0x0 + +/* SI regs, offset: 0h */ +#define ENETC_SIMR 0x0 +#define ENETC_SIMR_EN BIT(31) + +#define ENETC_SIPMAR0 0x80 +#define ENETC_SIPMAR1 0x84 + +#define ENETC_SICAPR0 0x900 +#define ENETC_SICAPR1 0x904 + +#define ENETC_SIMSITRV(n) (0xB00 + (n) * 0x4) +#define ENETC_SIMSIRRV(n) (0xB80 + (n) * 0x4) + +#define ENETC_SICCAPR 0x1200 + +/* enum for BD type */ +enum enetc_bdr_type {TX, RX}; + +#define ENETC_BDR(type, n, off) (0x8000 + (type) * 0x100 + (n) * 0x200 \ + + (off)) +/* RX BDR reg offsets */ +#define ENETC_RBMR 0x0 /* RX BDR mode register*/ +#define ENETC_RBMR_EN BIT(31) + +#define ENETC_RBSR 0x4 /* Rx BDR status register*/ +#define ENETC_RBBSR 0x8 /* Rx BDR buffer size register*/ +#define ENETC_RBCIR 0xc /* Rx BDR consumer index register*/ +#define ENETC_RBBAR0 0x10 /* Rx BDR base address register 0 */ +#define ENETC_RBBAR1 0x14 /* Rx BDR base address register 1*/ +#define ENETC_RBPIR 0x18 /* Rx BDR producer index register*/ +#define ENETC_RBLENR 0x20 /* Rx BDR length register*/ +#define ENETC_RBIER 0xa0 /* Rx BDR interrupt enable register*/ +#define ENETC_RBIER_RXTIE BIT(0) +#define ENETC_RBIDR 0xa4 /* Rx BDR interrupt detect register*/ +#define ENETC_RBICIR0 0xa8 /* Rx BDR inetrrupt coalescing register 0*/ +#define ENETC_RBICIR0_ICEN BIT(31) + + +#define ENETC_TBMR 0x0 /* Tx BDR mode register (TBMR) 32 RW */ +#define ENETC_TBSR 0x4 /* x BDR status register (TBSR) 32 RO */ +#define ENETC_TBBAR0 0x10 /* Tx BDR base address register 0 (TBBAR0) 32 RW */ +#define ENETC_TBBAR1 0x14 /* Tx BDR base address register 1 (TBBAR1) 32 RW */ +#define ENETC_TBCIR 0x18 /* Tx BDR consumer index register (TBCIR) 32 RW */ +#define ENETC_TBCISR 0x1C /* Tx BDR consumer index shadow register 32 RW */ +#define ENETC_TBIER 0xA0 /* Tx BDR interrupt enable register 32 RW */ +#define ENETC_TBIDR 0xA4 /* Tx BDR interrupt detect register 32 RO */ +#define ENETC_TBICR0 0xA8 /* Tx BDR interrupt coalescing register 0 32 RW */ +#define ENETC_TBICR1 0xAC /* Tx BDR interrupt coalescing register 1 32 RW */ +#define ENETC_TBLENR 0x20 + +#define ENETC_TBCISR_IDX_MASK 0xffff +#define ENETC_TBIER_TXFIE BIT(1) + +#define ENETC_RTBLENR_LEN(n) ((n) & ~0x7) +#define ENETC_TBMR_EN BIT(31) + +/* Port regs, offset: 1_0000h */ +#define ENETC_PORT_BASE 0x10000 +#define ENETC_PMR 0x00000 +#define ENETC_PMR_EN (BIT(16) | BIT(17) | BIT(18)) +#define ENETC_PSR 0x00004 /* RO */ +#define ENETC_PSIPMR 0x00018 +#define ENETC_PSIPMR_SET_UP(n) (0x1 << (n)) /* n = SI index */ +#define ENETC_PSIPMR_SET_MP(n) (0x1 << ((n) + 8)) +#define ENETC_PSIPMR_SET_VLAN_MP(n) (0x1 << ((n) + 16)) +#define ENETC_PSIPMAR0(n) (0x00100 + (n) * 0x20) +#define ENETC_PSIPMAR1(n) (0x00104 + (n) * 0x20) +#define ENETC_PCAPR0 0x00900 +#define ENETC_PCAPR1 0x00904 + +#define ENETC_PV0CFGR(n) (0x00920 + (n) * 0x10) +#define ENETC_PVCFGR_SET_TXBDR(val) ((val) & 0xff) +#define ENETC_PVCFGR_SET_RXBDR(val) (((val) & 0xff) << 16) + +#define ENETC_PM0_CMD_CFG 0x08008 +#define ENETC_PM0_TX_EN BIT(0) +#define ENETC_PM0_RX_EN BIT(1) + +#define ENETC_PM0_MAXFRM 0x08014 +#define ENETC_SET_MAXFRM(val) ((val) << 16) + +/* Global regs, offset: 2_0000h */ +#define ENETC_GLOBAL_BASE 0x20000 +#define ENETC_G_EIPBRR0 0x00bf8 +#define ENETC_G_EIPBRR1 0x00bfc + +#define ETH_ADDR_LEN 6 + +/* general register accessors */ +#define enetc_rd_reg(reg) rte_read32((reg)) +#define enetc_wr_reg(reg, val) rte_write32((val), (reg)) +#define enetc_rd(hw, off) enetc_rd_reg((hw)->reg + (off)) +#define enetc_wr(hw, off, val) enetc_wr_reg((hw)->reg + (off), val) +/* port register accessors - PF only */ +#define enetc_port_rd(hw, off) enetc_rd_reg((hw)->port + (off)) +#define enetc_port_wr(hw, off, val) enetc_wr_reg((hw)->port + (off), val) +/* global register accessors - PF only */ +#define enetc_global_rd(hw, off) enetc_rd_reg((hw)->global + (off)) +#define enetc_global_wr(hw, off, val) enetc_wr_reg((hw)->global + (off), val) +/* BDR register accessors, see ENETC_BDR() */ +#define enetc_bdr_rd(hw, t, n, off) \ + enetc_rd(hw, ENETC_BDR(t, n, off)) +#define enetc_bdr_wr(hw, t, n, off, val) \ + enetc_wr(hw, ENETC_BDR(t, n, off), val) + +#define enetc_txbdr_rd(hw, n, off) enetc_bdr_rd(hw, TX, n, off) +#define enetc_rxbdr_rd(hw, n, off) enetc_bdr_rd(hw, RX, n, off) +#define enetc_txbdr_wr(hw, n, off, val) \ + enetc_bdr_wr(hw, TX, n, off, val) +#define enetc_rxbdr_wr(hw, n, off, val) \ + enetc_bdr_wr(hw, RX, n, off, val) + +#define ENETC_TX_ADDR(txq, addr) ((void *)((txq)->enetc_txbdr + (addr))) + +#define ENETC_TXBD_FLAGS_IE BIT(13) +#define ENETC_TXBD_FLAGS_F BIT(15) + +/* ENETC Parsed values (Little Endian) */ +#define ENETC_PKT_TYPE_ETHER 0x0060 +#define ENETC_PKT_TYPE_IPV4 0x0000 +#define ENETC_PKT_TYPE_IPV6 0x0020 +#define ENETC_PKT_TYPE_IPV4_TCP \ + (0x0010 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_TCP \ + (0x0010 | ENETC_PKT_TYPE_IPV6) +#define ENETC_PKT_TYPE_IPV4_UDP \ + (0x0011 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_UDP \ + (0x0011 | ENETC_PKT_TYPE_IPV6) +#define ENETC_PKT_TYPE_IPV4_SCTP \ + (0x0013 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_SCTP \ + (0x0013 | ENETC_PKT_TYPE_IPV6) +#define ENETC_PKT_TYPE_IPV4_ICMP \ + (0x0003 | ENETC_PKT_TYPE_IPV4) +#define ENETC_PKT_TYPE_IPV6_ICMP \ + (0x0003 | ENETC_PKT_TYPE_IPV6) + +/* PCI device info */ +struct enetc_hw { + void *reg; /* SI registers, used by all PCI functions */ + void *port; /* Port registers, PF only */ + void *global; /* IP global registers, PF only */ +}; + +struct enetc_eth_mac_info { + uint8_t addr[ETH_ADDR_LEN]; + uint8_t perm_addr[ETH_ADDR_LEN]; + uint8_t get_link_status; +}; + +struct enetc_eth_hw { + struct rte_eth_dev *ndev; + struct enetc_hw hw; + uint16_t device_id; + uint16_t vendor_id; + uint8_t revision_id; + struct enetc_eth_mac_info mac; +}; + +/* Transmit Descriptor */ +struct enetc_tx_desc { + uint64_t addr; + uint16_t frm_len; + uint16_t buf_len; + uint32_t flags_errors; +}; + +/* TX Buffer Descriptors (BD) */ +struct enetc_tx_bd { + uint64_t addr; + uint16_t buf_len; + uint16_t frm_len; + uint16_t err_csum; + uint16_t flags; +}; + +/* RX buffer descriptor */ +union enetc_rx_bd { + struct { + uint64_t addr; + uint8_t reserved[8]; + } w; + struct { + uint16_t inet_csum; + uint16_t parse_summary; + uint32_t rss_hash; + uint16_t buf_len; + uint16_t vlan_opt; + union { + struct { + uint16_t flags; + uint16_t error; + }; + uint32_t lstatus; + }; + } r; +}; + +#endif diff --git a/drivers/net/enetc/enetc.h b/drivers/net/enetc/enetc.h new file mode 100644 index 000000000..9fa7c726c --- /dev/null +++ b/drivers/net/enetc/enetc.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018 NXP + */ + +#ifndef _ENETC_H_ +#define _ENETC_H_ + +#include + +#include "base/enetc_hw.h" + +#define PCI_VENDOR_ID_FREESCALE 0x1957 + +/* Max TX rings per ENETC. */ +#define MAX_TX_RINGS 2 + +/* Max RX rings per ENTEC. */ +#define MAX_RX_RINGS 1 + +/* Max BD counts per Ring. */ +#define MAX_BD_COUNT 256 + +/* + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((uint32_t)(((n) >> 16) >> 16)) + +/* + * lower_32_bits - return bits 0-31 of a number + * @n: the number we're accessing + */ +#define lower_32_bits(n) ((uint32_t)(n)) + +#define ENETC_TXBD(BDR, i) (&(((struct enetc_tx_bd *)((BDR).bd_base))[i])) +#define ENETC_RXBD(BDR, i) (&(((union enetc_rx_bd *)((BDR).bd_base))[i])) + +struct enetc_swbd { + struct rte_mbuf *buffer_addr; +}; + +struct enetc_bdr { + struct rte_eth_dev *ndev; + struct rte_mempool *mb_pool; /* mbuf pool to populate RX ring. */ + void *bd_base; /* points to Rx or Tx BD ring */ + union { + void *tcir; + void *rcir; + }; + uint16_t index; + int bd_count; /* # of BDs */ + int next_to_use; + int next_to_clean; + struct enetc_swbd *q_swbd; + union { + void *tcisr; /* Tx */ + int next_to_alloc; /* Rx */ + }; +}; + +/* + * Structure to store private data for each driver instance (for each port). + */ +struct enetc_eth_adapter { + struct rte_eth_dev *ndev; + struct enetc_eth_hw hw; +}; + +#define ENETC_DEV_PRIVATE(adapter) \ + ((struct enetc_eth_adapter *)adapter) + +#define ENETC_DEV_PRIVATE_TO_HW(adapter) \ + (&((struct enetc_eth_adapter *)adapter)->hw) + +#define ENETC_DEV_PRIVATE_TO_STATS(adapter) \ + (&((struct enetc_eth_adapter *)adapter)->stats) + +#define ENETC_DEV_PRIVATE_TO_INTR(adapter) \ + (&((struct enetc_eth_adapter *)adapter)->intr) + +#define ENETC_GET_HW_ADDR(reg, addr) ((void *)(((size_t)reg) + (addr))) +#define ENETC_REG_READ(addr) (*(uint32_t *)addr) +#define ENETC_REG_WRITE(addr, val) (*(uint32_t *)addr = val) +#define ENETC_REG_WRITE_RELAXED(addr, val) (*(uint32_t *)addr = val) + +#endif /* _ENETC_H_ */ diff --git a/drivers/net/enetc/enetc_ethdev.c b/drivers/net/enetc/enetc_ethdev.c new file mode 100644 index 000000000..47e2a8ebf --- /dev/null +++ b/drivers/net/enetc/enetc_ethdev.c @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018 NXP + */ + +#include +#include + +#include "enetc_logs.h" +#include "enetc.h" + +int enetc_logtype_pmd; + +/* Functions Prototypes */ +static int enetc_dev_configure(struct rte_eth_dev *dev); +static int enetc_dev_start(struct rte_eth_dev *dev); +static void enetc_dev_stop(struct rte_eth_dev *dev); +static void enetc_dev_close(struct rte_eth_dev *dev); +static void enetc_dev_infos_get(struct rte_eth_dev *dev, + struct rte_eth_dev_info *dev_info); +static int enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete); +static int enetc_hardware_init(struct enetc_eth_hw *hw); + +/* + * The set of PCI devices this driver supports + */ +static const struct rte_pci_id pci_id_enetc_map[] = { + { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID) }, + { RTE_PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, ENETC_DEV_ID_VF) }, + { .vendor_id = 0, /* sentinel */ }, +}; + +/* Features supported by this driver */ +static const struct eth_dev_ops enetc_ops = { + .dev_configure = enetc_dev_configure, + .dev_start = enetc_dev_start, + .dev_stop = enetc_dev_stop, + .dev_close = enetc_dev_close, + .link_update = enetc_link_update, + .dev_infos_get = enetc_dev_infos_get, +}; + +/** + * Initialisation of the enetc device + * + * @param eth_dev + * - Pointer to the structure rte_eth_dev + * + * @return + * - On success, zero. + * - On failure, negative value. + */ +static int +enetc_dev_init(struct rte_eth_dev *eth_dev) +{ + int error = 0; + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private); + + PMD_INIT_FUNC_TRACE(); + eth_dev->dev_ops = &enetc_ops; + eth_dev->rx_pkt_burst = NULL; + eth_dev->tx_pkt_burst = NULL; + + /* Retrieving and storing the HW base address of device */ + hw->hw.reg = (void *)pci_dev->mem_resource[0].addr; + hw->device_id = pci_dev->id.device_id; + + error = enetc_hardware_init(hw); + if (error != 0) { + ENETC_PMD_ERR("Hardware initialization failed"); + return -1; + } + + /* Allocate memory for storing MAC addresses */ + eth_dev->data->mac_addrs = rte_zmalloc("enetc_eth", ETHER_ADDR_LEN, 0); + if (!eth_dev->data->mac_addrs) { + ENETC_PMD_ERR("Failed to allocate %d bytes needed to " + "store MAC addresses", + ETHER_ADDR_LEN * 1); + error = -ENOMEM; + return -1; + } + + /* Copy the permanent MAC address */ + ether_addr_copy((struct ether_addr *)hw->mac.addr, + ð_dev->data->mac_addrs[0]); + + ENETC_PMD_DEBUG("port_id %d vendorID=0x%x deviceID=0x%x", + eth_dev->data->port_id, pci_dev->id.vendor_id, + pci_dev->id.device_id); + return 0; +} + +static int +enetc_dev_uninit(struct rte_eth_dev *eth_dev __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); + return 0; +} + +static int +enetc_dev_configure(struct rte_eth_dev *dev __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); + return 0; +} + +static int +enetc_dev_start(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t val; + + PMD_INIT_FUNC_TRACE(); + val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, + ENETC_PM0_CMD_CFG)); + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), + val | ENETC_PM0_TX_EN | ENETC_PM0_RX_EN); + + /* Enable port */ + val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), + val | ENETC_PMR_EN); + + return 0; +} + +static void +enetc_dev_stop(struct rte_eth_dev *dev) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + uint32_t val; + + PMD_INIT_FUNC_TRACE(); + /* Disable port */ + val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR)); + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PMR), + val & (~ENETC_PMR_EN)); + + val = ENETC_REG_READ(ENETC_GET_HW_ADDR(hw->hw.port, + ENETC_PM0_CMD_CFG)); + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PM0_CMD_CFG), + val & (~(ENETC_PM0_TX_EN | ENETC_PM0_RX_EN))); +} + +static void +enetc_dev_close(struct rte_eth_dev *dev __rte_unused) +{ + PMD_INIT_FUNC_TRACE(); +} + +/* return 0 means link status changed, -1 means not changed */ +static int +enetc_link_update(struct rte_eth_dev *dev, int wait_to_complete __rte_unused) +{ + struct enetc_eth_hw *hw = + ENETC_DEV_PRIVATE_TO_HW(dev->data->dev_private); + struct rte_eth_link link; + + PMD_INIT_FUNC_TRACE(); + hw->mac.get_link_status = 1; + + memset(&link, 0, sizeof(link)); + rte_eth_linkstatus_get(dev, &link); + + link.link_duplex = ETH_LINK_FULL_DUPLEX; + link.link_status = ETH_LINK_UP; + rte_eth_linkstatus_set(dev, &link); + + return 0; +} + +static int +enetc_hardware_init(struct enetc_eth_hw *hw) +{ + uint32_t psipmr = 0; + + PMD_INIT_FUNC_TRACE(); + /* Calculating and storing the base HW addresses */ + hw->hw.port = (void *)((size_t)hw->hw.reg + ENETC_PORT_BASE); + hw->hw.global = (void *)((size_t)hw->hw.reg + ENETC_GLOBAL_BASE); + + /* Enabling Station Interface */ + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.reg, ENETC_SIMR), + ENETC_SIMR_EN); + + /* Setting to accept broadcast packets for each inetrface */ + psipmr |= ENETC_PSIPMR_SET_UP(0) | ENETC_PSIPMR_SET_MP(0) | + ENETC_PSIPMR_SET_VLAN_MP(0); + psipmr |= ENETC_PSIPMR_SET_UP(1) | ENETC_PSIPMR_SET_MP(1) | + ENETC_PSIPMR_SET_VLAN_MP(1); + psipmr |= ENETC_PSIPMR_SET_UP(2) | ENETC_PSIPMR_SET_MP(2) | + ENETC_PSIPMR_SET_VLAN_MP(2); + + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMR), + psipmr); + + /* Enabling broadcast address */ + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR0(0)), + 0xFFFFFFFF); + ENETC_REG_WRITE(ENETC_GET_HW_ADDR(hw->hw.port, ENETC_PSIPMAR1(0)), + 0xFFFF << 16); + + return 0; +} + +static void +enetc_dev_infos_get(struct rte_eth_dev *dev __rte_unused, + struct rte_eth_dev_info *dev_info) +{ + PMD_INIT_FUNC_TRACE(); + dev_info->max_rx_queues = MAX_RX_RINGS; + dev_info->max_tx_queues = MAX_TX_RINGS; + dev_info->max_rx_pktlen = 1500; +} + +static int +enetc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_probe(pci_dev, + sizeof(struct enetc_eth_adapter), + enetc_dev_init); +} + +static int +enetc_pci_remove(struct rte_pci_device *pci_dev) +{ + return rte_eth_dev_pci_generic_remove(pci_dev, enetc_dev_uninit); +} + +static struct rte_pci_driver rte_enetc_pmd = { + .id_table = pci_id_enetc_map, + .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA, + .probe = enetc_pci_probe, + .remove = enetc_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(net_enetc, rte_enetc_pmd); +RTE_PMD_REGISTER_PCI_TABLE(net_enetc, pci_id_enetc_map); +RTE_PMD_REGISTER_KMOD_DEP(net_enetc, "* vfio-pci"); + +RTE_INIT(enetc_pmd_init_log) +{ + enetc_logtype_pmd = rte_log_register("pmd.net.enetc"); + if (enetc_logtype_pmd >= 0) + rte_log_set_level(enetc_logtype_pmd, RTE_LOG_NOTICE); +} diff --git a/drivers/net/enetc/enetc_logs.h b/drivers/net/enetc/enetc_logs.h new file mode 100644 index 000000000..c8a6c0cf3 --- /dev/null +++ b/drivers/net/enetc/enetc_logs.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018 NXP + */ + +#ifndef _ENETC_LOGS_H_ +#define _ENETC_LOGS_H_ + +extern int enetc_logtype_pmd; + +#define ENETC_PMD_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, enetc_logtype_pmd, "enetc_net: " \ + fmt "\n", ##args) + +#define ENETC_PMD_DEBUG(fmt, args...) \ + rte_log(RTE_LOG_DEBUG, enetc_logtype_pmd, "enetc_net: %s(): "\ + fmt "\n", __func__, ##args) + +#define PMD_INIT_FUNC_TRACE() ENETC_PMD_DEBUG(">>") + +#define ENETC_PMD_CRIT(fmt, args...) \ + ENETC_PMD_LOG(CRIT, fmt, ## args) +#define ENETC_PMD_INFO(fmt, args...) \ + ENETC_PMD_LOG(INFO, fmt, ## args) +#define ENETC_PMD_ERR(fmt, args...) \ + ENETC_PMD_LOG(ERR, fmt, ## args) +#define ENETC_PMD_WARN(fmt, args...) \ + ENETC_PMD_LOG(WARNING, fmt, ## args) + +/* DP Logs, toggled out at compile time if level lower than current level */ +#define ENETC_PMD_DP_LOG(level, fmt, args...) \ + RTE_LOG_DP(level, PMD, fmt, ## args) + +#define ENETC_PMD_DP_DEBUG(fmt, args...) \ + ENETC_PMD_DP_LOG(DEBUG, fmt, ## args) +#define ENETC_PMD_DP_INFO(fmt, args...) \ + ENETC_PMD_DP_LOG(INFO, fmt, ## args) +#define ENETC_PMD_DP_WARN(fmt, args...) \ + ENETC_PMD_DP_LOG(WARNING, fmt, ## args) + +#endif /* _ENETC_LOGS_H_*/ diff --git a/drivers/net/enetc/meson.build b/drivers/net/enetc/meson.build new file mode 100644 index 000000000..506b174ed --- /dev/null +++ b/drivers/net/enetc/meson.build @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright 2018 NXP + +if host_machine.system() != 'linux' + build = false +endif + +sources = files('enetc_ethdev.c') + +includes += include_directories('base') diff --git a/drivers/net/enetc/rte_pmd_enetc_version.map b/drivers/net/enetc/rte_pmd_enetc_version.map new file mode 100644 index 000000000..521e51f41 --- /dev/null +++ b/drivers/net/enetc/rte_pmd_enetc_version.map @@ -0,0 +1,4 @@ +DPDK_18.11 { + + local: *; +}; diff --git a/drivers/net/meson.build b/drivers/net/meson.build index 9c28ed4da..65aa6f60c 100644 --- a/drivers/net/meson.build +++ b/drivers/net/meson.build @@ -11,6 +11,7 @@ drivers = ['af_packet', 'dpaa', 'dpaa2', 'e1000', 'ena', + 'enetc', 'enic', 'failsafe', 'fm10k', 'i40e', diff --git a/mk/rte.app.mk b/mk/rte.app.mk index de33883be..154ae3b2c 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -135,6 +135,7 @@ endif _LDLIBS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += -lrte_pmd_e1000 _LDLIBS-$(CONFIG_RTE_LIBRTE_ENA_PMD) += -lrte_pmd_ena _LDLIBS-$(CONFIG_RTE_LIBRTE_ENIC_PMD) += -lrte_pmd_enic +_LDLIBS-$(CONFIG_RTE_LIBRTE_ENETC_PMD) += -lrte_pmd_enetc _LDLIBS-$(CONFIG_RTE_LIBRTE_FM10K_PMD) += -lrte_pmd_fm10k _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_FAILSAFE) += -lrte_pmd_failsafe _LDLIBS-$(CONFIG_RTE_LIBRTE_I40E_PMD) += -lrte_pmd_i40e -- 2.17.1