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Sat, 3 Nov 2018 01:06:32 +0000 From: Yongseok Koh To: Thomas Monjalon , "bruce.richardson@intel.com" , "ferruh.yigit@intel.com" CC: "dev@dpdk.org" , Shahaf Shuler , "konstantin.ananyev@intel.com" , "anatoly.burakov@intel.com" , Yongseok Koh , "stable@dpdk.org" Thread-Topic: [PATCH v3] build: disable gcc AVX512F support Thread-Index: AQHUcxF1Bj+VPCkk40K5AI/W5u/f9g== Date: Sat, 3 Nov 2018 01:06:32 +0000 Message-ID: <20181103010623.42468-1-yskoh@mellanox.com> References: <20181023212318.43082-1-yskoh@mellanox.com> In-Reply-To: <20181023212318.43082-1-yskoh@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR01CA0065.prod.exchangelabs.com (2603:10b6:a03:94::42) To AM0PR0502MB3971.eurprd05.prod.outlook.com (2603:10a6:208:11::23) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR0502MB3908; H:AM0PR0502MB3971.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: IsJuCVw7ZYRMsRc9C8JRe9J7nJlL/qtVm9xaG59D4v01tJP/xcLy43Jno6Lx4h0dPYbQAOxS7VN6GzleXZRFHQ0awoFOvAk2sGAUDmu3JvVw1XV5neZBerD4NZmJe7QFy4zr80c3atlu9n8qNgqeaV/3H5Ia6By4oH4Lo8wFViicCynrmYEhji9xzGN3II/3pRAibGbB9YwSjC9iV9s33WAxYLAl2LtPfZPrLsLtBAw3jifYNJbdeVqHwpLrJ0+gfp6X5nsduP+vIb9q/uB/REl/NlesdCUbOpEh0VwQKAySQo+C8J+yBbUVeZzNYpHlhN8tTGSKNLLUNPHJ63h/Qg+zg5DGO7Pi24NGT9Ai6BI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: fc60263b-a6c5-40ad-efd0-08d64128976a X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Nov 2018 01:06:32.1283 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR0502MB3908 Subject: [dpdk-dev] [PATCH v3] build: disable gcc AVX512F support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Nov 2018 01:06:45 -0000 This is a workaround to prevent a crash, which might be caused by optimization of newer gcc (7.3.0) on Intel Skylake. This disables AVX512F support of gcc by adding -mno-avx512f if it is disabled in DPDK (CONFIG_RTE_ENABLE_AVX512=3Dn). This does not apply to the meson build as that doesn't have such an option but always enable AVX512F whenever supported. Bugzilla ID: 97 Cc: stable@dpdk.org Signed-off-by: Yongseok Koh --- v3: * use AUTO_CPUFLAGS instead of redundant check for gcc * remove the change from meson build v2: * disable the flag only in case of gcc mk/rte.cpuflags.mk | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/mk/rte.cpuflags.mk b/mk/rte.cpuflags.mk index 43ed84155b..c3291b17a1 100644 --- a/mk/rte.cpuflags.mk +++ b/mk/rte.cpuflags.mk @@ -68,6 +68,11 @@ endif ifneq ($(filter $(AUTO_CPUFLAGS),__AVX512F__),) ifeq ($(CONFIG_RTE_ENABLE_AVX512),y) CPUFLAGS +=3D AVX512F +else +# disable AVX512F support of gcc as a workaround for Bug 97 +ifeq ($(CONFIG_RTE_TOOLCHAIN_GCC),y) +MACHINE_CFLAGS +=3D -mno-avx512f +endif endif endif =20 --=20 2.11.0