From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.droids-corp.org (zoll.droids-corp.org [94.23.50.67]) by dpdk.org (Postfix) with ESMTP id 2909B548B; Mon, 5 Nov 2018 10:30:58 +0100 (CET) Received: from rsa59-2-82-233-193-189.fbx.proxad.net ([82.233.193.189] helo=droids-corp.org) by mail.droids-corp.org with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:256) (Exim 4.89) (envelope-from ) id 1gJbEv-0003kF-LH; Mon, 05 Nov 2018 10:32:11 +0100 Received: by droids-corp.org (sSMTP sendmail emulation); Mon, 05 Nov 2018 10:30:45 +0100 Date: Mon, 5 Nov 2018 10:30:45 +0100 From: Olivier Matz To: Gavin Hu Cc: dev@dpdk.org, thomas@monjalon.net, stephen@networkplumber.org, chaozhu@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, jerin.jacob@caviumnetworks.com, Honnappa.Nagarahalli@arm.com, stable@dpdk.org Message-ID: <20181105093045.lj6i4rx7ao3nlowk@platinum> References: <1541066031-29125-1-git-send-email-gavin.hu@arm.com> <1541157688-40012-2-git-send-email-gavin.hu@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1541157688-40012-2-git-send-email-gavin.hu@arm.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [dpdk-dev] [PATCH v5 1/2] ring: synchronize the load and store of the tail X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Nov 2018 09:30:58 -0000 On Fri, Nov 02, 2018 at 07:21:27PM +0800, Gavin Hu wrote: > Synchronize the load-acquire of the tail and the store-release > within update_tail, the store release ensures all the ring operations, > enqueue or dequeue, are seen by the observers on the other side as soon > as they see the updated tail. The load-acquire is needed here as the > data dependency is not a reliable way for ordering as the compiler might > break it by saving to temporary values to boost performance. > When computing the free_entries and avail_entries, use atomic semantics > to load the heads and tails instead. > > The patch was benchmarked with test/ring_perf_autotest and it decreases > the enqueue/dequeue latency by 5% ~ 27.6% with two lcores, the real gains > are dependent on the number of lcores, depth of the ring, SPSC or MPMC. > For 1 lcore, it also improves a little, about 3 ~ 4%. > It is a big improvement, in case of MPMC, with two lcores and ring size > of 32, it saves latency up to (3.26-2.36)/3.26 = 27.6%. > > This patch is a bug fix, while the improvement is a bonus. In our analysis > the improvement comes from the cacheline pre-filling after hoisting load- > acquire from _atomic_compare_exchange_n up above. > > The test command: > $sudo ./test/test/test -l 16-19,44-47,72-75,100-103 -n 4 --socket-mem=\ > 1024 -- -i > > Test result with this patch(two cores): > SP/SC bulk enq/dequeue (size: 8): 5.86 > MP/MC bulk enq/dequeue (size: 8): 10.15 > SP/SC bulk enq/dequeue (size: 32): 1.94 > MP/MC bulk enq/dequeue (size: 32): 2.36 > > In comparison of the test result without this patch: > SP/SC bulk enq/dequeue (size: 8): 6.67 > MP/MC bulk enq/dequeue (size: 8): 13.12 > SP/SC bulk enq/dequeue (size: 32): 2.04 > MP/MC bulk enq/dequeue (size: 32): 3.26 > > Fixes: 39368ebfc6 ("ring: introduce C11 memory model barrier option") > Cc: stable@dpdk.org > > Signed-off-by: Gavin Hu > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Steve Capper > Reviewed-by: Ola Liljedahl > Reviewed-by: Jia He > Acked-by: Jerin Jacob > Tested-by: Jerin Jacob Acked-by: Olivier Matz