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Thu, 15 Nov 2018 10:29:19 +0000 From: Yongseok Koh To: Shahaf Shuler CC: "dev@dpdk.org" , Yongseok Koh , "stable@dpdk.org" Thread-Topic: [PATCH 3/4] net/mlx5: optimize Tx doorbell write Thread-Index: AQHUfM4Qa+rvfHCNUUiUI1OyUjCB7A== Date: Thu, 15 Nov 2018 10:29:19 +0000 Message-ID: <20181115102859.10928-3-yskoh@mellanox.com> References: <20181115102859.10928-1-yskoh@mellanox.com> In-Reply-To: <20181115102859.10928-1-yskoh@mellanox.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR05CA0019.namprd05.prod.outlook.com (2603:10b6:a03:c0::32) To DB3PR0502MB3980.eurprd05.prod.outlook.com (2603:10a6:8:10::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=yskoh@mellanox.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [209.116.155.178] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DB3PR0502MB3963; 6:yhzvCcc0DXHBfDoJtdZJf8YkCyB3XMsUWn4lMMDPiNbyTuzvKQSVeK1OQ2Pg+huC+ICY7UngsHzO/FbVM78cFd0gS83s44DdmF0xJpbwR6bxSdI7834T3NErw2We95GLs2xfIePQ2PyEc2N/T1qEQlyLS2qrFyFEQ0HNZcK6X8Oj2twS8dYvWW/u121NNgq3jAQrlpZTkmphnjK21vNizQrBMJnS06XVbd/SH2EA1l25BhwCR2hbzo+5+rKUSAzoe5jv+OOk5rxzrhLnglpZiK8b/SSmcsOKb+YmZO6GEZ7uyNbIL9K+bljvhtahlWXBUmALj1qIRwBK8NngY65XF96QwiYp/VZrq8/Ob24GXodVxBB1qF4eg/YOmlwy/tk8C1+GZFCB4nk2mS0FFWdlvPSXcpEuYPZp6bNuugQS4fJ5UFx/MFWUz5ta7Fz85Z6GsCrnVpYqZwpeBseC+MHmnA==; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: ca960453-5784-466e-cf14-08d64ae53354 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Nov 2018 10:29:19.1166 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB3963 Subject: [dpdk-dev] [PATCH 3/4] net/mlx5: optimize Tx doorbell write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Nov 2018 10:29:20 -0000 Unnecessary volatile attribute keeps compiler from further optimizing the code and this results in a little performance drop (~2%). Because of memory barriers, it is safe to remove. Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh --- drivers/net/mlx5/mlx5_rxtx.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 59fb43fefe..e210453fe0 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -379,17 +379,16 @@ uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *= txq, uintptr_t addr, * Address of the lock to use for that UAR access. */ static __rte_always_inline void -__mlx5_uar_write64_relaxed(uint64_t val, volatile void *addr, +__mlx5_uar_write64_relaxed(uint64_t val, void *addr, rte_spinlock_t *lock __rte_unused) { #ifdef RTE_ARCH_64 - rte_write64_relaxed(val, addr); + *(uint64_t *)addr =3D val; #else /* !RTE_ARCH_64 */ rte_spinlock_lock(lock); - rte_write32_relaxed(val, addr); + *(uint32_t *)addr =3D val; rte_io_wmb(); - rte_write32_relaxed(val >> 32, - (volatile void *)((volatile char *)addr + 4)); + *((uint32_t *)addr + 1) =3D val >> 32; rte_spinlock_unlock(lock); #endif } @@ -407,7 +406,7 @@ __mlx5_uar_write64_relaxed(uint64_t val, volatile void = *addr, * Address of the lock to use for that UAR access. */ static __rte_always_inline void -__mlx5_uar_write64(uint64_t val, volatile void *addr, rte_spinlock_t *lock= ) +__mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) { rte_io_wmb(); __mlx5_uar_write64_relaxed(val, addr, lock); --=20 2.11.0