From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by dpdk.org (Postfix) with ESMTP id BAD1B1B93B for ; Wed, 19 Dec 2018 17:10:51 +0100 (CET) Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 15FF6A04AD; Wed, 19 Dec 2018 16:10:51 +0000 (UTC) Received: from redhat.com (ovpn-120-67.rdu2.redhat.com [10.10.120.67]) by smtp.corp.redhat.com (Postfix) with SMTP id 56BA168D21; Wed, 19 Dec 2018 16:10:45 +0000 (UTC) Date: Wed, 19 Dec 2018 11:10:44 -0500 From: "Michael S. Tsirkin" To: Maxime Coquelin Cc: Ilya Maximets , dev@dpdk.org, tiwei.bie@intel.com, zhihong.wang@intel.com, jfreimann@redhat.com, Jason Wang Message-ID: <20181219110010-mutt-send-email-mst@kernel.org> References: <20181212082403.12002-1-maxime.coquelin@redhat.com> <20181212134459-mutt-send-email-mst@kernel.org> <003a5fbb-386f-2cf6-e83d-abd7b9fc2938@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <003a5fbb-386f-2cf6-e83d-abd7b9fc2938@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Wed, 19 Dec 2018 16:10:51 +0000 (UTC) Subject: Re: [dpdk-dev] [PATCH] vhost: batch used descriptors chains write-back with packed ring X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Dec 2018 16:10:52 -0000 On Wed, Dec 19, 2018 at 10:16:24AM +0100, Maxime Coquelin wrote: > > > On 12/12/18 7:53 PM, Michael S. Tsirkin wrote: > > On Wed, Dec 12, 2018 at 05:34:31PM +0100, Maxime Coquelin wrote: > > > Hi Ilya, > > > > > > On 12/12/18 4:23 PM, Ilya Maximets wrote: > > > > On 12.12.2018 11:24, Maxime Coquelin wrote: > > > > > Instead of writing back descriptors chains in order, let's > > > > > write the first chain flags last in order to improve batching. > > > > > > > > > > With Kernel's pktgen benchmark, ~3% performance gain is measured. > > > > > > > > > > Signed-off-by: Maxime Coquelin > > > > > --- > > > > > lib/librte_vhost/virtio_net.c | 39 +++++++++++++++++++++-------------- > > > > > 1 file changed, 24 insertions(+), 15 deletions(-) > > > > > > > > > > > > > Hi. > > > > I made some rough testing on my ARMv8 system with this patch and v1 of it. > > > > Here is the performance difference with current master: > > > > v1: +1.1 % > > > > v2: -3.6 % > > > > > > > > So, write barriers are quiet heavy in practice. > > > > > > Thanks for testing it on ARM. Indeed, SMP WMB is heavier on ARM. > > > > Besides your ideas for improving packed rings, maybe we should switch to > > load_acquite/store_release? > > > > See > > virtio: use smp_load_acquire/smp_store_release > > > > which worked fine but as I only tested on x86 did not result in any gains. > > > > Thanks for the pointer. > We'll look into it for v19.05, as -rc1 for v19.02 is planned for end of > week, so it will be too late to introduce such changes. > > Regards, > Maxime That's not the only option BTW. For loads, another option it to work the value into an indirect dependency which does not need a barrier. For example: #define OPTIMIZER_HIDE_VAR(var) \ __asm__ ("" : "=r" (var) : "0" (var)) unsigned empty = last_used == idx->used; if (!empty) { OPTIMIZER_HIDE_VAR(empty); desc = used->ring[last_used + empty]; } See linux for definitions of OPTIMIZER_HIDE_VAR. One side effect of this is that this also blocks code speculation. which can be a good or a bad thing for performance, but can be a good thing for security. -- MST