[dpdk-dev] [PATCH 1/7] net/ice/base: code clean

[Qi Zhang <qi.z.zhang@intel.com>]

Remove some unnecessary code.

Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
---
 drivers/net/ice/base/ice_common.c   | 14 --------------
 drivers/net/ice/base/ice_common.h   | 17 -----------------
 drivers/net/ice/base/ice_controlq.c |  2 +-
 3 files changed, 1 insertion(+), 32 deletions(-)

diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c
index d49264d14..2ccf58527 100644
--- a/drivers/net/ice/base/ice_common.c
+++ b/drivers/net/ice/base/ice_common.c
@@ -60,16 +60,6 @@ static enum ice_status ice_set_mac_type(struct ice_hw *hw)
 	return status;
 }
 
-#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)
-void ice_dev_onetime_setup(struct ice_hw *hw)
-{
-	/* configure Rx - set non pxe mode */
-	wr32(hw, GLLAN_RCTL_0, 0x1);
-
-
-
-}
-#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */
 
 /**
  * ice_clear_pf_cfg - Clear PF configuration
@@ -830,10 +820,6 @@ enum ice_status ice_init_hw(struct ice_hw *hw)
 	if (status)
 		goto err_unroll_sched;
 
-#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)
-	/* some of the register write workarounds to get Rx working */
-	ice_dev_onetime_setup(hw);
-#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */
 
 	/* Get MAC information */
 	/* A single port can report up to two (LAN and WoL) addresses */
diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h
index 082ae66f9..0197fbfe3 100644
--- a/drivers/net/ice/base/ice_common.h
+++ b/drivers/net/ice/base/ice_common.h
@@ -9,18 +9,6 @@
 
 #include "ice_switch.h"
 
-/* prototype for functions used for SW locks */
-void ice_free_list(struct LIST_HEAD_TYPE *list);
-void ice_init_lock(struct ice_lock *lock);
-void ice_acquire_lock(struct ice_lock *lock);
-void ice_release_lock(struct ice_lock *lock);
-void ice_destroy_lock(struct ice_lock *lock);
-
-void *ice_alloc_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m, u64 size);
-void ice_free_dma_mem(struct ice_hw *hw, struct ice_dma_mem *m);
-
-bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq);
-
 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
 
 void
@@ -61,11 +49,6 @@ enum ice_status ice_get_caps(struct ice_hw *hw);
 
 
 
-#if defined(FPGA_SUPPORT) || defined(CVL_A0_SUPPORT)
-void ice_dev_onetime_setup(struct ice_hw *hw);
-#endif /* FPGA_SUPPORT || CVL_A0_SUPPORT */
-
-
 enum ice_status
 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
 		  u32 rxq_index);
diff --git a/drivers/net/ice/base/ice_controlq.c b/drivers/net/ice/base/ice_controlq.c
index fb82c23ee..cbc4cb4c2 100644
--- a/drivers/net/ice/base/ice_controlq.c
+++ b/drivers/net/ice/base/ice_controlq.c
@@ -735,7 +735,7 @@ static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
  * Returns true if the firmware has processed all descriptors on the
  * admin send queue. Returns false if there are still requests pending.
  */
-bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
+static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
 {
 	/* AQ designers suggest use of head for better
 	 * timing reliability than DD bit
-- 
2.13.6