From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id CC75DA3 for ; Thu, 17 Jan 2019 16:38:05 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jan 2019 07:38:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,489,1539673200"; d="scan'208";a="139112040" Received: from txasoft-yocto.an.intel.com (HELO txasoft-yocto.an.intel.com.) ([10.123.72.192]) by fmsmga001.fm.intel.com with ESMTP; 17 Jan 2019 07:38:03 -0800 From: Gage Eads To: dev@dpdk.org Cc: olivier.matz@6wind.com, arybchenko@solarflare.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, gavin.hu@arm.com Date: Thu, 17 Jan 2019 09:36:58 -0600 Message-Id: <20190117153659.28477-2-gage.eads@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20190117153659.28477-1-gage.eads@intel.com> References: <20190116151835.22424-1-gage.eads@intel.com> <20190117153659.28477-1-gage.eads@intel.com> Subject: [dpdk-dev] [PATCH v4 1/2] eal: add 128-bit cmpset (x86-64 only) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Jan 2019 15:38:06 -0000 This operation can be used for non-blocking algorithms, such as a non-blocking stack or ring. Signed-off-by: Gage Eads --- .../common/include/arch/x86/rte_atomic_64.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h index fd2ec9c53..34c2addf8 100644 --- a/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h +++ b/lib/librte_eal/common/include/arch/x86/rte_atomic_64.h @@ -34,6 +34,7 @@ /* * Inspired from FreeBSD src/sys/amd64/include/atomic.h * Copyright (c) 1998 Doug Rabson + * Copyright (c) 2019 Intel Corporation * All rights reserved. */ @@ -208,4 +209,25 @@ static inline void rte_atomic64_clear(rte_atomic64_t *v) } #endif +static inline int +rte_atomic128_cmpset(volatile uint64_t *dst, uint64_t *exp, uint64_t *src) +{ + uint8_t res; + + asm volatile ( + MPLOCKED + "cmpxchg16b %[dst];" + " sete %[res]" + : [dst] "=m" (*dst), + [res] "=r" (res) + : "c" (src[1]), + "b" (src[0]), + "m" (*dst), + "d" (exp[1]), + "a" (exp[0]) + : "memory"); + + return res; +} + #endif /* _RTE_ATOMIC_X86_64_H_ */ -- 2.13.6