From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.tetrasec.net (mx1.tetrasec.net [74.117.190.25]) by dpdk.org (Postfix) with ESMTP id 7CCA8239 for ; Tue, 12 Mar 2019 11:18:49 +0100 (CET) Received: from mx1.tetrasec.net (mail.local [127.0.0.1]) by mx1.tetrasec.net (Postfix) with ESMTP id 839479E0455; Tue, 12 Mar 2019 10:18:48 +0000 (UTC) Received: from ncopa-desktop.lan (67.63.200.37.customer.cdi.no [37.200.63.67]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: n@tanael.org) by mx1.tetrasec.net (Postfix) with ESMTPSA id A787E9E0026; Tue, 12 Mar 2019 10:18:47 +0000 (UTC) From: Natanael Copa To: dev@dpdk.org Cc: Natanael Copa Date: Tue, 12 Mar 2019 11:18:36 +0100 Message-Id: <20190312101836.18447-1-ncopa@alpinelinux.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190311173702.24471-5-ncopa@alpinelinux.org> References: <20190311173702.24471-5-ncopa@alpinelinux.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Subject: [dpdk-dev] [PATCH v2 04/15] bus/pci: factor out various ifdefs in pci_uio_ioport_{read, write} X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Mar 2019 10:18:49 -0000 define the macros so we can remove various #if defined(RTE_ARCH_X86) Ref: https://bugs.dpdk.org/show_bug.cgi?id=3D35#c6 Signed-off-by: Natanael Copa --- v1 -> v2 fixed coding style issues reported by checkpatch drivers/bus/pci/linux/pci_uio.c | 54 +++++++++++++++------------------ 1 file changed, 24 insertions(+), 30 deletions(-) diff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_= uio.c index e1dd8c875..b0470358d 100644 --- a/drivers/bus/pci/linux/pci_uio.c +++ b/drivers/bus/pci/linux/pci_uio.c @@ -14,11 +14,18 @@ =20 #if defined(RTE_ARCH_X86) #include + +#define pci_uio_inl(reg) inl(reg) +#define pci_uio_inw(reg) inw(reg) +#define pci_uio_inb(reg) inb(reg) + #if defined(__GLIBC__) + #define pci_uio_outl_p outl_p #define pci_uio_outw_p outw_p #define pci_uio_outb_p outb_p -#else + +#else /* defined(__GLIBC__) */ static inline void pci_uio_outl_p(unsigned int value, unsigned short int port) { @@ -39,8 +46,19 @@ pci_uio_outb_p(unsigned char value, unsigned short int= port) __asm__ __volatile__ ("outb %b0,%w1\noutb %%al,$0x80" : : "a" (value), "Nd" (port)); } -#endif -#endif +#endif /* defined(__GLIBC__) */ + +#else /* RTE_ARCH_X86 */ + +#define pci_uio_inl(reg) (*(volatile uint32_t *)(reg)) +#define pci_uio_inw(reg) (*(volatile uint16_t *)(reg)) +#define pci_uio_inb(reg) (*(volatile uint8_t *)(reg)) + +#define pci_uio_outl_p(value, reg) (*(volatile uint32_t *)(reg) =3D (val= ue)) +#define pci_uio_outw_p(value, reg) (*(volatile uint16_t *)(reg) =3D (val= ue)) +#define pci_uio_outb_p(value, reg) (*(volatile uint8_t *)(reg) =3D (valu= e)) + +#endif /* RTE_ARCH_X86 */ =20 #include #include @@ -518,25 +536,13 @@ pci_uio_ioport_read(struct rte_pci_ioport *p, for (d =3D data; len > 0; d +=3D size, reg +=3D size, len -=3D size) { if (len >=3D 4) { size =3D 4; -#if defined(RTE_ARCH_X86) - *(uint32_t *)d =3D inl(reg); -#else - *(uint32_t *)d =3D *(volatile uint32_t *)reg; -#endif + *(uint32_t *)d =3D pci_uio_inl(reg); } else if (len >=3D 2) { size =3D 2; -#if defined(RTE_ARCH_X86) - *(uint16_t *)d =3D inw(reg); -#else - *(uint16_t *)d =3D *(volatile uint16_t *)reg; -#endif + *(uint16_t *)d =3D pci_uio_inw(reg); } else { size =3D 1; -#if defined(RTE_ARCH_X86) - *d =3D inb(reg); -#else - *d =3D *(volatile uint8_t *)reg; -#endif + *d =3D pci_uio_inb(reg); } } } @@ -552,25 +558,13 @@ pci_uio_ioport_write(struct rte_pci_ioport *p, for (s =3D data; len > 0; s +=3D size, reg +=3D size, len -=3D size) { if (len >=3D 4) { size =3D 4; -#if defined(RTE_ARCH_X86) pci_uio_outl_p(*(const uint32_t *)s, reg); -#else - *(volatile uint32_t *)reg =3D *(const uint32_t *)s; -#endif } else if (len >=3D 2) { size =3D 2; -#if defined(RTE_ARCH_X86) pci_uio_outw_p(*(const uint16_t *)s, reg); -#else - *(volatile uint16_t *)reg =3D *(const uint16_t *)s; -#endif } else { size =3D 1; -#if defined(RTE_ARCH_X86) pci_uio_outb_p(*s, reg); -#else - *(volatile uint8_t *)reg =3D *s; -#endif } } } --=20 2.21.0