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Thu, 14 Mar 2019 14:22:32 +0000 From: Jerin Jacob Kollanukkaran To: Gavin Hu CC: "dev@dpdk.org" , "nd@arm.com" , "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , "nipun.gupta@nxp.com" , "Honnappa.Nagarahalli@arm.com" , "i.maximets@samsung.com" , "chaozhu@linux.vnet.ibm.com" , "stable@dpdk.org" Thread-Topic: [EXT] [PATCH v8 3/3] spinlock: reimplement with atomic one-way barrier builtins Thread-Index: AQHU1YSJmx87sBuVNEKqZcZOtIR4ZKYLN6YA Date: Thu, 14 Mar 2019 14:22:31 +0000 Message-ID: <20190314142224.GA10102@dc5-eodlnx05.marvell.com> References: <20181220104246.5590-1-gavin.hu@arm.com> <1552031797-146710-4-git-send-email-gavin.hu@arm.com> In-Reply-To: <1552031797-146710-4-git-send-email-gavin.hu@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BY5PR13CA0005.namprd13.prod.outlook.com (2603:10b6:a03:180::18) To BYAPR18MB2424.namprd18.prod.outlook.com (2603:10b6:a03:130::21) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [199.233.59.128] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: de8a360c-ce2c-454f-0419-08d6a8887ed4 x-microsoft-antispam: BCL:0; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: QagQ0bGrT976f3hTCDpFcMDQkGkjYDDZr0PUP9mmi/TiyXh+sA+KpSXxSbasongRqtF9dtI5TdFgtUt8Qo6kTkydyNTe2Lzg2EyuOaqdxEbTvGzucX3q2FfL16sSP02CrmwYVZQnL7ljIHNtaYU+s0LXMaKYS3hkzdDwCYNx2B+hXY16Iwuh0CBvi9DyaQQ2CFhFWYvH7le9+94h4Lkk7K6kZ8OYpByOfwGKaiNfNSHAfB8DnFCdK0zGfINw3Cmx1z7DFMho+Jh8GIqH37TwlocQxchuvzfojILiEMxhUGiMyvRQCR98sooK/AM+WXVrFimIKlFEGME60Cc3gDF3pnx54PUO4d1g/SjmM3rFVnTS4ig8ROEubsU++xcCOGt/l4XgN/aK/hM/iCxwH6Zhk9/osV0gnG289o8V12UmsWg= Content-Type: text/plain; charset="us-ascii" Content-ID: <47E783601067A04F9A297D288CCE4A1F@namprd18.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: de8a360c-ce2c-454f-0419-08d6a8887ed4 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Mar 2019 14:22:31.9788 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2885 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-14_06:, , signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v8 3/3] spinlock: reimplement with atomic one-way barrier builtins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Mar 2019 14:22:42 -0000 On Fri, Mar 08, 2019 at 03:56:37PM +0800, Gavin Hu wrote: > External Email >=20 > ---------------------------------------------------------------------- > The __sync builtin based implementation generates full memory barriers > ('dmb ish') on Arm platforms. Using C11 atomic builtins to generate one w= ay > barriers. >=20 > Here is the assembly code of __sync_compare_and_swap builtin. > __sync_bool_compare_and_swap(dst, exp, src); > 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8] > 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6] > 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4] > 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff > 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0] > 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1 > 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4 > // b.any > 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0] > 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0 > > 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish > 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq =3D non= e >=20 > The benchmarking results showed constant improvements on all available > platforms: > 1. Cavium ThunderX2: 126% performance; > 2. Hisilicon 1616: 30%; > 3. Qualcomm Falkor: 13%; > 4. Marvell ARMADA 8040 with A72 cores on macchiatobin: 3.7% >=20 > Here is the example test result on TX2: > $sudo ./build/app/test -l 16-27 -- i > RTE>>spinlock_autotest >=20 > *** spinlock_autotest without this patch *** > Test with lock on 12 cores... > Core [16] Cost Time =3D 53886 us > Core [17] Cost Time =3D 53605 us > Core [18] Cost Time =3D 53163 us > Core [19] Cost Time =3D 49419 us > Core [20] Cost Time =3D 34317 us > Core [21] Cost Time =3D 53408 us > Core [22] Cost Time =3D 53970 us > Core [23] Cost Time =3D 53930 us > Core [24] Cost Time =3D 53283 us > Core [25] Cost Time =3D 51504 us > Core [26] Cost Time =3D 50718 us > Core [27] Cost Time =3D 51730 us > Total Cost Time =3D 612933 us >=20 > *** spinlock_autotest with this patch *** > Test with lock on 12 cores... > Core [16] Cost Time =3D 18808 us > Core [17] Cost Time =3D 29497 us > Core [18] Cost Time =3D 29132 us > Core [19] Cost Time =3D 26150 us > Core [20] Cost Time =3D 21892 us > Core [21] Cost Time =3D 24377 us > Core [22] Cost Time =3D 27211 us > Core [23] Cost Time =3D 11070 us > Core [24] Cost Time =3D 29802 us > Core [25] Cost Time =3D 15793 us > Core [26] Cost Time =3D 7474 us > Core [27] Cost Time =3D 29550 us > Total Cost Time =3D 270756 us >=20 > In the tests on ThunderX2, with more cores contending, the performance ga= in > was even higher, indicating the __atomic implementation scales up better > than __sync. >=20 > Fixes: af75078fece3 ("first public release") > Cc: stable@dpdk.org >=20 > Signed-off-by: Gavin Hu > Reviewed-by: Phil Yang > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Ola Liljedahl > Reviewed-by: Steve Capper Reviewed-by: Jerin Jacob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 15C50A0096 for ; Thu, 14 Mar 2019 15:22:44 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5E2013572; Thu, 14 Mar 2019 15:22:43 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 8EC3E201; Thu, 14 Mar 2019 15:22:42 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x2EEK4tr012443; Thu, 14 Mar 2019 07:22:39 -0700 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-0016f401.pphosted.com with ESMTP id 2r7j0n1gae-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Mar 2019 07:22:39 -0700 Received: from m0045851.ppops.net (m0045851.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.27/8.16.0.27) with SMTP id x2EEMc5M014405; Thu, 14 Mar 2019 07:22:38 -0700 Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2r7j0n1gac-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); 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Thu, 14 Mar 2019 14:22:32 +0000 Received: from BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2cce:b981:61da:f92b]) by BYAPR18MB2424.namprd18.prod.outlook.com ([fe80::2cce:b981:61da:f92b%2]) with mapi id 15.20.1709.011; Thu, 14 Mar 2019 14:22:32 +0000 From: Jerin Jacob Kollanukkaran To: Gavin Hu CC: "dev@dpdk.org" , "nd@arm.com" , "thomas@monjalon.net" , "hemant.agrawal@nxp.com" , "nipun.gupta@nxp.com" , "Honnappa.Nagarahalli@arm.com" , "i.maximets@samsung.com" , "chaozhu@linux.vnet.ibm.com" , "stable@dpdk.org" Thread-Topic: [EXT] [PATCH v8 3/3] spinlock: reimplement with atomic one-way barrier builtins Thread-Index: AQHU1YSJmx87sBuVNEKqZcZOtIR4ZKYLN6YA Date: Thu, 14 Mar 2019 14:22:31 +0000 Message-ID: <20190314142224.GA10102@dc5-eodlnx05.marvell.com> References: <20181220104246.5590-1-gavin.hu@arm.com> <1552031797-146710-4-git-send-email-gavin.hu@arm.com> In-Reply-To: <1552031797-146710-4-git-send-email-gavin.hu@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BY5PR13CA0005.namprd13.prod.outlook.com (2603:10b6:a03:180::18) To BYAPR18MB2424.namprd18.prod.outlook.com (2603:10b6:a03:130::21) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [199.233.59.128] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: de8a360c-ce2c-454f-0419-08d6a8887ed4 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600127)(711020)(4605104)(2017052603328)(7153060)(7193020); SRVR:BYAPR18MB2885; x-ms-traffictypediagnostic: BYAPR18MB2885: x-microsoft-antispam-prvs: x-forefront-prvs: 09760A0505 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(979002)(136003)(366004)(39860400002)(396003)(376002)(346002)(199004)(189003)(14454004)(26005)(102836004)(229853002)(25786009)(6506007)(3846002)(7736002)(86362001)(7416002)(446003)(11346002)(6116002)(6246003)(386003)(81156014)(2906002)(81166006)(33656002)(8676002)(52116002)(4326008)(305945005)(99286004)(186003)(76176011)(1076003)(6486002)(256004)(6436002)(478600001)(97736004)(68736007)(66066001)(14444005)(71200400001)(6916009)(6512007)(8936002)(106356001)(5660300002)(476003)(53936002)(316002)(71190400001)(105586002)(54906003)(486006)(969003)(989001)(999001)(1009001)(1019001); DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2885; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: QagQ0bGrT976f3hTCDpFcMDQkGkjYDDZr0PUP9mmi/TiyXh+sA+KpSXxSbasongRqtF9dtI5TdFgtUt8Qo6kTkydyNTe2Lzg2EyuOaqdxEbTvGzucX3q2FfL16sSP02CrmwYVZQnL7ljIHNtaYU+s0LXMaKYS3hkzdDwCYNx2B+hXY16Iwuh0CBvi9DyaQQ2CFhFWYvH7le9+94h4Lkk7K6kZ8OYpByOfwGKaiNfNSHAfB8DnFCdK0zGfINw3Cmx1z7DFMho+Jh8GIqH37TwlocQxchuvzfojILiEMxhUGiMyvRQCR98sooK/AM+WXVrFimIKlFEGME60Cc3gDF3pnx54PUO4d1g/SjmM3rFVnTS4ig8ROEubsU++xcCOGt/l4XgN/aK/hM/iCxwH6Zhk9/osV0gnG289o8V12UmsWg= Content-Type: text/plain; charset="UTF-8" Content-ID: <47E783601067A04F9A297D288CCE4A1F@namprd18.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: de8a360c-ce2c-454f-0419-08d6a8887ed4 X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Mar 2019 14:22:31.9788 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2885 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-14_06:, , signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH v8 3/3] spinlock: reimplement with atomic one-way barrier builtins X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190314142231.QsYGcIA2Jyp9k8qF7Z7qMZFwPTpUiErs_zQ1iDMiPx4@z> On Fri, Mar 08, 2019 at 03:56:37PM +0800, Gavin Hu wrote: > External Email >=20 > ---------------------------------------------------------------------- > The __sync builtin based implementation generates full memory barriers > ('dmb ish') on Arm platforms. Using C11 atomic builtins to generate one w= ay > barriers. >=20 > Here is the assembly code of __sync_compare_and_swap builtin. > __sync_bool_compare_and_swap(dst, exp, src); > 0x000000000090f1b0 <+16>: e0 07 40 f9 ldr x0, [sp, #8] > 0x000000000090f1b4 <+20>: e1 0f 40 79 ldrh w1, [sp, #6] > 0x000000000090f1b8 <+24>: e2 0b 40 79 ldrh w2, [sp, #4] > 0x000000000090f1bc <+28>: 21 3c 00 12 and w1, w1, #0xffff > 0x000000000090f1c0 <+32>: 03 7c 5f 48 ldxrh w3, [x0] > 0x000000000090f1c4 <+36>: 7f 00 01 6b cmp w3, w1 > 0x000000000090f1c8 <+40>: 61 00 00 54 b.ne 0x90f1d4 > // b.any > 0x000000000090f1cc <+44>: 02 fc 04 48 stlxrh w4, w2, [x0] > 0x000000000090f1d0 <+48>: 84 ff ff 35 cbnz w4, 0x90f1c0 > > 0x000000000090f1d4 <+52>: bf 3b 03 d5 dmb ish > 0x000000000090f1d8 <+56>: e0 17 9f 1a cset w0, eq // eq =3D non= e >=20 > The benchmarking results showed constant improvements on all available > platforms: > 1. Cavium ThunderX2: 126% performance; > 2. Hisilicon 1616: 30%; > 3. Qualcomm Falkor: 13%; > 4. Marvell ARMADA 8040 with A72 cores on macchiatobin: 3.7% >=20 > Here is the example test result on TX2: > $sudo ./build/app/test -l 16-27 -- i > RTE>>spinlock_autotest >=20 > *** spinlock_autotest without this patch *** > Test with lock on 12 cores... > Core [16] Cost Time =3D 53886 us > Core [17] Cost Time =3D 53605 us > Core [18] Cost Time =3D 53163 us > Core [19] Cost Time =3D 49419 us > Core [20] Cost Time =3D 34317 us > Core [21] Cost Time =3D 53408 us > Core [22] Cost Time =3D 53970 us > Core [23] Cost Time =3D 53930 us > Core [24] Cost Time =3D 53283 us > Core [25] Cost Time =3D 51504 us > Core [26] Cost Time =3D 50718 us > Core [27] Cost Time =3D 51730 us > Total Cost Time =3D 612933 us >=20 > *** spinlock_autotest with this patch *** > Test with lock on 12 cores... > Core [16] Cost Time =3D 18808 us > Core [17] Cost Time =3D 29497 us > Core [18] Cost Time =3D 29132 us > Core [19] Cost Time =3D 26150 us > Core [20] Cost Time =3D 21892 us > Core [21] Cost Time =3D 24377 us > Core [22] Cost Time =3D 27211 us > Core [23] Cost Time =3D 11070 us > Core [24] Cost Time =3D 29802 us > Core [25] Cost Time =3D 15793 us > Core [26] Cost Time =3D 7474 us > Core [27] Cost Time =3D 29550 us > Total Cost Time =3D 270756 us >=20 > In the tests on ThunderX2, with more cores contending, the performance ga= in > was even higher, indicating the __atomic implementation scales up better > than __sync. >=20 > Fixes: af75078fece3 ("first public release") > Cc: stable@dpdk.org >=20 > Signed-off-by: Gavin Hu > Reviewed-by: Phil Yang > Reviewed-by: Honnappa Nagarahalli > Reviewed-by: Ola Liljedahl > Reviewed-by: Steve Capper Reviewed-by: Jerin Jacob