From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 76976A05D3 for ; Mon, 25 Mar 2019 20:13:18 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6E1092BFA; Mon, 25 Mar 2019 20:13:17 +0100 (CET) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id 6235510A3 for ; Mon, 25 Mar 2019 20:13:15 +0100 (CET) Received: from Internal Mail-Server by MTLPINE1 (envelope-from yskoh@mellanox.com) with ESMTPS (AES256-SHA encrypted); 25 Mar 2019 21:13:14 +0200 Received: from scfae-sc-2.mti.labs.mlnx (scfae-sc-2.mti.labs.mlnx [10.101.0.96]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x2PJDCGc007438; Mon, 25 Mar 2019 21:13:13 +0200 From: Yongseok Koh To: shahafs@mellanox.com Cc: dev@dpdk.org, stable@dpdk.org Date: Mon, 25 Mar 2019 12:13:10 -0700 Message-Id: <20190325191310.20594-1-yskoh@mellanox.com> X-Mailer: git-send-email 2.11.0 Subject: [dpdk-dev] [PATCH] net/mlx5: revert mbuf address calculation for x86 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Content-Type: text/plain; charset="UTF-8" Message-ID: <20190325191310.Uab94Qcm844A5qUBBPlDcPWSUCAyYXuBMBCyvK8HXr8@z> When replenishing mbufs on Rx, buffer address (mbuf->buf_addr) should be loaded. non-x86 processors (mostly RISC such as ARM and Power) are more vulnerable to load stall. For x86, reducing the number of instructions seems to matter most. For x86, this is simply a load but for other architectures, it is calculated from the address of mbuf structure by rte_mbuf_buf_addr() without having to load the first cacheline of the mbuf. Fixes: 12d468a62bc1 ("net/mlx5: fix instruction hotspot on replenishing Rx buffer") Cc: stable@dpdk.org Signed-off-by: Yongseok Koh --- drivers/net/mlx5/mlx5_rxtx_vec.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.h b/drivers/net/mlx5/mlx5_rxtx_vec.h index 5df8e291e6..4220b08dd2 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.h +++ b/drivers/net/mlx5/mlx5_rxtx_vec.h @@ -102,9 +102,21 @@ mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n) return; } for (i = 0; i < n; ++i) { - void *buf_addr = rte_mbuf_buf_addr(elts[i], rxq->mp); + void *buf_addr; + /* + * Load the virtual address for Rx WQE. non-x86 processors + * (mostly RISC such as ARM and Power) are more vulnerable to + * load stall. For x86, reducing the number of instructions + * seems to matter most. + */ +#ifdef RTE_ARCH_X86_64 + buf_addr = elts[i]->buf_addr; + assert(buf_addr == rte_mbuf_buf_addr(elts[i], rxq->mp)); +#else + buf_addr = rte_mbuf_buf_addr(elts[i], rxq->mp); assert(buf_addr == elts[i]->buf_addr); +#endif wq[i].addr = rte_cpu_to_be_64((uintptr_t)buf_addr + RTE_PKTMBUF_HEADROOM); /* If there's only one MR, no need to replace LKey in WQE. */ -- 2.11.0