From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id C5EC3A0679 for ; Mon, 1 Apr 2019 21:34:36 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 136D63576; Mon, 1 Apr 2019 21:34:36 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 45AE03572 for ; Mon, 1 Apr 2019 21:34:34 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Apr 2019 12:34:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,297,1549958400"; d="scan'208";a="219579522" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga001.jf.intel.com with ESMTP; 01 Apr 2019 12:34:32 -0700 Received: from fmsmsx115.amr.corp.intel.com (10.18.116.19) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 1 Apr 2019 12:34:33 -0700 Received: from fmsmsx108.amr.corp.intel.com ([169.254.9.216]) by fmsmsx115.amr.corp.intel.com ([169.254.4.62]) with mapi id 14.03.0415.000; Mon, 1 Apr 2019 12:34:32 -0700 From: "Eads, Gage" To: Honnappa Nagarahalli , "dev@dpdk.org" CC: "olivier.matz@6wind.com" , "arybchenko@solarflare.com" , "Richardson, Bruce" , "Ananyev, Konstantin" , "Gavin Hu (Arm Technology China)" , nd , "thomas@monjalon.net" , nd Thread-Topic: [PATCH v3 1/8] stack: introduce rte stack library Thread-Index: AQHU1CtVrsaMA7YCkEOnYy6dB4cOVqYgkw6AgAJQ+XCABNcfIIAACF7Q Date: Mon, 1 Apr 2019 19:34:32 +0000 Message-ID: <9184057F7FC11744A2107296B6B8EB1E5420E63B@FMSMSX108.amr.corp.intel.com> References: <20190305164256.2367-1-gage.eads@intel.com> <20190306144559.391-1-gage.eads@intel.com> <20190306144559.391-2-gage.eads@intel.com> <9184057F7FC11744A2107296B6B8EB1E5420D923@FMSMSX108.amr.corp.intel.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYThiZTljNGYtYTc4Ni00ODk5LWFjOWQtZTQ5ZDQ3MjU3OWNiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiYllzODZNdTdXeTZBZXllZkJTT3hobzJkMUpRbzJJajJHRnZrT0luV1ZCUUtRU1VaelVOazRyM2lza0tpUEJ5aiJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.1.200.106] Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [dpdk-dev] [PATCH v3 1/8] stack: introduce rte stack library X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190401193432.EXhfQ1Umhn9o3IKAdMr28SOFNi_pgNp4TNmzEDtgsDI@z> > -----Original Message----- > From: Honnappa Nagarahalli [mailto:Honnappa.Nagarahalli@arm.com] > Sent: Monday, April 1, 2019 12:41 PM > To: Eads, Gage ; dev@dpdk.org > Cc: olivier.matz@6wind.com; arybchenko@solarflare.com; Richardson, Bruce > ; Ananyev, Konstantin > ; Gavin Hu (Arm Technology China) > ; nd ; thomas@monjalon.net; nd > > Subject: RE: [PATCH v3 1/8] stack: introduce rte stack library >=20 > > > > > > +static ssize_t > > > > +rte_stack_get_memsize(unsigned int count) { > > > > + ssize_t sz =3D sizeof(struct rte_stack); > > > > + > > > > + /* Add padding to avoid false sharing conflicts */ > > > > + sz +=3D RTE_CACHE_LINE_ROUNDUP(count * sizeof(void *)) + > > > > + 2 * RTE_CACHE_LINE_SIZE; > > > I did not understand how the false sharing is caused and how this > > > padding is solving the issue. Verbose comments would help. > > > > The additional padding (beyond the CACHE_LINE_ROUNDUP) is to prevent > > false sharing caused by adjacent/next-line hardware prefetchers. I'll > > address this. > > > Is it not a generic problem? Or is it specific to this library? This is not limited to this library, but it only affects systems with (enab= led) next-line prefetchers, for example Intel products with an L2 adjacent = cache line prefetcher[1]. For those systems, additional padding can potenti= ally improve performance. As I understand it, this was the reason behind th= e 128B alignment added to rte_ring a couple years ago[2]. [1] https://software.intel.com/en-us/articles/disclosure-of-hw-prefetcher-c= ontrol-on-some-intel-processors [2] http://mails.dpdk.org/archives/dev/2017-February/058613.html