From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: <dev-bounces@dpdk.org> Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id B4DF3A0679 for <public@inbox.dpdk.org>; Wed, 3 Apr 2019 22:01:10 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 786DF1B131; Wed, 3 Apr 2019 22:01:08 +0200 (CEST) Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id B5BC77EC7 for <dev@dpdk.org>; Wed, 3 Apr 2019 22:01:06 +0200 (CEST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id 2EBDD2716C; Wed, 3 Apr 2019 16:01:06 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Wed, 03 Apr 2019 16:01:06 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s=mesmtp; bh=vtUVgHydxLB7/ThIeSPgQnKsNo3LtscK/Qa6AwPvWtM=; b=aGKfH5X1twGL eGapkflOKJr2rBkzQ7U5a3J5lAZj17zuog43bU1AX/oDf5pokG/q+YHXmBJ7lzip RrzwNYHb4C9cMAdoAJPFVANAT6gx/p9xpz07x01efxr01yebetkRRGBNtu79uB/8 UPcUN/8oe3pGO3uQnKODi+YA5OXwC98= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=vtUVgHydxLB7/ThIeSPgQnKsNo3LtscK/Qa6AwPvW tM=; b=PquaxIOXleL04Xn0o0BglUZNop+oPoLdVhdFlkKZaBA+pNeZr7KoF0EBH 0zJBiwDVpWiR4S2dRd/dnceUjyI/Hs7h4jRF5cl8oPurEEGRiGuuk29tvOMWhrX6 +dBfZ8vG9hlB0OpywNB2PtvRzOIdVE3/kd3XzDMjOiIdItEF3Dm60ta+Uhh2sWeY Gfp1FlmI8X8Giald+0ixppKmjCfD9PFcdBT8piei43bXM2vnnVpNktMtzSVbd+hQ E6LqZqdKgP6vOz2DGF9JAUYlcJtwUPe1+fkr9iKI/+6ufSchycNvePbKxGiYJo8z y62CqWoVFVqA2YL0r49YHMu/zXFRA== X-ME-Sender: <xms:ABGlXDOAoYcUSdKmOO9a9Q9ccIanovC1NHyuRAxkeRdUZinsXVZhQw> X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduuddrtdefgdduudejucdltddurdeguddtrddttd dmucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfv pdfurfetoffkrfgpnffqhgenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpih gvnhhtshculddquddttddmnecujfgurhephffvufffkfgjfhgggfgtsehtufertddttddv necuhfhrohhmpefvhhhomhgrshcuofhonhhjrghlohhnuceothhhohhmrghssehmohhnjh grlhhonhdrnhgvtheqnecuffhomhgrihhnpeguphgukhdrohhrghenucfkphepjeejrddu feegrddvtdefrddukeegnecurfgrrhgrmhepmhgrihhlfhhrohhmpehthhhomhgrshesmh honhhjrghlohhnrdhnvghtnecuvehluhhsthgvrhfuihiivgeptd X-ME-Proxy: <xmx:ABGlXESwXtUU6BnDv9dNYTXl_CMaaeSGeWSFU5g-e6K_rgEh5AR4pA> <xmx:ABGlXISa6lP6FuA5GFHSnExuUpcfp1FnUCdw8kfUPJHZ1GTxGl5iPQ> <xmx:ABGlXFADY8qhdZHKBeT6C09bVeg8Lz4t2O9LSiiLjNYYzA8IBfuH8Q> <xmx:AhGlXCANcq4QT-Hqg7qYhb9H8TIo_4OQI1Nhh9m4_pO8yeeWJlgzgg> Received: from xps.localnet (184.203.134.77.rev.sfr.net [77.134.203.184]) by mail.messagingengine.com (Postfix) with ESMTPA id EB345E4124; Wed, 3 Apr 2019 16:01:01 -0400 (EDT) From: Thomas Monjalon <thomas@monjalon.net> To: Gage Eads <gage.eads@intel.com> Cc: dev@dpdk.org, olivier.matz@6wind.com, arybchenko@solarflare.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, gavin.hu@arm.com, Honnappa.Nagarahalli@arm.com, nd@arm.com, chaozhu@linux.vnet.ibm.com, jerinj@marvell.com, hemant.agrawal@nxp.com Date: Wed, 03 Apr 2019 22:01:00 +0200 Message-ID: <2782725.XVNmG20pT0@xps> In-Reply-To: <20190403194456.13133-1-gage.eads@intel.com> References: <20190403193541.28044-1-thomas@monjalon.net> <20190403194456.13133-1-gage.eads@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="UTF-8" Subject: Re: [dpdk-dev] [PATCH v6] eal/x86: add 128-bit atomic compare exchange X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> Message-ID: <20190403200100.h5Sv58nmGrN8wXDA6zchNCgw9NiISfFGigAm8eY4q84@z> 03/04/2019 21:44, Gage Eads: > This operation can be used for non-blocking algorithms, such as a > non-blocking stack or ring. > > It is available only for x86_64. > > Signed-off-by: Gage Eads <gage.eads@intel.com> > Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> > --- > This patch addresses x86-64 only; other architectures can/will be supported > in the future. The __atomic intrinsic was considered for the implementation, > however libatomic was found[1] to use locks to implement the 128-bit CAS on at > least one architecture and so is eschewed here. The interface is modeled after > the __atomic_compare_exchange_16 (which itself is based on the C++11 memory > model) to best support weak consistency architectures. > > This patch was originally part of a series that introduces a non-blocking stack > mempool handler[2], and is required by a non-blocking ring patchset. This > patch was spun off so that the the NB ring depends only on this patch > and not on the entire non-blocking stack patchset. > > [1] http://mails.dpdk.org/archives/dev/2019-January/124002.html > [2] http://mails.dpdk.org/archives/dev/2019-January/123653.html > > v6: > - Use @code and @endcode to clean up pseudo-code generation > - Add note that the function is currently limited to x86-64 > > v5: > - Move declaration in the generic file for doxygen only (Thomas) > > v4: > - Move function declaration from generic/rte_atomic.h to x86-64 header file > > v3: > - Rename function to ISA-neutral rte_atomic128_cmp_exchange() > - Fix two pseudocode bugs in function documentation > > v2: > - Rename function to rte_atomic128_cmpxchg() > - Replace "=A" output constraint with "=a" and "=d" to prevent GCC from using > the al register for the sete destination > - Extend 'weak' definition to allow non-atomic 'exp' updates. > - Add const keyword to 'src' and remove volatile keyword from 'dst' > - Put __int128 in a union in rte_int128_t and move the structure definition > inside the RTE_ARCH_x86_64 ifdef > - Drop enum rte_atomic_memmodel_t in favor of compiler-defined __ATOMIC_* > - Drop unnecessary comment relating to X86_64 > - Tweak the pseudocode to reflect the 'exp' update on failure. > > .../common/include/arch/x86/rte_atomic_64.h | 47 +++++++++++++++++++ > lib/librte_eal/common/include/generic/rte_atomic.h | 52 ++++++++++++++++++++++ > 2 files changed, 99 insertions(+) Applied, thanks