From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by dpdk.org (Postfix) with ESMTP id B5DA34C96 for ; Sat, 6 Apr 2019 16:28:29 +0200 (CEST) Received: by mail-pf1-f194.google.com with SMTP id y13so4899676pfm.11 for ; Sat, 06 Apr 2019 07:28:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Eafi/uPL5ecY/xhRQYiAdpY6E8uOqNwAjaF3LQtbfc=; b=IxD7Ws02/PgrcSk/FtVDZUGPCQzr4zSB4ZqG20bpoiizzStLFwT5GgRSzM4xpSN1ee LQZphLrDcXdBjSicRn0JpUT7T2HbVE93QJy65oZaE5YSRr+a9YiYYjsqKzbPcdYV5UG/ lnqsoDKGl8KmZpWdoaRCHyd1NEWOqnkdwPBjowmeD5uUTycDPoGquzoh9wzA7xB90lru kdWSf0xtGbYR0vvB4GNebEonDsyTXRBu+Qp44dCt27w7Q+ZS52MxuexINMbZPsIlVcTy OE7H3Wfah5oS0LEN3enl3zXpb3ls9cPOOGpRqU5DuhSPVcsaaL6HjhM0tBbykzHv2MKB ejnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Eafi/uPL5ecY/xhRQYiAdpY6E8uOqNwAjaF3LQtbfc=; b=EilL6AUBMKMCMDPVAxxW1p3S+i8aazo1yOG/CkxjJnZ7n1vpERmzXUxfi5uhsStofz ZehQM3hqPs9n4Y7OZrCZ87k267hK5WtuIqXZ594HktSKLLWmSO4PSMPbU537q65lV1mK 4CCGgtUYJaHuJFp/kJU+ffV47D2hS0nS/4Uhh8kCfxF7hgXACzd1P8OP5jFpP8bYz8Vf Ks3QgU6fjmK6KyTmXjNZirHULGOXWUt8/fvNdrD6Zn5Cz5X4mU4K4zHGHnwRfp+B+RMJ V3Yvgjx0iqCPI4w0VjF9pi70Kku/ENieBDVbTcd3Lpl8RUTABclK0Q/NwsX4r4rel03j w+HA== X-Gm-Message-State: APjAAAX7VMUbgm/HIxd3feKMy7S1owhpk+xHEPZJifrAclBD1EOXf17Y NJjqW1UPgfEFGRFaQswHnMSvxSLM7Bk= X-Google-Smtp-Source: APXvYqzzg17KQmj7HGyCiuGAE5Gblclv0UIYhTamAViPwNZoM6PRLyWIVgpruEevy/kq3zWVRQ372w== X-Received: by 2002:a63:6581:: with SMTP id z123mr17505515pgb.243.1554560908740; Sat, 06 Apr 2019 07:28:28 -0700 (PDT) Received: from jerin.caveonetworks.com ([223.226.40.87]) by smtp.gmail.com with ESMTPSA id o5sm84199008pfa.135.2019.04.06.07.28.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 06 Apr 2019 07:28:28 -0700 (PDT) From: jerinjacobk@gmail.com X-Google-Original-From: jerinj@marvell.com To: Thomas Monjalon Cc: dev@dpdk.org, Pavan Nikhilesh , Jerin Jacob Date: Sat, 6 Apr 2019 19:57:35 +0530 Message-Id: <20190406142737.20091-2-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190406142737.20091-1-jerinj@marvell.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 06 Apr 2019 14:28:30 -0000 From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 170a4981a..8de3f3e3a 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -52,12 +52,10 @@ flags_generic = [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -71,6 +69,27 @@ flags_dpaa2 = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra = [] +flags_thunderx_extra = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']]] + +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -157,8 +176,16 @@ else endif foreach marg: machine[2] if marg[0] == impl_pn - foreach f: marg[1] - machine_args += f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args += flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 6B404A0679 for ; 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Sat, 06 Apr 2019 07:28:28 -0700 (PDT) From: jerinjacobk@gmail.com X-Google-Original-From: jerinj@marvell.com To: Thomas Monjalon Cc: dev@dpdk.org, Pavan Nikhilesh , Jerin Jacob Date: Sat, 6 Apr 2019 19:57:35 +0530 Message-Id: <20190406142737.20091-2-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190406142737.20091-1-jerinj@marvell.com> References: <20190318164949.2357-1-jerinj@marvell.com> <20190406142737.20091-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Content-Type: text/plain; charset="UTF-8" Message-ID: <20190406142735.QV_RiOFflb-P4CrXHKX-XzAv_XqVdq8kYpWeyhf9TYE@z> From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 170a4981a..8de3f3e3a 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -52,12 +52,10 @@ flags_generic = [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -71,6 +69,27 @@ flags_dpaa2 = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra = [] +flags_thunderx_extra = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']]] + +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -157,8 +176,16 @@ else endif foreach marg: machine[2] if marg[0] == impl_pn - foreach f: marg[1] - machine_args += f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args += flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach -- 2.21.0