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From: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>
To: Yongseok Koh <yskoh@mellanox.com>, "jerinjacobk@gmail.com"
<jerinjacobk@gmail.com>
CC: Thomas Monjalon <thomas@monjalon.net>, dev <dev@dpdk.org>, "Jerin Jacob
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Thread-Topic: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support machine
specific flags
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Subject: Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to
support machine specific flags
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Message-ID: <20190410142246.qMdBmBqPpNlmT0IyU-X6tRhRvNimtnJ9yl-djyvghak@z>
>-----Original Message-----
>From: Yongseok Koh <yskoh@mellanox.com>
>Sent: Wednesday, April 10, 2019 7:45 AM
>To: jerinjacobk@gmail.com; Pavan Nikhilesh Bhagavatula
><pbhagavatula@marvell.com>
>Cc: Thomas Monjalon <thomas@monjalon.net>; dev <dev@dpdk.org>; Jerin
>Jacob Kollanukkaran <jerinj@marvell.com>
>Subject: [EXT] Re: [dpdk-dev] [PATCH v7 2/4] meson: add infra to support
>machine specific flags
>
>External Email
>
>----------------------------------------------------------------------
>
>> On Apr 9, 2019, at 5:40 PM, Yongseok Koh <yskoh@mellanox.com> wrote:
>>
>>>
>>> On Apr 6, 2019, at 7:27 AM, jerinjacobk@gmail.com wrote:
>>>
>>> From: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>>
>>> Currently, RTE_* flags are set based on the implementer ID but there
>>> might be some micro arch specific differences from the same vendor
>>> eg. CACHE_LINESIZE. Add support to set micro arch specific flags.
>>>
>>> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
>>> Signed-off-by: Jerin Jacob <jerinj@marvell.com>
>>> ---
>>> config/arm/meson.build | 37 ++++++++++++++++++++++++++++++++-----
>>> 1 file changed, 32 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>> 170a4981a..8de3f3e3a 100644
>>> --- a/config/arm/meson.build
>>> +++ b/config/arm/meson.build
>>> @@ -52,12 +52,10 @@ flags_generic =3D [
>>> ['RTE_USE_C11_MEM_MODEL', true],
>>> ['RTE_CACHE_LINE_SIZE', 128]]
>>> flags_cavium =3D [
>>> - ['RTE_MACHINE', '"thunderx"'],
>>> ['RTE_CACHE_LINE_SIZE', 128],
>>> ['RTE_MAX_NUMA_NODES', 2],
>>> ['RTE_MAX_LCORE', 96],
>>> - ['RTE_MAX_VFIO_GROUPS', 128],
>>> - ['RTE_USE_C11_MEM_MODEL', false]]
>>> + ['RTE_MAX_VFIO_GROUPS', 128]]
>>> flags_dpaa =3D [
>>> ['RTE_MACHINE', '"dpaa"'],
>>> ['RTE_USE_C11_MEM_MODEL', true],
>>> @@ -71,6 +69,27 @@ flags_dpaa2 =3D [
>>> ['RTE_MAX_NUMA_NODES', 1],
>>> ['RTE_MAX_LCORE', 16],
>>> ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]]
>>> +flags_default_extra =3D []
>>> +flags_thunderx_extra =3D [
>>> + ['RTE_MACHINE', '"thunderx"'],
>>> + ['RTE_USE_C11_MEM_MODEL', false]]
>>> +
>>> +machine_args_generic =3D [
>>> + ['default', ['-march=3Darmv8-a+crc+crypto']],
>>> + ['native', ['-march=3Dnative']],
>>> + ['0xd03', ['-mcpu=3Dcortex-a53']],
>>> + ['0xd04', ['-mcpu=3Dcortex-a35']],
>>> + ['0xd07', ['-mcpu=3Dcortex-a57']],
>>> + ['0xd08', ['-mcpu=3Dcortex-a72']],
>>> + ['0xd09', ['-mcpu=3Dcortex-a73']],
>>> + ['0xd0a', ['-mcpu=3Dcortex-a75']]]
>>> +
>>> +machine_args_cavium =3D [
>>> + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']],
>>> + ['native', ['-march=3Dnative']],
>>> + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra],
>>> + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra],
>>> + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]]
>>
>> Looks like there's a mistake in rebasing it?
Seems so will send out v8.
>> You should've removed machine_args_generic and machine_args_cavium in
>> the beginning of this file.
>>
>> Other than that, it looks good to me.
>>
>> BTW, thanks for the patch. I raised this issue before and I was
>> supposed to make the change but you have taken it.
>>
>> Yongseok
>>
>>> ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page
>>> G7-5321) impl_generic =3D ['Generic armv8', flags_generic,
>>> machine_args_generic] @@ -157,8 +176,16 @@ else
>>> endif
>>> foreach marg: machine[2]
>>> if marg[0] =3D=3D impl_pn
>>> - foreach f: marg[1]
>>> - machine_args +=3D f
>>> + foreach flag: marg[1]
>>> + if cc.has_argument(flag)
>>> + machine_args +=3D flag
>>> + endif
>>> + endforeach
>>> + # Apply any extra machine specific flags.
>>> + foreach flag: marg.get(2, flags_default_extra)
>>> + if flag.length() > 0
>>> + dpdk_conf.set(flag[0], flag[1])
>>> + endif
>
>And setting the extra flags doesn't work well with gcc < 7 because of the
>following,
Extra flags aren't set in this case as the third variable in the list is m=
issing when 'native' or 'default' is selected
generic=3D=20
['default', ['-march=3Darmv8-a+crc+crypto']],
['native', ['-march=3Dnative']]
cavium=3D
['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']],
['native', ['-march=3Dnative']]
And marg.get falls back to flags_default_extra =3D [].
>
> # Primary part number based mcpu flags are supported
> # for gcc versions > 7
> if cc.version().version_compare(
> '<7.0') or cmd_output.length() =3D=3D 0
> if not meson.is_cross_build() and arm_force_native_march =
=3D=3D true
> impl_pn =3D 'native'
> else
> impl_pn =3D 'default'
> endif
> endif
>
>Thanks,
>Yongseok
>
>>> endforeach
>>> endif
>>> endforeach
>>> --
>>> 2.21.0