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SRVR:BYAPR18MB2536; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: ASYuR5yU2ajkDlg+4pcYkFTgriOUvzRpLyFS4EHMuNquQI5XKRYU356pX73GSRghQFPhaCuLmN5eRGVfgMIirZmzOWg/f1Jn4K/DXfB5Ud72YH7uOKuCj4cDawG0Vf9ul/qS02TwgEkfdheylqoB2RM1GSNuM4I4BM6DWAPjzy9Gm3eJMlOmHc/nC+i5XO70ay7cp+6l95YC9ciHu61azDyPzHlXjnt2fUCrOdW3dmvrkwPEjzx25yWrUqlP1zOrvzRa63WnuJj8IgSvNQyy7IOaP3zZwhGC1lJ8gCEUYxVF/U74AqcywMlP7jxoMURcawzain13bJ+P185w2YuHjLKYh4Ka61NPZTaonjdXzmhTIwYH3561Z8hofeIwFc7ZbHsyZgg3TuQRzQ3ReUQte0zLw8TlhPOa37uvvXnPEMg= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: d183ff77-16be-43d9-2a8a-08d6bf1632eb X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Apr 2019 07:12:18.2120 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2536 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-12_05:, , signatures=0 Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> Message-ID: <20190412071218.P22qyfubWBMiEWlD6fC-hTdDCNzWiK4x953KSQqr-dA@z> > -----Original Message----- > From: Thomas Monjalon <thomas@monjalon.net> > Sent: Friday, April 12, 2019 5:07 AM > To: Pavan Nikhilesh Bhagavatula <pbhagavatula@marvell.com>; Jerin Jacob > Kollanukkaran <jerinj@marvell.com> > Cc: dev@dpdk.org; jerinjacobk@gmail.com; yskoh@mellanox.com; > bruce.richardson@intel.com > Subject: Re: [dpdk-dev] [PATCH v8 2/4] meson: add infra to support machin= e > specific flags >=20 > 10/04/2019 18:13, jerinjacobk@gmail.com: > > From: Pavan Nikhilesh <pbhagavatula@marvell.com> > > > > Currently, RTE_* flags are set based on the implementer ID but there > > might be some micro arch specific differences from the same vendor eg. > > CACHE_LINESIZE. Add support to set micro arch specific flags. >=20 > I don't like how flags are set in config/arm/meson.build. > It is a real mess to find which flag applies to which machine. > Adding the flags_*_extra in the machine_args_* is adding more mess. >=20 > [...] > > flags_common_default =3D [ > > # Accelarate rte_memcpy. Be sure to run unit test > (memcpy_perf_autotest) > > # to determine the best threshold in code. Refer to notes in source > > file @@ -52,12 +33,10 @@ flags_generic =3D [ > > ['RTE_USE_C11_MEM_MODEL', true], > > ['RTE_CACHE_LINE_SIZE', 128]] > > flags_cavium =3D [ > > - ['RTE_MACHINE', '"thunderx"'], > > ['RTE_CACHE_LINE_SIZE', 128], > > ['RTE_MAX_NUMA_NODES', 2], > > ['RTE_MAX_LCORE', 96], > > - ['RTE_MAX_VFIO_GROUPS', 128], > > - ['RTE_USE_C11_MEM_MODEL', false]] > > + ['RTE_MAX_VFIO_GROUPS', 128]] > > flags_dpaa =3D [ > > ['RTE_MACHINE', '"dpaa"'], > > ['RTE_USE_C11_MEM_MODEL', true], > > @@ -71,6 +50,27 @@ flags_dpaa2 =3D [ > > ['RTE_MAX_NUMA_NODES', 1], > > ['RTE_MAX_LCORE', 16], > > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] > > +flags_default_extra =3D [] > > +flags_thunderx_extra =3D [ > > + ['RTE_MACHINE', '"thunderx"'], > > + ['RTE_USE_C11_MEM_MODEL', false]] > > + > > +machine_args_generic =3D [ > > + ['default', ['-march=3Darmv8-a+crc+crypto']], > > + ['native', ['-march=3Dnative']], > > + ['0xd03', ['-mcpu=3Dcortex-a53']], > > + ['0xd04', ['-mcpu=3Dcortex-a35']], > > + ['0xd07', ['-mcpu=3Dcortex-a57']], > > + ['0xd08', ['-mcpu=3Dcortex-a72']], > > + ['0xd09', ['-mcpu=3Dcortex-a73']], > > + ['0xd0a', ['-mcpu=3Dcortex-a75']]] > > + > > +machine_args_cavium =3D [ > > + ['default', ['-march=3Darmv8-a+crc+crypto','-mcpu=3Dthunderx']], > > + ['native', ['-march=3Dnative']], > > + ['0xa1', ['-mcpu=3Dthunderxt88'], flags_thunderx_extra], > > + ['0xa2', ['-mcpu=3Dthunderxt81'], flags_thunderx_extra], > > + ['0xa3', ['-mcpu=3Dthunderxt83'], flags_thunderx_extra]] >=20 > I think we should have a simpler model. > We need only to know the machine name and get all the related machine > config. > In native compilation, machine name is guessed from implementor id and pn > (from config/arm/armv8_machine.py). We can directly output the machine > name from this script and leave the naming logic in this script. > In the cross-compilation config files (config/arm/*), we can just specify= the > machine name. > Then every machine config (machine_args and dpdk_conf) would be > specified in some arrays based on the machine name. > Of course, we can keep some common default values. Thomas, This patch was around last three months. It reached upto v8. I think, in that last minute for RC2, We cannot take major rework on this a= s it needs to tested for Other arm64 platform too. It was pulled out from RC1 because other pcap iss= ue from meson. Now its not fair to say to rework the meson stuff now. I suggest to take other rework in next release. >=20 > Thoughts? >=20