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DIR:OUT; SFP:1101; SCL:1; SRVR:BYAPR18MB2885; H:BYAPR18MB2424.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: wmvnmiczAiu59XZW7IxnwZ+bAiCOOlx7zW4sbOYlMwc1HvHIJUG4Bf1N4UFCCxE+ertFmcrGpRQ5JpZxqvUaBCqlGLrfm25WfjfS0tZPji3Ia5MDSKnU9bPic8QiJp0j4lzi4yQKb3w+ifd9IvPyzI9lDjKEMFHSF6KQg3pCGzzv+mEUmCcazG+f6Mnpvsm7nfu5g6TaS66QwHTjnSIn8CJBLgkH1Lue4h2JWK8F8J3OAtNczL/eWx5FBkd9MmeHyY7MaaMtn6Sdrj0gfT4U9MbrULdViT1NFJCCtEXNcy0O69sTviMg9FkFV6XAXbQ9/lNY1Zf82I4IL36gUj0PWosbKO1i1AhBaWV/Mr4Uc95fhkIDcbMpwQJPViTEHCI3ILIj9yRDcYvUUepu14CZr8jHRyBWrQ9G4mWpIliBv1M= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 8fed4e00-579e-48dd-c25a-08d6bfdb56a3 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Apr 2019 06:43:29.0688 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR18MB2885 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-13_02:, , signatures=0 Subject: Re: [dpdk-dev] [EXT] [PATCH 2/6] meson: change default cache line size for cortex-a72 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions <dev.dpdk.org> List-Unsubscribe: <https://mails.dpdk.org/options/dev>, <mailto:dev-request@dpdk.org?subject=unsubscribe> List-Archive: <http://mails.dpdk.org/archives/dev/> List-Post: <mailto:dev@dpdk.org> List-Help: <mailto:dev-request@dpdk.org?subject=help> List-Subscribe: <https://mails.dpdk.org/listinfo/dev>, <mailto:dev-request@dpdk.org?subject=subscribe> Errors-To: dev-bounces@dpdk.org Sender: "dev" <dev-bounces@dpdk.org> Message-ID: <20190413064329.3oVb8tvLNzitYRkzWApQTrR3xGnrsfm5RDgpwub8V0E@z> > -----Original Message----- > From: Yongseok Koh <yskoh@mellanox.com> > Sent: Saturday, April 13, 2019 4:55 AM > To: bruce.richardson@intel.com; Jerin Jacob Kollanukkaran > <jerinj@marvell.com>; Pavan Nikhilesh Bhagavatula > <pbhagavatula@marvell.com>; shahafs@mellanox.com > Cc: dev@dpdk.org; thomas@monjalon.net; gavin.hu@arm.com; > Honnappa.Nagarahalli@arm.com > Subject: [EXT] [PATCH 2/6] meson: change default cache line size for cort= ex-a72 >=20 > ---------------------------------------------------------------------- > Per the email discussion [1], the default cache line size of armv8 > cortex-a72 is changed to 64 bytes. IMO, In git commit you remove the reference to specific discussion and Update the reason correctly. >=20 > [1] https://mails.dpdk.org/archives/dev/2019-January/123218.html >=20 > Signed-off-by: Yongseok Koh <yskoh@mellanox.com> > --- > config/arm/meson.build | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > e00b894523..73c581948c 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -51,6 +51,8 @@ flags_dpaa2 =3D [ > ['RTE_MAX_LCORE', 16], > ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] flags_default_extra =3D [] > +flags_cortex_a72_extra =3D [ > + ['RTE_CACHE_LINE_SIZE', 64]] > flags_thunderx_extra =3D [ > ['RTE_MACHINE', '"thunderx"'], > ['RTE_USE_C11_MEM_MODEL', false]] > @@ -73,7 +75,7 @@ machine_args_generic =3D [ > ['0xd03', ['-mcpu=3Dcortex-a53']], > ['0xd04', ['-mcpu=3Dcortex-a35']], > ['0xd07', ['-mcpu=3Dcortex-a57']], > - ['0xd08', ['-mcpu=3Dcortex-a72']], > + ['0xd08', ['-mcpu=3Dcortex-a72'], flags_cortex_a72_extra], > ['0xd09', ['-mcpu=3Dcortex-a73']], > ['0xd0a', ['-mcpu=3Dcortex-a75']]] I think, flags_cortex_a72_extra() can be changed to flags_vendor_arm_extra = or something similar And update the following CPUs also not just cortex-a72. ['0xd03', ['-mcpu=3Dcortex-a53']], ['0xd04', ['-mcpu=3Dcortex-a35']], ['0xd05', ['-mcpu=3Dcortex-a55']], ['0xd07', ['-mcpu=3Dcortex-a57']], ['0xd08', ['-mcpu=3Dcortex-a72']], ['0xd09', ['-mcpu=3Dcortex-a73']], ['0xd0a', ['-mcpu=3Dcortex-a75']], ['0xd0b', ['-mcpu=3Dcortex-a76']], >=20 > -- > 2.21.0.196.g041f5ea