From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id F221F1B113 for ; Sat, 13 Apr 2019 21:01:45 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3DJ03Ib013832; Sat, 13 Apr 2019 12:01:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=l1t7FD4KeBpw0l452weo/JoqiLxqvJFSCdubOE6CD+g=; b=aISDI/qvURu0c6R20hgLgvvwaNNVvxCN+TixwezZCrUEPUaOqEpghhM8gkUdU+oe9jXP hIwJthFNznhSiw3e+4s9dICPwgwG2WlMSfboelDu26B8s/UGx5NCbH7XTna4Z71b52ys jIA5e+t/TYklkAK4LJH860heYeANfEut7gf8F/TZsxbFfVFNRYc+VhhMdHnM7J/KEUlM TJDTogegITd1RZe3m5G/yxBfncU1ib8wDcwyVSmAUQ+JcjVfUWoqQUya2lac2hNSD6Ef rRTcCmKgwP74cOk9KIEIbZFqXUhmbqcNccHI0/TuRI+G6sLjMki3HI0JkngUopNvm8Me pg== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2ruf9jrtjs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 13 Apr 2019 12:01:45 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 13 Apr 2019 12:01:43 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 13 Apr 2019 12:01:43 -0700 Received: from jerin-lab.marvell.com (unknown [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id DAD1A3F703F; Sat, 13 Apr 2019 12:01:41 -0700 (PDT) From: To: , Thomas Monjalon CC: , Pavan Nikhilesh , "Jerin Jacob" Date: Sun, 14 Apr 2019 00:31:19 +0530 Message-ID: <20190413190121.15416-2-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190413190121.15416-1-jerinj@marvell.com> References: <20190410161400.9361-1-jerinj@marvell.com> <20190413190121.15416-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-13_06:, , signatures=0 Subject: [dpdk-dev] [PATCH v9 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 13 Apr 2019 19:01:46 -0000 From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 67 +++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 170a4981a..d30a17426 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine) arm_force_native_march = false -machine_args_generic = [ - ['default', ['-march=armv8-a+crc+crypto']], - ['native', ['-march=native']], - ['0xd03', ['-mcpu=cortex-a53']], - ['0xd04', ['-mcpu=cortex-a35']], - ['0xd05', ['-mcpu=cortex-a55']], - ['0xd07', ['-mcpu=cortex-a57']], - ['0xd08', ['-mcpu=cortex-a72']], - ['0xd09', ['-mcpu=cortex-a73']], - ['0xd0a', ['-mcpu=cortex-a75']], - ['0xd0b', ['-mcpu=cortex-a76']], -] -machine_args_cavium = [ - ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], - ['native', ['-march=native']], - ['0xa1', ['-mcpu=thunderxt88']], - ['0xa2', ['-mcpu=thunderxt81']], - ['0xa3', ['-mcpu=thunderxt83']]] - flags_common_default = [ # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) # to determine the best threshold in code. Refer to notes in source file @@ -52,12 +33,10 @@ flags_generic = [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -71,6 +50,27 @@ flags_dpaa2 = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra = [] +flags_thunderx_extra = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']]] + +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -145,20 +145,19 @@ else dpdk_conf.set(flag[0], flag[1]) endif endforeach - # Primary part number based mcpu flags are supported - # for gcc versions > 7 - if cc.version().version_compare( - '<7.0') or cmd_output.length() == 0 - if not meson.is_cross_build() and arm_force_native_march == true - impl_pn = 'native' - else - impl_pn = 'default' - endif - endif + foreach marg: machine[2] if marg[0] == impl_pn - foreach f: marg[1] - machine_args += f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args += flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id C458DA0096 for ; Sat, 13 Apr 2019 21:01:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 538571B113; Sat, 13 Apr 2019 21:01:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id F221F1B113 for ; Sat, 13 Apr 2019 21:01:45 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x3DJ03Ib013832; Sat, 13 Apr 2019 12:01:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=l1t7FD4KeBpw0l452weo/JoqiLxqvJFSCdubOE6CD+g=; b=aISDI/qvURu0c6R20hgLgvvwaNNVvxCN+TixwezZCrUEPUaOqEpghhM8gkUdU+oe9jXP hIwJthFNznhSiw3e+4s9dICPwgwG2WlMSfboelDu26B8s/UGx5NCbH7XTna4Z71b52ys jIA5e+t/TYklkAK4LJH860heYeANfEut7gf8F/TZsxbFfVFNRYc+VhhMdHnM7J/KEUlM TJDTogegITd1RZe3m5G/yxBfncU1ib8wDcwyVSmAUQ+JcjVfUWoqQUya2lac2hNSD6Ef rRTcCmKgwP74cOk9KIEIbZFqXUhmbqcNccHI0/TuRI+G6sLjMki3HI0JkngUopNvm8Me pg== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2ruf9jrtjs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 13 Apr 2019 12:01:45 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 13 Apr 2019 12:01:43 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 13 Apr 2019 12:01:43 -0700 Received: from jerin-lab.marvell.com (unknown [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id DAD1A3F703F; Sat, 13 Apr 2019 12:01:41 -0700 (PDT) From: To: , Thomas Monjalon CC: , Pavan Nikhilesh , "Jerin Jacob" Date: Sun, 14 Apr 2019 00:31:19 +0530 Message-ID: <20190413190121.15416-2-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190413190121.15416-1-jerinj@marvell.com> References: <20190410161400.9361-1-jerinj@marvell.com> <20190413190121.15416-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="UTF-8" X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-13_06:, , signatures=0 Subject: [dpdk-dev] [PATCH v9 2/4] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190413190119.qPvqxRteMOCNCg76yMI2cE6AotSFL4iNW-rEqDikXVM@z> From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Pavan Nikhilesh Signed-off-by: Jerin Jacob --- config/arm/meson.build | 67 +++++++++++++++++++++--------------------- 1 file changed, 33 insertions(+), 34 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index 170a4981a..d30a17426 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -7,25 +7,6 @@ march_opt = '-march=@0@'.format(machine) arm_force_native_march = false -machine_args_generic = [ - ['default', ['-march=armv8-a+crc+crypto']], - ['native', ['-march=native']], - ['0xd03', ['-mcpu=cortex-a53']], - ['0xd04', ['-mcpu=cortex-a35']], - ['0xd05', ['-mcpu=cortex-a55']], - ['0xd07', ['-mcpu=cortex-a57']], - ['0xd08', ['-mcpu=cortex-a72']], - ['0xd09', ['-mcpu=cortex-a73']], - ['0xd0a', ['-mcpu=cortex-a75']], - ['0xd0b', ['-mcpu=cortex-a76']], -] -machine_args_cavium = [ - ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], - ['native', ['-march=native']], - ['0xa1', ['-mcpu=thunderxt88']], - ['0xa2', ['-mcpu=thunderxt81']], - ['0xa3', ['-mcpu=thunderxt83']]] - flags_common_default = [ # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) # to determine the best threshold in code. Refer to notes in source file @@ -52,12 +33,10 @@ flags_generic = [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -71,6 +50,27 @@ flags_dpaa2 = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra = [] +flags_thunderx_extra = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']]] + +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -145,20 +145,19 @@ else dpdk_conf.set(flag[0], flag[1]) endif endforeach - # Primary part number based mcpu flags are supported - # for gcc versions > 7 - if cc.version().version_compare( - '<7.0') or cmd_output.length() == 0 - if not meson.is_cross_build() and arm_force_native_march == true - impl_pn = 'native' - else - impl_pn = 'default' - endif - endif + foreach marg: machine[2] if marg[0] == impl_pn - foreach f: marg[1] - machine_args += f + foreach flag: marg[1] + if cc.has_argument(flag) + machine_args += flag + endif + endforeach + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif endforeach endif endforeach -- 2.21.0