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DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB5024; H:VE1PR08MB5149.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: yLHGUTFi3VNq1enCAhC4iFmSytKHlvhZDYN+5/pPScL0e+dFm3CfNAcLOm/kBIwaEsweapNtTyEqUaXx1bqplCaekP0BaF6gQDQs/ez85qdQbGJO1vLMOF2Uoh3kxFuWiWKlCqFTPke/YhTv0RTnT0wYou0H+01DPJVeddFKeMr1CyYG9+IBa7uhruyhnwgQRVlA3vfBSDkzW4931EzpU7R/N7V8FU3tp0N++DnukOUl6yvH9BcSAlEyXoof04F20iIW/g3MQxrLT91s7u2r4HZg41IrddTMLCe69KEdak9/kH3+AW0fdJIM1BdE06t6SAX4inKDuBRqaWmAgjlkGf35HW25Se8/GSWMfFhfcRBM5NjRVfybhfs6Et6cG+ifW4/VRvRTsg41DhhlSOWxoyGSLkW6wWvV+OgBC7qFyek= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: c96da2be-9d4d-4f8c-a8aa-08d6c3bad8eb X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Apr 2019 05:00:58.8268 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR08MB5024 Subject: Re: [dpdk-dev] [PATCH v2 2/4] meson: change default cache line size for armv8 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190418050058.FBEfueE8XQYpzJPsUymWAcy35g4klVTYn-azvR5Pndw@z> >=20 > Currently, the cache line size of armv8 CPUs having Implementor ID of 0x4= 1 is > 64 bytes. I guess you meant to say 128 bytes >=20 > Signed-off-by: Yongseok Koh > --- >=20 > v2: > * introduce flags_arm replacing flags_generic instead of using the extra = flags >=20 > config/arm/meson.build | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) >=20 > diff --git a/config/arm/meson.build b/config/arm/meson.build index > 22a062bad9..1db4ad2ee7 100644 > --- a/config/arm/meson.build > +++ b/config/arm/meson.build > @@ -32,6 +32,11 @@ flags_generic =3D [ > ['RTE_MAX_LCORE', 256], > ['RTE_USE_C11_MEM_MODEL', true], > ['RTE_CACHE_LINE_SIZE', 128]] > +flags_arm =3D [ > + ['RTE_MACHINE', '"armv8a"'], > + ['RTE_MAX_LCORE', 256], I am not aware of any implementations with implementor ID 0x41. Bluefield i= s the first one I am aware of. May be we can keep this smaller, 16? > + ['RTE_USE_C11_MEM_MODEL', true], > + ['RTE_CACHE_LINE_SIZE', 64]] > flags_cavium =3D [ > ['RTE_CACHE_LINE_SIZE', 128], > ['RTE_MAX_NUMA_NODES', 2], > @@ -88,7 +93,7 @@ machine_args_cavium =3D [ >=20 > ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) > impl_generic =3D ['Generic armv8', flags_generic, machine_args_generic] > -impl_0x41 =3D ['Arm', flags_generic, machine_args_generic] > +impl_0x41 =3D ['Arm', flags_arm, machine_args_generic] > impl_0x42 =3D ['Broadcom', flags_generic, machine_args_generic] > impl_0x43 =3D ['Cavium', flags_cavium, machine_args_cavium] > impl_0x44 =3D ['DEC', flags_generic, machine_args_generic] > -- > 2.11.0