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DIR:OUT; SFP:1101; SCL:1; SRVR:DB3PR0502MB4043; H:DB3PR0502MB3980.eurprd05.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: mellanox.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: fxsY505hoRZsRGFHLFlDlrGSfuZy7YhvL0GsZ0x10UV/VKt4IaXD0ohYLYBQyqkO89UmNUS7ob5etUwT2j5aiq/ziqyYNk2VtwxgkVv8+XTq2OYDMyTCPca1dVkOxixDG/dH84JkFr2oi51RgIGeQXSXGTzEuPwQThcbNkI6VSiWnErcCDvVEzJ/MB/rjclhxAcyDKv3y4FmiieFk1+8kY1crah0GYbLjFXqMJ+cXgnst+jQ5KXjvFVgDkancmruJUXCLgjX1Dmkc4EmguIE75XlFLbisWB9YSSqY+/I3YLFDqFZcbY/rlfKmB4AdE6dlQGfQ/18pbXrQCbFtjqQ54kGvwdIOtICgXn1zEa2ol2R7V6PwlpDp24mRrmo9Z7wzaO/+fu/hsF7GKvq7Xol5619PSW+/r0nGafJhdIzZ2Q= Content-Type: text/plain; charset="UTF-8" Content-ID: <0AB63C92A621FC4EAC3C208C32EC8DBC@eurprd05.prod.outlook.com> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: 89b85453-bcf4-4194-f427-08d6c82f1cdf X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Apr 2019 21:03:19.8144 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB3PR0502MB4043 Subject: Re: [dpdk-dev] [PATCH] net/mlx5: fix E-Switch flow without port item X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190423210319.uWBkUy56qsWDzNPCFcvwU3JLjdE6D1mLrxnrMT2D5Jg@z> On Tue, Apr 23, 2019 at 11:19:16AM +0000, Ori Kam wrote: > When creating a flow rule without the port_id pattern item, always the > PF was selected. >=20 > This commit fixes this issue, if no port_id pattern item is available > then we use the port that the flow was created on as source port. >=20 > Fixes: 822fb3195348 ("net/mlx5: add port id item to Direct Verbs") >=20 > Signed-off-by: Ori Kam > --- > drivers/net/mlx5/mlx5_flow_dv.c | 30 +++++++++++++++--------------- > 1 file changed, 15 insertions(+), 15 deletions(-) >=20 > diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow= _dv.c > index c2a2fc6..d17adbe 100644 > --- a/drivers/net/mlx5/mlx5_flow_dv.c > +++ b/drivers/net/mlx5/mlx5_flow_dv.c > @@ -3623,6 +3623,8 @@ struct field_modify_info modify_tcp[] =3D { > union flow_dv_attr flow_attr =3D { .attr =3D 0 }; > struct mlx5_flow_dv_tag_resource tag_resource; > uint32_t modify_action_position =3D UINT32_MAX; > + void *match_mask =3D matcher.mask.buf; > + void *match_value =3D dev_flow->dv.value.buf; > =20 > flow->group =3D attr->group; > if (attr->transfer) > @@ -3895,23 +3897,8 @@ struct field_modify_info modify_tcp[] =3D { > } > dev_flow->dv.actions_n =3D actions_n; > flow->actions =3D action_flags; > - if (attr->ingress && !attr->transfer && > - (priv->representor || priv->master)) { > - /* It was validated - we support unidirection flows only. */ > - assert(!attr->egress); > - /* > - * Add matching on source vport index only > - * for ingress rules in E-Switch configurations. > - */ > - flow_dv_translate_item_source_vport(matcher.mask.buf, > - dev_flow->dv.value.buf, > - priv->vport_id, > - 0xffff); > - } > for (; items->type !=3D RTE_FLOW_ITEM_TYPE_END; items++) { > int tunnel =3D !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); > - void *match_mask =3D matcher.mask.buf; > - void *match_value =3D dev_flow->dv.value.buf; > =20 > switch (items->type) { > case RTE_FLOW_ITEM_TYPE_PORT_ID: > @@ -4018,6 +4005,19 @@ struct field_modify_info modify_tcp[] =3D { > } > item_flags |=3D last_item; > } > + if (((attr->ingress && !attr->transfer) || > + (attr->transfer && !(item_flags & MLX5_FLOW_ITEM_PORT_ID))) && > + (priv->representor || priv->master)) { >From the validations, I could figure out - Either ingress (I) or egress (E) must be specified - Transfer (T) can't be egress - Port ID (P) is valid only if transfer (T) is specified. (!T and I) or (T and !P) =3D (I - T) + (T - P) =3D I - P So, this condition is equivalent to=20 if (attr->ingress && !!(item_flags & MLX5_FLOW_ITEM_PORT_ID) && (priv->representor || priv->master)) { ... } Right? If agreed, please add comment properly. > + /* It was validated - we support unidirection flows only. */ > + assert(!attr->egress); This comment and assert are there to mention ingress and egress are exclusi= ve. Is it still relevant? Did you also test the patch with enabling DEBUG? > + /* > + * Add matching on source vport index only > + * for ingress rules in E-Switch configurations. > + */ Please make this comment appropriate as well. Thanks, Yongseok > + if (flow_dv_translate_item_port_id(dev, match_mask, > + match_value, NULL)) > + return -rte_errno; > + } > assert(!flow_dv_check_valid_spec(matcher.mask.buf, > dev_flow->dv.value.buf)); > dev_flow->layers =3D item_flags; > --=20 > 1.8.3.1 >=20