From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 7521AA0096 for ; Thu, 9 May 2019 14:24:01 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 58BD737B7; Thu, 9 May 2019 14:24:00 +0200 (CEST) Received: from stargate.chelsio.com (stargate.chelsio.com [12.32.117.8]) by dpdk.org (Postfix) with ESMTP id 8EA0334F0; Thu, 9 May 2019 14:23:58 +0200 (CEST) Received: from localhost (scalar.blr.asicdesigners.com [10.193.185.94]) by stargate.chelsio.com (8.13.8/8.13.8) with ESMTP id x49CNo5S020850; Thu, 9 May 2019 05:23:51 -0700 Date: Thu, 9 May 2019 17:49:24 +0530 From: Rahul Lakkireddy To: Kevin Traynor Cc: "dev@dpdk.org" , Nirranjan Kirubaharan , Indranil Choudhury , "stable@dpdk.org" , Ferruh Yigit , Yongseok Koh , Luca Boccassi Message-ID: <20190509121923.GA16714@chelsio.com> References: <1555665721-11883-1-git-send-email-rahul.lakkireddy@chelsio.com> <9f373d3f-6701-8b68-9a56-f7f1db866e00@redhat.com> <20190509100331.GA16509@chelsio.com> <34e6c02a-7c06-03f6-1292-ffb618fc4c46@redhat.com> <20190509111138.GA16603@chelsio.com> <26afe358-4411-c481-5afa-93dcb263576b@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline In-Reply-To: <26afe358-4411-c481-5afa-93dcb263576b@redhat.com> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [dpdk-dev] [PATCH] net/cxgbe: update Chelsio T5/T6 NIC device ids X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Message-ID: <20190509121924.LT2RnxXOzrOwUKgKQtRsunkQczFcw59rWsVzymKO508@z> On Thursday, May 05/09/19, 2019 at 17:25:56 +0530, Kevin Traynor wrote: > On 09/05/2019 12:11, Rahul Lakkireddy wrote: > > On Thursday, May 05/09/19, 2019 at 16:08:05 +0530, Kevin Traynor wrote: > >> On 09/05/2019 11:03, Rahul Lakkireddy wrote: > >>> On Thursday, May 05/09/19, 2019 at 14:29:05 +0530, Kevin Traynor wrote: > >>>> On 19/04/2019 10:22, Rahul Lakkireddy wrote: > >>>>> Fixes: 04868e5bfddd ("net/cxgbe: add support to run Chelsio T6 cards") > >>>>> Cc: stable@dpdk.org > >>>>> > >>>> > >>>> Hi Rahul, > >>>> > >>>> Which stable release(s) is this change requested for? Have you tested > >>>> these devices on those branches to ensure they work with the cxgbe pmd > >>>> on those branches? > >>>> > >>>> Kevin. > >>> > >>> Hi Kevin, > >>> > >>> Please target 18.11 and 19.02 branches. All these devices work fine > >>> in these branches. > >>> > >> > >> Sorry, but this is not clear. There is no 19.02 branch and for 18.11 > >> branch, I don't know if you tested some/all of the devices with that > >> branch or are making assumption based on the cxgbe pmd in 18.11. > >> > > > > Yes, these devices work fine by manually applying this patch on 18.11.1 > > and 19.02. > > > > Thanks for clarifying. > > > I had thought 19.02 branch is available by now. Looks like this is not > > the case. Please apply the patch to 19.02 branch as well when it becomes > > available. > > > > There won't be a 19.02 stable branch. tl;dr there wasn't a maintainer > and not enough resources in the community for validating non-LTS > stables. See policy: here > http://doc.dpdk.org/guides/contributing/stable.html#stable-releases > I see. I wasn't aware of this. Thanks for clarifying. Thanks, Rahul > >> I think these need to have some testing to be in 18.11.2. I will apply > >> it, but requesting you to do some testing to check they're working as > >> you expect when 18.11.2 RC is available (ETA for RC-1, week of 20th May). > >> > > > > Sure, will test these devices on 18.11.2 RC as well. > > > > ok, sounds good, > > Kevin. > > > Thanks, > > Rahul > > > >> thanks, > >> Kevin. > >> > >>> Thanks, > >>> Rahul > >>> > >>>> > >>>>> Signed-off-by: Rahul Lakkireddy > >>>>> --- > >>>>> drivers/net/cxgbe/base/t4_pci_id_tbl.h | 52 +++++++++++++++++++++++++- > >>>>> 1 file changed, 51 insertions(+), 1 deletion(-) > >>>>> > >>>>> diff --git a/drivers/net/cxgbe/base/t4_pci_id_tbl.h b/drivers/net/cxgbe/base/t4_pci_id_tbl.h > >>>>> index 5f5cbe048..f5f027a2e 100644 > >>>>> --- a/drivers/net/cxgbe/base/t4_pci_id_tbl.h > >>>>> +++ b/drivers/net/cxgbe/base/t4_pci_id_tbl.h > >>>>> @@ -1,5 +1,5 @@ > >>>>> /* SPDX-License-Identifier: BSD-3-Clause > >>>>> - * Copyright(c) 2014-2018 Chelsio Communications. > >>>>> + * Copyright(c) 2014-2019 Chelsio Communications. > >>>>> * All rights reserved. > >>>>> */ > >>>>> > >>>>> @@ -103,6 +103,12 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5013), /* T580-chr */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5014), /* T580-so */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5015), /* T502-bt */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5016), /* T580-OCP-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5017), /* T520-OCP-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5018), /* T540-BT */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5019), /* T540-LP-BT */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x501a), /* T540-SO-BT */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x501b), /* T540-SO-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5080), /* Custom T540-cr */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5081), /* Custom T540-LL-cr */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5082), /* Custom T504-cr */ > >>>>> @@ -116,19 +122,63 @@ CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5090), /* Custom T540-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5091), /* Custom T522-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x5092), /* Custom T520-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5093), /* Custom T580-LP-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5094), /* Custom T540-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5095), /* Custom T540-CR-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5096), /* Custom T580-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5097), /* Custom T520-KR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5098), /* Custom 2x40G QSFP */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x5099), /* Custom 2x40G QSFP */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x509A), /* Custom T520-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x509B), /* Custom T540-CR LOM */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x509c), /* Custom T520-CR SFP+ LOM */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x509d), /* Custom T540-CR SFP+ */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x509e), /* Custom T520-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x509f), /* Custom T540-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a0), /* Custom T540-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a1), /* Custom T540-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a2), /* Custom T580-KR4 */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a3), /* Custom T580-KR4 */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a4), /* Custom 2x T540-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a5), /* Custom T522-BT */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a6), /* Custom T522-BT-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a7), /* Custom T580-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a8), /* Custom T580-KR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50a9), /* Custom T580-KR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50aa), /* Custom T580-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50ab), /* Custom T520-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50ac), /* Custom T540-BT */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50ad), /* Custom T520-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50ae), /* Custom T540-XL-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50af), /* Custom T580-KR-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x50b0), /* Custom T520-CR-LOM */ > >>>>> > >>>>> /* T6 adapter */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6001), /* T6225-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6002), /* T6225-SO-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6003), /* T6425-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6004), /* T6425-SO-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6005), /* T6225-OCP */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6006), /* T62100-OCP-SO */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6007), /* T62100-LP-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6008), /* T62100-SO-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6009), /* T6210-BT */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x600d), /* T62100-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6011), /* T6225-LL-CR */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6014), /* T61100-OCP-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6015), /* T6201-BT */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6080), /* Custom T6225-CR SFP28 */ > >>>>> CH_PCI_ID_TABLE_FENTRY(0x6081), /* Custom T62100-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6082), /* Custom T6225-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6083), /* Custom T62100-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6084), /* Custom T64100-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6085), /* Custom T6240-SO */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6086), /* Custom T6225-SO-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6087), /* Custom T6225-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6088), /* Custom T62100-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x6089), /* Custom T62100-KR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x608a), /* Custom T62100-CR */ > >>>>> + CH_PCI_ID_TABLE_FENTRY(0x608b), /* Custom T6225-CR */ > >>>>> CH_PCI_DEVICE_ID_TABLE_DEFINE_END; > >>>>> > >>>>> #endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */ > >>>>> > >>>> > >> >