* [dpdk-dev] [PATCH 01/11] net/bnxt: move tx bd checking to header file
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-23 11:44 ` Maxime Coquelin
2019-05-21 21:39 ` [dpdk-dev] [PATCH 02/11] net/bnxt: compute and store scattered RX status Ajit Khaparde
` (13 subsequent siblings)
14 siblings, 1 reply; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
From: Lance Richardson <lance.richardson@broadcom.com>
To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
vector-mode and non-vector transmit functions, move these functions
into bnxt_txr.h.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_txr.c | 15 ---------------
drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 9de12e0d0..16598ba63 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
return 0;
}
-static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
-{
- return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
- txq->tx_ring->tx_ring_struct->ring_mask);
-}
-
-static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
-{
- /* Tell compiler to fetch tx indices from memory. */
- rte_compiler_barrier();
-
- return ((txq->tx_ring->tx_ring_struct->ring_size -
- bnxt_tx_bds_in_hw(txq)) - 1);
-}
-
static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
struct bnxt_tx_queue *txq,
uint16_t *coal_pkts,
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index f802d5080..13ca04676 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -37,6 +37,21 @@ struct bnxt_sw_tx_bd {
unsigned short nr_bds;
};
+static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
+{
+ return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
+ txq->tx_ring->tx_ring_struct->ring_mask);
+}
+
+static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
+{
+ /* Tell compiler to fetch tx indices from memory. */
+ rte_compiler_barrier();
+
+ return ((txq->tx_ring->tx_ring_struct->ring_size -
+ bnxt_tx_bds_in_hw(txq)) - 1);
+}
+
void bnxt_free_tx_rings(struct bnxt *bp);
int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH 01/11] net/bnxt: move tx bd checking to header file
2019-05-21 21:39 ` [dpdk-dev] [PATCH 01/11] net/bnxt: move tx bd checking to header file Ajit Khaparde
@ 2019-05-23 11:44 ` Maxime Coquelin
0 siblings, 0 replies; 75+ messages in thread
From: Maxime Coquelin @ 2019-05-23 11:44 UTC (permalink / raw)
To: Ajit Khaparde, dev; +Cc: ferruh.yigit, Lance Richardson
On 5/21/19 11:39 PM, Ajit Khaparde wrote:
> From: Lance Richardson <lance.richardson@broadcom.com>
>
> To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
> vector-mode and non-vector transmit functions, move these functions
> into bnxt_txr.h.
>
> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> ---
> drivers/net/bnxt/bnxt_txr.c | 15 ---------------
> drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
> 2 files changed, 15 insertions(+), 15 deletions(-)
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH 02/11] net/bnxt: compute and store scattered RX status
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 01/11] net/bnxt: move tx bd checking to header file Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-23 11:47 ` Maxime Coquelin
2019-05-21 21:39 ` [dpdk-dev] [PATCH 03/11] net/bnxt: implement vector mode driver Ajit Khaparde
` (12 subsequent siblings)
14 siblings, 1 reply; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
From: Lance Richardson <lance.richardson@broadcom.com>
In preparation for a bnxt vector-mode driver, compute and store
scattered_rx status for the device when started.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index da0de211d..e0e0b72c6 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -624,6 +624,27 @@ static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
return 0;
}
+/*
+ * Determine whether the current configuration requires support for scattered
+ * receive; return 1 if scattered receive is required and 0 if not.
+ */
+static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
+{
+ uint16_t buf_size;
+ int i;
+
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
+
+ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
+ RTE_PKTMBUF_HEADROOM);
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
+ return 1;
+ }
+ return 0;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -642,6 +663,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
+
bnxt_link_update_op(eth_dev, 1);
if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH 02/11] net/bnxt: compute and store scattered RX status
2019-05-21 21:39 ` [dpdk-dev] [PATCH 02/11] net/bnxt: compute and store scattered RX status Ajit Khaparde
@ 2019-05-23 11:47 ` Maxime Coquelin
0 siblings, 0 replies; 75+ messages in thread
From: Maxime Coquelin @ 2019-05-23 11:47 UTC (permalink / raw)
To: Ajit Khaparde, dev; +Cc: ferruh.yigit, Lance Richardson
On 5/21/19 11:39 PM, Ajit Khaparde wrote:
> From: Lance Richardson<lance.richardson@broadcom.com>
>
> In preparation for a bnxt vector-mode driver, compute and store
> scattered_rx status for the device when started.
>
> Signed-off-by: Lance Richardson<lance.richardson@broadcom.com>
> Reviewed-by: Ajit Khaparde<ajit.khaparde@broadcom.com>
> ---
> drivers/net/bnxt/bnxt_ethdev.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH 03/11] net/bnxt: implement vector mode driver
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 01/11] net/bnxt: move tx bd checking to header file Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 02/11] net/bnxt: compute and store scattered RX status Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-23 12:18 ` Maxime Coquelin
2019-05-21 21:39 ` [dpdk-dev] [PATCH 04/11] net/bnxt: fix double counting VLAN tags Ajit Khaparde
` (11 subsequent siblings)
14 siblings, 1 reply; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
From: Lance Richardson <lance.richardson@broadcom.com>
Introduce vector mode support for the bnxt pmd.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
config/common_base | 1 +
drivers/net/bnxt/Makefile | 1 +
drivers/net/bnxt/bnxt_ethdev.c | 92 ++++-
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 +++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_txr.h | 11 +-
9 files changed, 598 insertions(+), 9 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
diff --git a/config/common_base b/config/common_base
index 6b96e0e80..1bbb7c10b 100644
--- a/config/common_base
+++ b/config/common_base
@@ -212,6 +212,7 @@ CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC=n
# Compile burst-oriented Broadcom BNXT PMD driver
#
CONFIG_RTE_LIBRTE_BNXT_PMD=y
+CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR=n
#
# Compile burst-oriented Chelsio Terminator (CXGBE) PMD
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
index 8be3cb0e4..9e006b5d1 100644
--- a/drivers/net/bnxt/Makefile
+++ b/drivers/net/bnxt/Makefile
@@ -41,6 +41,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_util.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += rte_pmd_bnxt.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR) += bnxt_rxtx_vec_sse.c
#
# Export include files
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index e0e0b72c6..064a153ec 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -645,6 +645,67 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
return 0;
}
+static eth_rx_burst_t
+bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ /*
+ * Vector mode receive can be enabled only if scatter rx is not
+ * in use and rx offloads are limited to VLAN stripping and
+ * CRC stripping.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.rxmode.offloads &
+ ~(DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_KEEP_CRC |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM |
+ DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_VLAN_FILTER))) {
+ PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_recv_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d rx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.rxmode.offloads);
+#endif
+ return bnxt_recv_pkts;
+}
+
+static eth_tx_burst_t
+bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ /*
+ * Vector mode receive can be enabled only if scatter tx is not
+ * in use and tx offloads other than VLAN insertion are not
+ * in use.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.txmode.offloads &
+ ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
+ PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_xmit_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d tx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.txmode.offloads);
+#endif
+ return bnxt_xmit_pkts;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -675,6 +736,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
+ eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
bp->flags |= BNXT_FLAG_INIT_DONE;
return 0;
@@ -1597,6 +1660,8 @@ bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
+ uint32_t new_pkt_size = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS;
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_dev_info dev_info;
uint32_t rc = 0;
@@ -1610,6 +1675,23 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
return -EINVAL;
}
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ /*
+ * If vector-mode tx/rx is active, disallow any MTU change that would
+ * require scattered receive support.
+ */
+ if (eth_dev->data->dev_started &&
+ (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
+ eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
+ (new_pkt_size >
+ eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
+ PMD_DRV_LOG(ERR,
+ "MTU change would require scattered rx support. ");
+ PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
+ return -EINVAL;
+ }
+#endif
+
if (new_mtu > ETHER_MTU) {
bp->flags |= BNXT_FLAG_JUMBO;
bp->eth_dev->data->dev_conf.rxmode.offloads |=
@@ -1620,8 +1702,7 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
bp->flags &= ~BNXT_FLAG_JUMBO;
}
- eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
- new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
+ eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
eth_dev->data->mtu = new_mtu;
PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
@@ -2655,9 +2736,10 @@ bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
RTE_PTYPE_UNKNOWN
};
- if (dev->rx_pkt_burst == bnxt_recv_pkts)
- return ptypes;
- return NULL;
+ if (!dev->rx_pkt_burst)
+ return NULL;
+
+ return ptypes;
}
static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index 1446d784f..fd3d0bd73 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -10,7 +10,8 @@
#include <rte_memory.h>
-#define RING_NEXT(ring, idx) (((idx) + 1) & (ring)->ring_mask)
+#define RING_ADV(ring, idx, n) (((idx) + (n)) & (ring)->ring_mask)
+#define RING_NEXT(ring, idx) RING_ADV(ring, idx, 1)
#define DB_IDX_MASK 0xffffff
#define DB_IDX_VALID (0x1 << 26)
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index 17e2909a7..ff219f4b8 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -355,6 +355,11 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
RTE_ETH_QUEUE_STATE_STARTED;
eth_dev->data->rx_queue_state[queue_idx] = queue_state;
rte_spinlock_init(&rxq->lock);
+
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ bnxt_rxq_vec_setup(rxq);
+#endif
+
out:
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h
index e5d6001d3..057a59e2c 100644
--- a/drivers/net/bnxt/bnxt_rxq.h
+++ b/drivers/net/bnxt/bnxt_rxq.h
@@ -22,6 +22,10 @@ struct bnxt_rx_queue {
uint16_t nb_rx_hold; /* num held free RX desc */
uint16_t rx_free_thresh; /* max free RX desc to hold */
uint16_t queue_id; /* RX queue index */
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ uint16_t rxrearm_nb; /* number of descs to reinit. */
+ uint16_t rxrearm_start; /* next desc index to reinit. */
+#endif
uint16_t reg_idx; /* RX queue register index */
uint16_t port_id; /* Device port identifier */
uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 3815a2199..cf1c7e5cf 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -7,7 +7,7 @@
#define _BNXT_RXR_H_
#define B_RX_DB(db, prod) \
- (*(uint32_t *)db = (DB_KEY_RX | prod))
+ (*(uint32_t *)db = (DB_KEY_RX | (prod)))
#define BNXT_TPA_L4_SIZE(x) \
{ \
@@ -110,4 +110,11 @@ int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
+int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
+#endif
+
#endif
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
new file mode 100644
index 000000000..1c32c986c
--- /dev/null
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright(c) 2019 Broadcom All rights reserved. */
+
+#include <inttypes.h>
+#include <stdbool.h>
+
+#include <rte_bitmap.h>
+#include <rte_byteorder.h>
+#include <rte_malloc.h>
+#include <rte_memory.h>
+#if defined(RTE_ARCH_X86)
+#include <tmmintrin.h>
+#else
+#error "bnxt vector pmd: unsupported target."
+#endif
+
+#include "bnxt.h"
+#include "bnxt_cpr.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxr.h"
+#include "bnxt_rxq.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "bnxt_txq.h"
+#include "bnxt_txr.h"
+
+/*
+ * RX Ring handling
+ */
+
+#define RTE_BNXT_MAX_RX_BURST 32
+#define RTE_BNXT_MAX_TX_BURST 32
+#define RTE_BNXT_RXQ_REARM_THRESH 32
+#define RTE_BNXT_DESCS_PER_LOOP 4
+
+static inline void
+bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
+{
+ struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
+ struct bnxt_sw_rx_bd *rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
+ struct rte_mbuf *mb0, *mb1;
+ int i;
+
+ const __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, 0);
+ const __m128i addrmask = _mm_set_epi64x(UINT64_MAX, 0);
+
+ /* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
+ if (rte_mempool_get_bulk(rxq->mb_pool,
+ (void *)rx_bufs,
+ RTE_BNXT_RXQ_REARM_THRESH) < 0) {
+ rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
+ RTE_BNXT_RXQ_REARM_THRESH;
+
+ return;
+ }
+
+ /* Initialize the mbufs in vector, process 2 mbufs in one loop */
+ for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
+ __m128i buf_addr0, buf_addr1;
+ __m128i rxbd0, rxbd1;
+
+ mb0 = rx_bufs[0].mbuf;
+ mb1 = rx_bufs[1].mbuf;
+
+ /* Load address fields from both mbufs */
+ buf_addr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
+ buf_addr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
+
+ /* Load both rx descriptors (preserving some existing fields) */
+ rxbd0 = _mm_loadu_si128((__m128i *)(rxbds + 0));
+ rxbd1 = _mm_loadu_si128((__m128i *)(rxbds + 1));
+
+ /* Add default offset to buffer address. */
+ buf_addr0 = _mm_add_epi64(buf_addr0, hdr_room);
+ buf_addr1 = _mm_add_epi64(buf_addr1, hdr_room);
+
+ /* Clear all fields except address. */
+ buf_addr0 = _mm_and_si128(buf_addr0, addrmask);
+ buf_addr1 = _mm_and_si128(buf_addr1, addrmask);
+
+ /* Clear address field in descriptor. */
+ rxbd0 = _mm_andnot_si128(addrmask, rxbd0);
+ rxbd1 = _mm_andnot_si128(addrmask, rxbd1);
+
+ /* Set address field in descriptor. */
+ rxbd0 = _mm_add_epi64(rxbd0, buf_addr0);
+ rxbd1 = _mm_add_epi64(rxbd1, buf_addr1);
+
+ /* Store descriptors to memory. */
+ _mm_store_si128((__m128i *)(rxbds++), rxbd0);
+ _mm_store_si128((__m128i *)(rxbds++), rxbd1);
+ }
+
+ rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
+ B_RX_DB(rxr->rx_doorbell, rxq->rxrearm_start - 1);
+ if (rxq->rxrearm_start >= rxq->nb_rx_desc)
+ rxq->rxrearm_start = 0;
+
+ rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
+}
+
+static uint32_t
+bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ uint32_t l3, pkt_type = 0;
+ uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
+ uint32_t flags_type;
+
+ vlan = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ t_ipcs = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
+ ip6 = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
+
+ flags_type = rxcmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
+
+ if (!t_ipcs && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_ipcs && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_ipcs && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ return pkt_type;
+}
+
+uint16_t
+bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_rx_queue *rxq = rx_queue;
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ int nb_rx_pkts = 0;
+ struct rx_pkt_cmpl *rxcmp;
+ bool evt = false;
+ const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
+ const __m128i shuf_msk =
+ _mm_set_epi8(15, 14, 13, 12, /* rss */
+ 0xFF, 0xFF, /* vlan_tci (zeroes) */
+ 3, 2, /* data_len */
+ 0xFF, 0xFF, 3, 2, /* pkt_len */
+ 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
+
+ /* If Rx Q was stopped return */
+ if (rxq->rx_deferred_start)
+ return 0;
+
+ if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
+ bnxt_rxq_rearm(rxq, rxr);
+
+ /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
+ nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
+
+ /* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP */
+ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
+
+ /* Handle RX burst request */
+ while (1) {
+ cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
+
+ rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
+
+ if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
+ break;
+
+ cpr->valid = FLIP_VALID(cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ if (likely(CMP_TYPE(rxcmp) == RX_PKT_CMPL_TYPE_RX_L2)) {
+ struct rx_pkt_cmpl_hi *rxcmp1;
+ uint32_t tmp_raw_cons;
+ uint16_t cp_cons;
+ struct rte_mbuf *mbuf;
+ __m128i mm_rxcmp, pkt_mb;
+
+ tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
+ cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
+ rxcmp1 = (struct rx_pkt_cmpl_hi *)
+ &cpr->cp_desc_ring[cp_cons];
+
+ if (!CMP_VALID(rxcmp1, tmp_raw_cons,
+ cpr->cp_ring_struct))
+ break;
+
+ raw_cons = tmp_raw_cons;
+ cons = rxcmp->opaque;
+
+ mbuf = rxr->rx_buf_ring[cons].mbuf;
+ rte_prefetch0(mbuf);
+ rxr->rx_buf_ring[cons].mbuf = NULL;
+
+ cpr->valid = FLIP_VALID(cp_cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ /* Set constant fields from mbuf initializer. */
+ _mm_store_si128((__m128i *)&mbuf->rearm_data,
+ mbuf_init);
+
+ /* Set mbuf pkt_len, data_len, and rss_hash fields. */
+ mm_rxcmp = _mm_load_si128((__m128i *)rxcmp);
+ pkt_mb = _mm_shuffle_epi8(mm_rxcmp, shuf_msk);
+ _mm_storeu_si128((void *)&mbuf->rx_descriptor_fields1,
+ pkt_mb);
+
+ rte_compiler_barrier();
+
+ if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
+ mbuf->ol_flags |= PKT_RX_RSS_HASH;
+
+ if (rxcmp1->flags2 &
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
+ mbuf->vlan_tci = rxcmp1->metadata &
+ (RX_PKT_CMPL_METADATA_VID_MASK |
+ RX_PKT_CMPL_METADATA_DE |
+ RX_PKT_CMPL_METADATA_PRI_MASK);
+ mbuf->ol_flags |= PKT_RX_VLAN;
+ }
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
+ rx_pkts[nb_rx_pkts++] = mbuf;
+ } else {
+ evt =
+ bnxt_event_hwrm_resp_handler(rxq->bp,
+ (struct cmpl_base *)rxcmp);
+ }
+
+ raw_cons = NEXT_RAW_CMP(raw_cons);
+ if (nb_rx_pkts == nb_pkts || evt)
+ break;
+ }
+ rxr->rx_prod = RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
+
+ rxq->rxrearm_nb += nb_rx_pkts;
+ cpr->cp_raw_cons = raw_cons;
+ if (nb_rx_pkts || evt)
+ B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
+
+ return nb_rx_pkts;
+}
+
+static inline void bnxt_next_cmpl(struct bnxt_cp_ring_info *cpr, uint32_t *idx,
+ bool *v, uint32_t inc)
+{
+ *idx += inc;
+ if (unlikely(*idx == cpr->cp_ring_struct->ring_size)) {
+ *v = !*v;
+ *idx = 0;
+ }
+}
+
+static void
+bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
+{
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ struct rte_mbuf **free = txq->free;
+ uint16_t cons = txr->tx_cons;
+ unsigned int blk = 0;
+
+ while (nr_pkts--) {
+ struct bnxt_sw_tx_bd *tx_buf;
+ struct rte_mbuf *mbuf;
+
+ tx_buf = &txr->tx_buf_ring[cons];
+ cons = RING_NEXT(txr->tx_ring_struct, cons);
+ mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
+ tx_buf->mbuf = NULL;
+
+ if (blk && mbuf->pool != free[0]->pool) {
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+ blk = 0;
+ }
+ free[blk++] = mbuf;
+ }
+ if (blk)
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+
+ txr->tx_cons = cons;
+}
+
+static void
+bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
+{
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ uint32_t nb_tx_pkts = 0;
+ struct tx_cmpl *txcmp;
+ struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
+ struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
+ uint32_t ring_mask = cp_ring_struct->ring_mask;
+
+ do {
+ cons = RING_CMPL(ring_mask, raw_cons);
+ txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
+
+ if (!CMPL_VALID(txcmp, cpr->valid))
+ break;
+ bnxt_next_cmpl(cpr, &cons, &cpr->valid, 1);
+ rte_prefetch0(&cp_desc_ring[cons]);
+
+ if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ nb_tx_pkts += txcmp->opaque;
+ else
+ RTE_LOG_DP(ERR, PMD,
+ "Unhandled CMP type %02x\n",
+ CMP_TYPE(txcmp));
+ raw_cons = cons;
+ } while (nb_tx_pkts < ring_mask);
+
+ if (nb_tx_pkts) {
+ bnxt_tx_cmp_vec(txq, nb_tx_pkts);
+ cpr->cp_raw_cons = raw_cons;
+ B_CP_DB(cpr, raw_cons, ring_mask);
+ }
+}
+
+#define TX_BD_FLAGS_CMPL ((1 << TX_BD_LONG_FLAGS_BD_CNT_SFT) | \
+ TX_BD_SHORT_FLAGS_COAL_NOW | \
+ TX_BD_SHORT_TYPE_TX_BD_SHORT | \
+ TX_BD_LONG_FLAGS_PACKET_END)
+
+#define TX_BD_FLAGS_NOCMPL (TX_BD_FLAGS_CMPL | TX_BD_LONG_FLAGS_NO_CMPL)
+
+static inline uint32_t
+bnxt_xmit_flags_len(uint16_t len, uint16_t flags)
+{
+ switch (len >> 9) {
+ case 0:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT512;
+ case 1:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT1K;
+ case 2:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ case 3:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ default:
+ return flags | TX_BD_LONG_FLAGS_LHINT_GTE2K;
+ }
+}
+
+static uint16_t
+bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_tx_queue *txq = tx_queue;
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ uint16_t prod = txr->tx_prod;
+ struct rte_mbuf *tx_mbuf;
+ struct tx_bd_long *txbd = NULL;
+ struct bnxt_sw_tx_bd *tx_buf;
+ uint16_t to_send;
+
+ nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
+
+ if (unlikely(nb_pkts == 0))
+ return 0;
+
+ /* Handle TX burst request */
+ to_send = nb_pkts;
+ while (to_send) {
+ tx_mbuf = *tx_pkts++;
+ rte_prefetch0(tx_mbuf);
+
+ tx_buf = &txr->tx_buf_ring[prod];
+ tx_buf->mbuf = tx_mbuf;
+ tx_buf->nr_bds = 1;
+
+ txbd = &txr->tx_desc_ring[prod];
+ txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
+ txbd->len = tx_mbuf->data_len;
+ txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
+ TX_BD_FLAGS_NOCMPL);
+ prod = RING_NEXT(txr->tx_ring_struct, prod);
+ to_send--;
+ }
+
+ /* Request a completion for last packet in burst */
+ if (txbd) {
+ txbd->opaque = nb_pkts;
+ txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
+ }
+
+ rte_compiler_barrier();
+ B_TX_DB(txr->tx_doorbell, prod);
+
+ txr->tx_prod = prod;
+
+ return nb_pkts;
+}
+
+uint16_t
+bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ int nb_sent = 0;
+ struct bnxt_tx_queue *txq = tx_queue;
+
+ /* Tx queue was stopped; wait for it to be restarted */
+ if (unlikely(txq->tx_deferred_start)) {
+ PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
+ return 0;
+ }
+
+ /* Handle TX completions */
+ if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
+ bnxt_handle_tx_cp_vec(txq);
+
+ while (nb_pkts) {
+ uint16_t ret, num;
+
+ num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
+ ret = bnxt_xmit_fixed_burst_vec(tx_queue,
+ &tx_pkts[nb_sent],
+ num);
+ nb_sent += ret;
+ nb_pkts -= ret;
+ if (ret < num)
+ break;
+ }
+
+ return nb_sent;
+}
+
+int __attribute__((cold))
+bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
+{
+ uintptr_t p;
+ struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
+
+ mb_def.nb_segs = 1;
+ mb_def.data_off = RTE_PKTMBUF_HEADROOM;
+ mb_def.port = rxq->port_id;
+ rte_mbuf_refcnt_set(&mb_def, 1);
+
+ /* prevent compiler reordering: rearm_data covers previous fields */
+ rte_compiler_barrier();
+ p = (uintptr_t)&mb_def.rearm_data;
+ rxq->mbuf_initializer = *(uint64_t *)p;
+ rxq->rxrearm_nb = 0;
+ rxq->rxrearm_start = 0;
+ return 0;
+}
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index 13ca04676..c28bd9c18 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -37,13 +37,15 @@ struct bnxt_sw_tx_bd {
unsigned short nr_bds;
};
-static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
+static inline uint32_t
+bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
{
return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
txq->tx_ring->tx_ring_struct->ring_mask);
}
-static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
+static inline uint32_t
+bnxt_tx_avail(struct bnxt_tx_queue *txq)
{
/* Tell compiler to fetch tx indices from memory. */
rte_compiler_barrier();
@@ -57,6 +59,11 @@ int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+uint16_t bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
+#endif
+
int bnxt_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
int bnxt_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH 03/11] net/bnxt: implement vector mode driver
2019-05-21 21:39 ` [dpdk-dev] [PATCH 03/11] net/bnxt: implement vector mode driver Ajit Khaparde
@ 2019-05-23 12:18 ` Maxime Coquelin
2019-05-23 19:23 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Maxime Coquelin @ 2019-05-23 12:18 UTC (permalink / raw)
To: Ajit Khaparde, dev; +Cc: ferruh.yigit, Lance Richardson
On 5/21/19 11:39 PM, Ajit Khaparde wrote:
> From: Lance Richardson <lance.richardson@broadcom.com>
>
> Introduce vector mode support for the bnxt pmd.
>
> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> ---
> config/common_base | 1 +
> drivers/net/bnxt/Makefile | 1 +
> drivers/net/bnxt/bnxt_ethdev.c | 92 ++++-
> drivers/net/bnxt/bnxt_ring.h | 3 +-
> drivers/net/bnxt/bnxt_rxq.c | 5 +
> drivers/net/bnxt/bnxt_rxq.h | 4 +
> drivers/net/bnxt/bnxt_rxr.h | 9 +-
> drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 +++++++++++++++++++++++++++
> drivers/net/bnxt/bnxt_txr.h | 11 +-
> 9 files changed, 598 insertions(+), 9 deletions(-)
> create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
>
> diff --git a/config/common_base b/config/common_base
> index 6b96e0e80..1bbb7c10b 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -212,6 +212,7 @@ CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC=n
> # Compile burst-oriented Broadcom BNXT PMD driver
> #
> CONFIG_RTE_LIBRTE_BNXT_PMD=y
> +CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR=n
>
> #
> # Compile burst-oriented Chelsio Terminator (CXGBE) PMD
> diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
> index 8be3cb0e4..9e006b5d1 100644
> --- a/drivers/net/bnxt/Makefile
> +++ b/drivers/net/bnxt/Makefile
> @@ -41,6 +41,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
> SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
> SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_util.c
> SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += rte_pmd_bnxt.c
> +SRCS-$(CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR) += bnxt_rxtx_vec_sse.c
>
> #
> # Export include files
How do we enable it with Meson build? It seems to be missing.
> diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> index e0e0b72c6..064a153ec 100644
> --- a/drivers/net/bnxt/bnxt_ethdev.c
> +++ b/drivers/net/bnxt/bnxt_ethdev.c
> @@ -645,6 +645,67 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
> return 0;
> }
>
> +static eth_rx_burst_t
> +bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
> +{
> +#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
> + /*
> + * Vector mode receive can be enabled only if scatter rx is not
> + * in use and rx offloads are limited to VLAN stripping and
> + * CRC stripping.
> + */
> + if (!eth_dev->data->scattered_rx &&
> + !(eth_dev->data->dev_conf.rxmode.offloads &
> + ~(DEV_RX_OFFLOAD_VLAN_STRIP |
> + DEV_RX_OFFLOAD_KEEP_CRC |
> + DEV_RX_OFFLOAD_JUMBO_FRAME |
> + DEV_RX_OFFLOAD_IPV4_CKSUM |
> + DEV_RX_OFFLOAD_UDP_CKSUM |
> + DEV_RX_OFFLOAD_TCP_CKSUM |
> + DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
> + DEV_RX_OFFLOAD_VLAN_FILTER))) {
> + PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
> + eth_dev->data->port_id);
> + return bnxt_recv_pkts_vec;
> + }
> + PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
> + eth_dev->data->port_id);
> + PMD_DRV_LOG(INFO,
> + "Port %d scatter: %d rx offload: %" PRIX64 "\n",
> + eth_dev->data->port_id,
> + eth_dev->data->scattered_rx,
> + eth_dev->data->dev_conf.rxmode.offloads);
> +#endif
I think we would better have a stub for bnxt_recv_pkts_vec() when
RTE_LIBRTE_BNXT_INC_VECTOR isn't set, that would avoid having all these
#ifdeferies in this file.
> + return bnxt_recv_pkts;
> +}
> +
> +static eth_tx_burst_t
> +bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
> +{
> +#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
> + /*
> + * Vector mode receive can be enabled only if scatter tx is not
> + * in use and tx offloads other than VLAN insertion are not
> + * in use.
> + */
> + if (!eth_dev->data->scattered_rx &&
> + !(eth_dev->data->dev_conf.txmode.offloads &
> + ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
> + PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
> + eth_dev->data->port_id);
> + return bnxt_xmit_pkts_vec;
> + }
> + PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
> + eth_dev->data->port_id);
> + PMD_DRV_LOG(INFO,
> + "Port %d scatter: %d tx offload: %" PRIX64 "\n",
> + eth_dev->data->port_id,
> + eth_dev->data->scattered_rx,
> + eth_dev->data->dev_conf.txmode.offloads);
> +#endif
> + return bnxt_xmit_pkts;
> +}
> +
> static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
> {
> struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
> @@ -675,6 +736,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
> if (rc)
> goto error;
>
> + eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
> + eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
> bp->flags |= BNXT_FLAG_INIT_DONE;
> return 0;
>
> @@ -1597,6 +1660,8 @@ bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
>
> static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
> {
> + uint32_t new_pkt_size = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
> + VLAN_TAG_SIZE * BNXT_NUM_VLANS;
> struct bnxt *bp = eth_dev->data->dev_private;
> struct rte_eth_dev_info dev_info;
> uint32_t rc = 0;
> @@ -1610,6 +1675,23 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
> return -EINVAL;
> }
>
> +#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
> + /*
> + * If vector-mode tx/rx is active, disallow any MTU change that would
> + * require scattered receive support.
> + */
> + if (eth_dev->data->dev_started &&
> + (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
> + eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
> + (new_pkt_size >
> + eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
> + PMD_DRV_LOG(ERR,
> + "MTU change would require scattered rx support. ");
> + PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
> + return -EINVAL;
> + }
> +#endif
> +
> if (new_mtu > ETHER_MTU) {
> bp->flags |= BNXT_FLAG_JUMBO;
> bp->eth_dev->data->dev_conf.rxmode.offloads |=
> @@ -1620,8 +1702,7 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
> bp->flags &= ~BNXT_FLAG_JUMBO;
> }
>
> - eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
> - new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
> + eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
>
> eth_dev->data->mtu = new_mtu;
> PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
> @@ -2655,9 +2736,10 @@ bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
> RTE_PTYPE_UNKNOWN
> };
>
> - if (dev->rx_pkt_burst == bnxt_recv_pkts)
> - return ptypes;
> - return NULL;
> + if (!dev->rx_pkt_burst)
> + return NULL;
> +
> + return ptypes;
> }
>
> static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
...
> diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
> index 13ca04676..c28bd9c18 100644
> --- a/drivers/net/bnxt/bnxt_txr.h
> +++ b/drivers/net/bnxt/bnxt_txr.h
> @@ -37,13 +37,15 @@ struct bnxt_sw_tx_bd {
> unsigned short nr_bds;
> };
>
> -static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
> +static inline uint32_t
> +bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
If to be done, it should be done in patch 1.
> {
> return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
> txq->tx_ring->tx_ring_struct->ring_mask);
> }
>
> -static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
> +static inline uint32_t
> +bnxt_tx_avail(struct bnxt_tx_queue *txq)
Ditto
> {
> /* Tell compiler to fetch tx indices from memory. */
> rte_compiler_barrier();
> @@ -57,6 +59,11 @@ int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
> int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
> uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
> uint16_t nb_pkts);
> +#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
> +uint16_t bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
> + uint16_t nb_pkts);
> +#endif
> +
> int bnxt_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
> int bnxt_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
>
>
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH 03/11] net/bnxt: implement vector mode driver
2019-05-23 12:18 ` Maxime Coquelin
@ 2019-05-23 19:23 ` Lance Richardson
0 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-23 19:23 UTC (permalink / raw)
To: Maxime Coquelin; +Cc: Ajit Khaparde, dev, ferruh.yigit
Hi Maxime, thanks for taking the time to review this.
On Thu, May 23, 2019 at 8:18 AM Maxime Coquelin
<maxime.coquelin@redhat.com> wrote:
...
> How do we enable it with Meson build? It seems to be missing.
Ah, thanks for pointing that out, I had completely missed the Meson
piece. Will fix in v2.
>
> I think we would better have a stub for bnxt_recv_pkts_vec() when
> RTE_LIBRTE_BNXT_INC_VECTOR isn't set, that would avoid having all these
> #ifdeferies in this file.
>
I'm having trouble picturing how having stubs would reduce the number
of #ifdefs,
but maybe the resulting code could be cleaner. I'll see what can be done for v2.
(Stubs with weak linkage might help, but that approach seems to be going
out of favor in http://patchwork.dpdk.org/patch/53498/).
> > -static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
> > +static inline uint32_t
> > +bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
>
> If to be done, it should be done in patch 1.
>
> > {
> > return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
> > txq->tx_ring->tx_ring_struct->ring_mask);
> > }
> >
> > -static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
> > +static inline uint32_t
> > +bnxt_tx_avail(struct bnxt_tx_queue *txq)
>
> Ditto
>
I'll drop both of those changes from this patch in v2 (they don't seem
to be needed
since checkpatch was happy with patch 1).
Thanks again,
Lance
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH 04/11] net/bnxt: fix double counting VLAN tags
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (2 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 03/11] net/bnxt: implement vector mode driver Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-23 12:21 ` Maxime Coquelin
2019-05-21 21:39 ` [dpdk-dev] [PATCH 05/11] net/bnxt: fix RSS reta indirection table update Ajit Khaparde
` (10 subsequent siblings)
14 siblings, 1 reply; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
From: Lance Richardson <lance.richardson@broadcom.com>
When determining whether scattered receive mode is needed, the
size of a QinQ header is being added to rxmode.max_rx_pkt_len
before comparing to the receive buffer size, however max_rx_pkt_len
already accounts for the QinQ header size. Fix by simply comparing
rxmode.max_rx_pkt_len against the buffer size.
Fixes: daef48efe5e5 ("net/bnxt: support set MTU")
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 064a153ec..52a6b94e0 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -638,8 +638,7 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
RTE_PKTMBUF_HEADROOM);
- if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
- VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
return 1;
}
return 0;
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH 04/11] net/bnxt: fix double counting VLAN tags
2019-05-21 21:39 ` [dpdk-dev] [PATCH 04/11] net/bnxt: fix double counting VLAN tags Ajit Khaparde
@ 2019-05-23 12:21 ` Maxime Coquelin
2019-05-23 18:53 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Maxime Coquelin @ 2019-05-23 12:21 UTC (permalink / raw)
To: Ajit Khaparde, dev; +Cc: ferruh.yigit, Lance Richardson
On 5/21/19 11:39 PM, Ajit Khaparde wrote:
> From: Lance Richardson <lance.richardson@broadcom.com>
>
> When determining whether scattered receive mode is needed, the
> size of a QinQ header is being added to rxmode.max_rx_pkt_len
> before comparing to the receive buffer size, however max_rx_pkt_len
> already accounts for the QinQ header size. Fix by simply comparing
> rxmode.max_rx_pkt_len against the buffer size.
>
> Fixes: daef48efe5e5 ("net/bnxt: support set MTU")
> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> ---
> drivers/net/bnxt/bnxt_ethdev.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> index 064a153ec..52a6b94e0 100644
> --- a/drivers/net/bnxt/bnxt_ethdev.c
> +++ b/drivers/net/bnxt/bnxt_ethdev.c
> @@ -638,8 +638,7 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
>
> buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
> RTE_PKTMBUF_HEADROOM);
> - if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
> - VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
> + if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
> return 1;
> }
> return 0;
>
Isn't it fixing patch 2?
If so, Fixes line is wrong, and it should be squashed directly into
patch 2.
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH 05/11] net/bnxt: fix RSS reta indirection table update
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (3 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 04/11] net/bnxt: fix double counting VLAN tags Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 06/11] net/bnxt: use reta update mask and translate qid to grp id Ajit Khaparde
` (9 subsequent siblings)
14 siblings, 0 replies; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Rahul Gupta, Lance Richardson
We are trying to update the indirection table for all the VNICs.
We should update the table only for the default vnic0.
This patch fixes the above issue.
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Rahul Gupta <rahul.gupta@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 18 ++++++++++--------
drivers/net/bnxt/bnxt_hwrm.c | 1 +
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 52a6b94e0..2d892cd4f 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -983,8 +983,13 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
- struct bnxt_vnic_info *vnic;
- int i;
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+
+ /* Update the default RSS VNIC */
+ if (!vnic)
+ return -EINVAL;
+ if (!vnic->rss_table)
+ return -EINVAL;
if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
return -EINVAL;
@@ -995,12 +1000,9 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
"(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
return -EINVAL;
}
- /* Update the RSS VNIC(s) */
- for (i = 0; i < bp->max_vnics; i++) {
- vnic = &bp->vnic_info[i];
- memcpy(vnic->rss_table, reta_conf, reta_size);
- bnxt_hwrm_vnic_rss_cfg(bp, vnic);
- }
+
+ memcpy(vnic->rss_table, reta_conf, reta_size);
+ bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index eb5c41ebb..8c4fa556d 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1607,6 +1607,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
req.hash_key_tbl_addr =
rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
+ req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH 06/11] net/bnxt: use reta update mask and translate qid to grp id
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (4 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 05/11] net/bnxt: fix RSS reta indirection table update Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 07/11] net/bnxt: fix reta query op Ajit Khaparde
` (8 subsequent siblings)
14 siblings, 0 replies; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
From: Lance Richardson <lance.richardson@broadcom.com>
Fix the reta update function to only update table entries that are
selected by the update mask. Translate queue number to firmware
group ID when updating an entry.
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 39 ++++++++++++++++++++++++++++------
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 2d892cd4f..d2b89a217 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -977,6 +977,15 @@ static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
}
+/* Return bnxt_rx_queue pointer corresponding to a given rxq. */
+static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
+{
+ if (qid >= bp->rx_nr_rings)
+ return NULL;
+
+ return bp->eth_dev->data->rx_queues[qid];
+}
+
static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
@@ -984,24 +993,42 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft;
+ int i;
- /* Update the default RSS VNIC */
- if (!vnic)
- return -EINVAL;
if (!vnic->rss_table)
return -EINVAL;
if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- memcpy(vnic->rss_table, reta_conf, reta_size);
+ for (i = 0; i < reta_size; i++) {
+ struct bnxt_rx_queue *rxq;
+
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (!(reta_conf[idx].mask & (1ULL << sft)))
+ continue;
+
+ rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
+ if (!rxq) {
+ PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
+ return -EINVAL;
+ }
+
+ vnic->rss_table[i] =
+ vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
+ }
+
bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH 07/11] net/bnxt: fix reta query op
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (5 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 06/11] net/bnxt: use reta update mask and translate qid to grp id Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 08/11] net/bnxt: update HWRM API Ajit Khaparde
` (7 subsequent siblings)
14 siblings, 0 replies; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
From: Lance Richardson <lance.richardson@broadcom.com>
Fix reta query op to only return table entries as identfied by the
provided mask. Translate firmware group IDs to queue numbers.
Removed extraneous code from bnxt_reta_query_op().
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 47 +++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index d2b89a217..70924d93d 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -618,12 +618,6 @@ static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
eth_dev->data->port_id);
}
-static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
-{
- bnxt_print_link_info(eth_dev);
- return 0;
-}
-
/*
* Determine whether the current configuration requires support for scattered
* receive; return 1 if scattered receive is required and 0 if not.
@@ -986,6 +980,19 @@ static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
return bp->eth_dev->data->rx_queues[qid];
}
+/* Return rxq corresponding to a given rss table ring/group ID. */
+static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
+{
+ unsigned int i;
+
+ for (i = 0; i < bp->rx_nr_rings; i++) {
+ if (bp->grp_info[i].fw_grp_id == fwr)
+ return i;
+ }
+
+ return INVALID_HW_RING_ID;
+}
+
static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
@@ -1039,8 +1046,8 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
- struct rte_intr_handle *intr_handle
- = &bp->pdev->intr_handle;
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft, i;
/* Retrieve from the default VNIC */
if (!vnic)
@@ -1048,18 +1055,28 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
if (!vnic->rss_table)
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* EW - need to revisit here copying from uint64_t to uint16_t */
- memcpy(reta_conf, vnic->rss_table, reta_size);
- if (rte_intr_allow_others(intr_handle)) {
- if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
- bnxt_dev_lsc_intr_setup(eth_dev);
+ for (idx = 0, i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (reta_conf[idx].mask & (1ULL << sft)) {
+ uint16_t qid;
+
+ qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
+
+ if (qid == INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
+ return -EINVAL;
+ }
+ reta_conf[idx].reta[sft] = qid;
+ }
}
return 0;
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH 08/11] net/bnxt: update HWRM API
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (6 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 07/11] net/bnxt: fix reta query op Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 09/11] net/bnxt: update HWRM version Ajit Khaparde
` (6 subsequent siblings)
14 siblings, 0 replies; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
Update HWRM API to version 1.10.0.19
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3112 +++++++++++++++++++-----
1 file changed, 2514 insertions(+), 598 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index e80057936..ea9a7d40e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2018 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Limited
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -68,9 +68,9 @@ struct hwrm_resp_hdr {
/* RoCE slow path command */
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
/* RoCE slow path command to query CC Gen1 support. */
-#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
/* RoCE slow path command to modify CC Gen1 support. */
-#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
/* Engine CKV - The device's serial number. */
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
/* Engine CKV - Per-function random nonce data. */
@@ -366,6 +366,7 @@ struct cmd_nums {
#define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
#define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
#define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
+ #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
#define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
#define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
@@ -442,6 +443,14 @@ struct cmd_nums {
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -591,61 +600,79 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ /*
+ * This error code is only reported by firmware when the specific
+ * request is not able to process when the HOT reset in progress.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances are not capable of hot reset.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ /*
+ * This value indicates that the HWRM response is in TLV format and
+ * should be interpreted as one or more TLVs starting with the
+ * hwrm_resp_hdr TLV. This value is not an indicatation of any error
+ * by itself, just an indicatation that the response should be parsed
+ * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
+ */
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -705,11 +732,11 @@ struct hwrm_err_output {
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
#define HWRM_VERSION_MAJOR 1
-#define HWRM_VERSION_MINOR 9
-#define HWRM_VERSION_UPDATE 2
+#define HWRM_VERSION_MINOR 10
+#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 53
-#define HWRM_VERSION_STR "1.9.2.53"
+#define HWRM_VERSION_RSVD 19
+#define HWRM_VERSION_STR "1.10.0.19"
/****************
* hwrm_ver_get *
@@ -959,6 +986,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
UINT32_C(0x100)
+ /*
+ * If set to 1, firmware is capable to support flow aging.
+ * If set to 0, firmware is not capable to support flow aging.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
+ UINT32_C(0x200)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -2031,7 +2065,7 @@ struct cmpl_base {
#define CMPL_BASE_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
/*
@@ -2116,7 +2150,7 @@ struct tx_cmpl {
#define TX_CMPL_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
@@ -2408,30 +2442,31 @@ struct rx_pkt_cmpl_hi {
* inner packet and that the ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the t_ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the t_l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
+ (UINT32_C(0x0) << 4)
/*
* The metadata field contains the VLAN tag and TPID value.
* - metadata[11:0] contains the vlan VID value.
@@ -2439,16 +2474,70 @@ struct rx_pkt_cmpl_hi {
* - metadata[15:13] contains the vlan PRI value.
* - metadata[31:16] contains the vlan TPID value.
*/
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
+ (UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
* This value is only valid if itype indicates a packet
* with an IP header.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2511,8 +2600,14 @@ struct rx_pkt_cmpl_hi {
*/
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
(UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
+ RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This indicates that there was an error in the IP header
* checksum.
@@ -2553,7 +2648,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 9)
@@ -2611,7 +2706,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 12)
@@ -2854,28 +2949,33 @@ struct rx_tpa_start_cmpl_hi {
* inner packet and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
+ UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the sum passed
* for all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
+ UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
+ UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the sum passed for
* all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
+ UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
+ UINT32_C(0xf0)
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
(UINT32_C(0x0) << 4)
@@ -2888,13 +2988,71 @@ struct rx_tpa_start_cmpl_hi {
*/
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
(UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
+ UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
+ UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
+ UINT32_C(0xc00)
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set. For TPA Start completions,
+ * the complete checksum is calculated for the first packet in the
+ * aggregation only.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2911,13 +3069,41 @@ struct rx_tpa_start_cmpl_hi {
/* When meta_format=1, this value is the VLAN TPID. */
#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
- uint16_t v2;
+ uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define RX_TPA_START_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for the packet that was found after part of the
+ * packet was already placed. The packet should be treated as
+ * invalid.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This field identifies the CFA action rule that was used for this
* packet.
@@ -3034,11 +3220,11 @@ struct rx_tpa_end_cmpl {
/*
* This value indicates what the inner packet determined for the
* packet was.
- * - 2 TCP Packet
- * Indicates that the packet was IP and TCP. This indicates
- * that the ip_cs field is valid and that the tcp_udp_cs
- * field is valid and contains the TCP checksum.
- * This also indicates that the payload_offset field is valid.
+ * - 2 TCP Packet
+ * Indicates that the packet was IP and TCP. This indicates
+ * that the ip_cs field is valid and that the tcp_udp_cs
+ * field is valid and contains the TCP checksum.
+ * This also indicates that the payload_offset field is valid.
*/
#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
@@ -3117,13 +3303,28 @@ struct rx_tpa_end_cmpl_hi {
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
- uint32_t tpa_dup_acks;
+ uint16_t tpa_dup_acks;
/*
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+ /*
+ * This value indicated the offset in bytes from the beginning of
+ * the packet where the inner payload starts. This value is valid
+ * for TCP, UDP, FCoE and RoCE packets
+ */
+ uint8_t payload_offset;
+ /*
+ * The value is the total number of aggregation buffers that were
+ * used in the TPA operation. All TPA aggregation buffer completions
+ * preceed the TPA End completion. If the value is zero, then the
+ * aggregation is completely contained in the buffer space provided
+ * in the aggregation start completion.
+ * Note that the field is simply provided as a cross check.
+ */
+ uint8_t tpa_agg_bufs;
/*
* This value is the valid when TPA completion is active. It
* indicates the length of the longest segment of the TPA operation
@@ -3154,6 +3355,9 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
/*
* This error occurs when there is a fatal HW problem in
* the chip only. It indicates that there were not
@@ -3162,6 +3366,12 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
(UINT32_C(0x2) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
/*
* This error occurs when TPA block was not configured to
* reserve adequate BDs for TPA operations on this RX
@@ -3174,8 +3384,14 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
(UINT32_C(0x4) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
+ RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/* unused5 is 16 b */
uint16_t unused_4;
/*
@@ -3239,15 +3455,23 @@ struct eject_cmpl {
* records. Odd values indicate 32B
* records.
*/
- #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
- #define EJECT_CMPL_TYPE_SFT 0
+ #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define EJECT_CMPL_TYPE_SFT 0
/*
* Statistics Ejection Completion:
* Completion of statistics data ejection buffer.
* Length = 16B
*/
- #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
- #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
+ #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
+ #define EJECT_CMPL_FLAGS_SFT 6
+ /*
+ * When this bit is '1', it indicates a packet that has an
+ * error of some type. Type of error is indicated in
+ * error_flags.
+ */
+ #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
/*
* This is the length of the statistics data stored in this
* buffer.
@@ -3258,13 +3482,47 @@ struct eject_cmpl {
* buffer corresponds to.
*/
uint32_t opaque;
- uint32_t v;
+ uint16_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
+ #define EJECT_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for statistics ejection. The statistics ejection should
+ * be treated as invalid
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Did Not Fit:
+ * Statistics did not fit into aggregation buffer provided.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
+ (UINT32_C(0x1) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+ /* reserved16 is 16 b */
+ uint16_t reserved16;
/* unused3 is 32 b */
uint32_t unused_2;
} __attribute__((packed));
@@ -3470,6 +3728,24 @@ struct hwrm_async_event_cmpl {
/* Default VNIC Configuration Change */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
UINT32_C(0x35)
+ /* HW flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ /*
+ * A debug notification being posted to the driver. These
+ * notifications are purely for diagnostic purpose and should not be
+ * used for functional purpose. The driver is not supposed to act
+ * on these messages except to log/record it.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
+ UINT32_C(0x37)
+ /*
+ * A trace log message. This contains firmware trace logs string
+ * embedded in the asynchronous message. This is an experimental
+ * event, not meant for production use at this time.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
/* HWRM Error */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
UINT32_C(0xff)
@@ -4111,9 +4387,19 @@ struct hwrm_async_event_cmpl_reset_notify {
/* opaque is 7 b */
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
- /* 8-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 8-lsb timestamp (100-msec resolution)
+ * The Minimum time required for the Firmware readiness after sending this
+ * notification to the driver instances.
+ */
uint8_t timestamp_lo;
- /* 16-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 16-lsb timestamp (100-msec resolution)
+ * The Maximum Firmware Reset bail out value in the order of 100
+ * milli seconds. The driver instances will use this value to re-initiate the
+ * registration process again if the core firmware didn’t set the ready
+ * state bit.
+ */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
@@ -4829,6 +5115,73 @@ struct hwrm_async_event_cmpl_default_vnic_change {
10
} __attribute__((packed));
+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_flow_aged {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of a hw flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates flow ID this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
+ UINT32_C(0x7fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
+ 0
+ /* Indicates flow direction this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x80000000)
+ /*
+ * If this bit set to 0, then it indicates that the aged
+ * event was rx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 31)
+ /*
+ * If this bit is set to 1, then it indicates that the aged
+ * event was tx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
struct hwrm_async_event_cmpl_hwrm_error {
uint16_t type;
@@ -5682,7 +6035,7 @@ struct hwrm_func_qcaps_output {
/*
* If the query is for a VF, then this flag shall be ignored,
* If this query is for a PF and this flag is set to 1,
- * then the PF has the capability to administer another PF.
+ * then the PF has the administrative privilege to configure another PF
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
UINT32_C(0x40000)
@@ -5700,6 +6053,19 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
UINT32_C(0x100000)
+ /*
+ * If 1, then FW has capability to allocate TX rings dynamically
+ * in ring alloc even if PF reserved pool is zero.
+ * This bit will be used only for PFs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x200000)
+ /*
+ * When this bit is '1', it indicates that core firmware is
+ * capable of Hot Reset.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
+ UINT32_C(0x400000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5864,7 +6230,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_func_qcfg_output (size:640b/80B) */
+/* hwrm_func_qcfg_output (size:704b/88B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -5951,6 +6317,13 @@ struct hwrm_func_qcfg_output {
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
UINT32_C(0x40)
+ /*
+ * If set to 1, then secure mode is enabled for this function or device.
+ * If set to 0, then secure mode is disabled (or normal mode) for this
+ * function or device.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
+ UINT32_C(0x80)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5995,7 +6368,8 @@ struct hwrm_func_qcfg_output {
uint16_t alloc_vnics;
/*
* The maximum transmission unit of the function.
- * For rings allocated on this function, this default
+ * If the reported mtu value is non-zero then it will used for the
+ * rings allocated on this function. otherwise the default
* value is used if ring MTU is not specified.
*/
uint16_t mtu;
@@ -6222,7 +6596,27 @@ struct hwrm_func_qcfg_output {
* reserved for itself (since the NQs must be contiguous in HW).
*/
uint16_t alloc_msix;
- uint8_t unused_2[5];
+ /*
+ * The number of registered VF’s associated with the PF. This field
+ * should be ignored when the request received on the VF interface.
+ * This field will be updated on the PF interface to initiate
+ * the unregister request on PF in the HOT Reset Process.
+ */
+ uint16_t registered_vfs;
+ uint8_t unused_1[3];
+ /*
+ * For backward compatibility this field must be set to 1.
+ * Older drivers might look for this field to be 1 before
+ * processing the message.
+ */
+ uint8_t always_1;
+ /*
+ * This GRC address location is used by the Host driver interfaces to poll
+ * the adapter ready state to re-initiate the registration process again
+ * after receiving the RESET Notify event.
+ */
+ uint32_t reset_addr_poll;
+ uint8_t unused_2[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -6424,6 +6818,13 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
+ /*
+ * When this bit it set, even if PF reserved pool size is zero,
+ * FW will allow driver to create TX rings in ring alloc,
+ * by reserving TX ring, S3 node dynamically.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x400000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7181,6 +7582,17 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
UINT32_C(0x8)
+ /*
+ * When this bit is '1', the function is indicating support of
+ * Hot Reset. The driver interface will destroy the resources,
+ * unregister the function and register again up on receiving
+ * the RESET_NOTIFY Async notification from the core firmware.
+ * The core firmware will this use flag and trigger the Hot Reset
+ * process only if all the registered driver instances are capable
+ * of this support.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
+ UINT32_C(0x10)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10774,6 +11186,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
@@ -10878,6 +11292,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
@@ -10930,6 +11346,9 @@ struct hwrm_port_phy_cfg_input {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* This value controls the wirespeed feature. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11159,6 +11578,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
@@ -11238,6 +11659,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
+ UINT32_C(0x4000)
/*
* Current setting of forced link speed.
* When the link speed is not being forced, this
@@ -11267,6 +11691,9 @@ struct hwrm_port_phy_qcfg_output {
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
+ UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11353,6 +11780,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11408,6 +11837,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* Current setting for wirespeed. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11574,8 +12006,20 @@ struct hwrm_port_phy_qcfg_output {
/* 1G_baseCX */
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
UINT32_C(0x1b)
+ /* 100G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
+ UINT32_C(0x1c)
+ /* 100G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
+ UINT32_C(0x1d)
+ /* 100G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
+ UINT32_C(0x1e)
+ /* 100G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
+ UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
+ HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
/* This value represents a media type. */
uint8_t media_type;
/* Unknown */
@@ -21081,6 +21525,15 @@ struct hwrm_cfa_l2_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -21887,6 +22340,15 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22107,6 +22569,12 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22212,6 +22680,12 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22312,6 +22786,12 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22517,8 +22997,14 @@ struct hwrm_cfa_encap_record_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -22872,6 +23358,15 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23381,6 +23876,15 @@ struct hwrm_cfa_em_flow_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23586,13 +24090,13 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_profile_alloc *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23620,266 +24124,1670 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
- */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
/*
- * This bit must be '1' for the src_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
- UINT32_C(0x4)
+ uint16_t reserved1;
/*
- * This bit must be '1' for the dst_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
- UINT32_C(0x8)
- /*
+ uint32_t reserved2;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_meter_profile_free *
+ *******************************/
+
+
+/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_profile_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_meter_profile_cfg *
+ ******************************/
+
+
+/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
+ UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint32_t reserved;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************************
+ * hwrm_cfa_meter_instance_alloc *
+ *********************************/
+
+
+/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
+ UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
+
+
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the src_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x8)
+ /*
* This bit must be '1' for the ovlan_vid field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
- UINT32_C(0x10)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the t_ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the t_ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the ethertype field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the src_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the dst_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the ipaddr_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the ip_protocol field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the src_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the dst_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x10000)
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
+ */
+ uint32_t tunnel_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0;
+ uint16_t unused_1;
+ /*
+ * This value indicates the source MAC address in
+ * the Ethernet header.
+ */
+ uint8_t src_macaddr[6];
+ uint8_t unused_2[2];
/*
- * This bit must be '1' for the ivlan_vid field to be
- * configured.
+ * This value indicates the destination MAC address in
+ * the Ethernet header.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
- UINT32_C(0x20)
+ uint8_t dst_macaddr[6];
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ivlan_vid;
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ivlan_vid;
+ /* This value indicates the ethertype in the Ethernet header. */
+ uint16_t ethertype;
+ /*
+ * This value indicates the type of IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
+ */
+ uint8_t ip_addr_type;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* IPv4 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ UINT32_C(0x4)
+ /* IPv6 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+ UINT32_C(0x6)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ /*
+ * The value of protocol filed in IP header.
+ * Applies to UDP and TCP traffic.
+ * 6 - TCP
+ * 17 - UDP
+ */
+ uint8_t ip_protocol;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+ UINT32_C(0x0)
+ /* TCP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+ UINT32_C(0x6)
+ /* UDP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+ UINT32_C(0x11)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint16_t unused_3;
+ uint32_t unused_4;
+ /*
+ * The value of source IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t src_ipaddr[4];
+ /*
+ * The value of destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t dst_ipaddr[4];
+ /*
+ * The value of source port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t src_port;
+ /*
+ * The value of destination port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t dst_port;
+ /*
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path.
+ */
+ uint16_t dst_id;
+ /*
+ * If set, this value shall represent the L2 context that matches the L2
+ * information of the decap filter.
+ */
+ uint16_t l2_ctxt_ref_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_decap_filter_free *
+ ******************************/
+
+
+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_decap_filter_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_flow_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
+ UINT32_C(0x1)
+ /* num_vlan is 2 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
+ UINT32_C(0x6)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
+ /* no tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
+ (UINT32_C(0x0) << 1)
+ /* 1 tag */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
+ (UINT32_C(0x1) << 1)
+ /* 2 tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
+ (UINT32_C(0x2) << 1)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
+ /* Enumeration denoting the Flow Type. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
+ UINT32_C(0x38)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
+ /* L2 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
+ (UINT32_C(0x0) << 3)
+ /* IPV4 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
+ (UINT32_C(0x1) << 3)
+ /* IPV6 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
+ (UINT32_C(0x2) << 3)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
/*
- * This bit must be '1' for the t_ovlan_vid field to be
- * configured.
+ * when set to 1, indicates TX flow offload for function specified in src_fid and
+ * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
+ * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
+ * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
+ * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
+ * belong to the children VFs of the same PF to indicate VM to VM flow.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
UINT32_C(0x40)
/*
- * This bit must be '1' for the t_ivlan_vid field to be
- * configured.
+ * when set to 1, indicates RX flow offload for function specified in dst_fid and
+ * the src_fid should be set to invalid value.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x80)
/*
- * This bit must be '1' for the ethertype field to be
- * configured.
+ * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
+ * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
+ * This flag is only valid when the flow direction is RX.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
/*
- * This bit must be '1' for the src_ipaddr field to be
- * configured.
+ * Tx Flow: vf fid.
+ * Rx Flow: pf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ uint16_t src_fid;
+ /* Tunnel handle valid when tunnel flag is set. */
+ uint32_t tunnel_handle;
+ uint16_t action_flags;
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* recycle is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* meter is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /* nat_src is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
+ UINT32_C(0x20)
+ /* nat_dest is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
+ UINT32_C(0x40)
+ /* nat_ipv4_address is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
+ UINT32_C(0x80)
+ /* l2_header_rewrite is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
+ UINT32_C(0x100)
+ /* ttl_decrement is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
UINT32_C(0x200)
/*
- * This bit must be '1' for the dst_ipaddr field to be
- * configured.
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header. The type of tunnel
+ * is specified in the tunnel_type field.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
UINT32_C(0x400)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x800)
/*
- * This bit must be '1' for the ipaddr_type field to be
- * configured.
+ * Tx Flow: pf or vf fid.
+ * Rx Flow: vf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
- UINT32_C(0x800)
+ uint16_t dst_fid;
+ /* VLAN tpid, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tci;
+ /* Meter id, valid when meter flag is set. */
+ uint16_t act_meter_id;
+ /* Flow with the same l2 context tcam key. */
+ uint16_t ref_flow_handle;
+ /* This value sets the match value for the ethertype. */
+ uint16_t ethertype;
+ /* valid when num tags is 1 or 2. */
+ uint16_t outer_vlan_tci;
+ /* This value sets the match value for the Destination MAC address. */
+ uint16_t dmac[3];
+ /* valid when num tags is 2. */
+ uint16_t inner_vlan_tci;
+ /* This value sets the match value for the Source MAC address. */
+ uint16_t smac[3];
+ /* The bit length of destination IP address mask. */
+ uint8_t ip_dst_mask_len;
+ /* The bit length of source IP address mask. */
+ uint8_t ip_src_mask_len;
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
/*
- * This bit must be '1' for the ip_protocol field to be
- * configured.
+ * The value of source port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
- UINT32_C(0x1000)
+ uint16_t l4_src_port;
/*
- * This bit must be '1' for the src_port field to be
- * configured.
+ * The value of source port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
- UINT32_C(0x2000)
+ uint16_t l4_src_port_mask;
/*
- * This bit must be '1' for the dst_port field to be
- * configured.
+ * The value of destination port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
- UINT32_C(0x4000)
+ uint16_t l4_dst_port;
/*
- * This bit must be '1' for the dst_id field to be
- * configured.
+ * The value of destination port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x8000)
+ uint16_t l4_dst_port_mask;
/*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
+ * NAT IPv4/6 address based on address type flag.
+ * 0 values are ignored.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x10000)
+ uint32_t nat_ip_address[4];
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
/*
- * Tunnel identifier.
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
+ * The NAT source/destination port based on direction flag.
+ * Applies to UDP and TCP traffic.
+ * 0 values are ignored.
*/
- uint32_t tunnel_id;
+ uint16_t nat_port;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* The value of ip protocol. */
+ uint8_t ip_proto;
/* Tunnel Type. */
uint8_t tunnel_type;
/* Non-tunnel */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
/* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
UINT32_C(0x3)
/* IP in IP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
/* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
UINT32_C(0x7)
/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
UINT32_C(0x8)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0;
- uint16_t unused_1;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
+struct hwrm_cfa_flow_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[2];
/*
- * This value indicates the source MAC address in
- * the Ethernet header.
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_free *
+ **********************/
+
+
+/* hwrm_cfa_flow_free_input (size:256b/32B) */
+struct hwrm_cfa_flow_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t src_macaddr[6];
- uint8_t unused_2[2];
+ uint16_t cmpl_ring;
/*
- * This value indicates the destination MAC address in
- * the Ethernet header.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t dst_macaddr[6];
+ uint16_t seq_id;
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the Ethernet header.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t ovlan_vid;
+ uint16_t target_id;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the Ethernet header.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t ivlan_vid;
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_free_output (size:256b/32B) */
+struct hwrm_cfa_flow_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* packet is 64 b */
+ uint64_t packet;
+ /* byte is 64 b */
+ uint64_t byte;
+ uint8_t unused_0[7];
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the tunnel Ethernet header.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t t_ovlan_vid;
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_info *
+ **********************/
+
+
+/* hwrm_cfa_flow_info_input (size:256b/32B) */
+struct hwrm_cfa_flow_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the tunnel Ethernet header.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t t_ivlan_vid;
- /* This value indicates the ethertype in the Ethernet header. */
- uint16_t ethertype;
+ uint16_t cmpl_ring;
/*
- * This value indicates the type of IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t ip_addr_type;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* IPv4 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
- UINT32_C(0x4)
- /* IPv6 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
- UINT32_C(0x6)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ uint16_t seq_id;
/*
- * The value of protocol filed in IP header.
- * Applies to UDP and TCP traffic.
- * 6 - TCP
- * 17 - UDP
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint8_t ip_protocol;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
- UINT32_C(0x0)
- /* TCP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
- UINT32_C(0x6)
- /* UDP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
- UINT32_C(0x11)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
- uint16_t unused_3;
- uint32_t unused_4;
+ uint16_t target_id;
/*
- * The value of source IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t src_ipaddr[4];
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ /* Max flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
+ UINT32_C(0xfff)
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
+ /* CNP flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
+ UINT32_C(0x1000)
+ /* RoCEv1 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
+ UINT32_C(0x2000)
+ /* RoCEv2 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
+ UINT32_C(0x4000)
+ /* Direction rx = 1 */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
+ UINT32_C(0x8000)
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_info_output (size:448b/56B) */
+struct hwrm_cfa_flow_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* flags is 8 b */
+ uint8_t flags;
+ /* profile is 8 b */
+ uint8_t profile;
+ /* src_fid is 16 b */
+ uint16_t src_fid;
+ /* dst_fid is 16 b */
+ uint16_t dst_fid;
+ /* l2_ctxt_id is 16 b */
+ uint16_t l2_ctxt_id;
+ /* em_info is 64 b */
+ uint64_t em_info;
+ /* tcam_info is 64 b */
+ uint64_t tcam_info;
+ /* vfp_tcam_info is 64 b */
+ uint64_t vfp_tcam_info;
+ /* ar_id is 16 b */
+ uint16_t ar_id;
+ /* flow_handle is 16 b */
+ uint16_t flow_handle;
+ /* tunnel_handle is 32 b */
+ uint32_t tunnel_handle;
+ /* The flow aging timer for the flow, the unit is 100 milliseconds */
+ uint16_t flow_timer;
+ uint8_t unused_0[5];
/*
- * The value of destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint32_t dst_ipaddr[4];
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_flush *
+ ***********************/
+
+
+/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+struct hwrm_cfa_flow_flush_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * The value of source port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t src_port;
+ uint16_t cmpl_ring;
/*
- * The value of destination port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t dst_port;
+ uint16_t seq_id;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t dst_id;
+ uint16_t target_id;
/*
- * If set, this value shall represent the L2 context that matches the L2
- * information of the decap filter.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t l2_ctxt_ref_id;
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_alloc_output {
+/* hwrm_cfa_flow_flush_output (size:128b/16B) */
+struct hwrm_cfa_flow_flush_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23888,9 +25796,7 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -23901,13 +25807,13 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_decap_filter_free *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_stats *
+ ***********************/
-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_decap_filter_free_input {
+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
+struct hwrm_cfa_flow_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23935,13 +25841,53 @@ struct hwrm_cfa_decap_filter_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[4];
+ /* Flow handle. */
+ uint16_t num_flows;
+ /* Flow handle. */
+ uint16_t flow_handle_0;
+ /* Flow handle. */
+ uint16_t flow_handle_1;
+ /* Flow handle. */
+ uint16_t flow_handle_2;
+ /* Flow handle. */
+ uint16_t flow_handle_3;
+ /* Flow handle. */
+ uint16_t flow_handle_4;
+ /* Flow handle. */
+ uint16_t flow_handle_5;
+ /* Flow handle. */
+ uint16_t flow_handle_6;
+ /* Flow handle. */
+ uint16_t flow_handle_7;
+ /* Flow handle. */
+ uint16_t flow_handle_8;
+ /* Flow handle. */
+ uint16_t flow_handle_9;
+ uint8_t unused_0[2];
+ /* Flow ID of a flow. */
+ uint32_t flow_id_0;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_1;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_2;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_3;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_4;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_5;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_6;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_7;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_8;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_9;
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_free_output {
+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
+struct hwrm_cfa_flow_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23950,6 +25896,46 @@ struct hwrm_cfa_decap_filter_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* packet_0 is 64 b */
+ uint64_t packet_0;
+ /* packet_1 is 64 b */
+ uint64_t packet_1;
+ /* packet_2 is 64 b */
+ uint64_t packet_2;
+ /* packet_3 is 64 b */
+ uint64_t packet_3;
+ /* packet_4 is 64 b */
+ uint64_t packet_4;
+ /* packet_5 is 64 b */
+ uint64_t packet_5;
+ /* packet_6 is 64 b */
+ uint64_t packet_6;
+ /* packet_7 is 64 b */
+ uint64_t packet_7;
+ /* packet_8 is 64 b */
+ uint64_t packet_8;
+ /* packet_9 is 64 b */
+ uint64_t packet_9;
+ /* byte_0 is 64 b */
+ uint64_t byte_0;
+ /* byte_1 is 64 b */
+ uint64_t byte_1;
+ /* byte_2 is 64 b */
+ uint64_t byte_2;
+ /* byte_3 is 64 b */
+ uint64_t byte_3;
+ /* byte_4 is 64 b */
+ uint64_t byte_4;
+ /* byte_5 is 64 b */
+ uint64_t byte_5;
+ /* byte_6 is 64 b */
+ uint64_t byte_6;
+ /* byte_7 is 64 b */
+ uint64_t byte_7;
+ /* byte_8 is 64 b */
+ uint64_t byte_8;
+ /* byte_9 is 64 b */
+ uint64_t byte_9;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -23961,13 +25947,13 @@ struct hwrm_cfa_decap_filter_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_alloc *
- ***********************/
+/***********************************
+ * hwrm_cfa_flow_aging_timer_reset *
+ ***********************************/
-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_flow_alloc_input {
+/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_timer_reset_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23989,219 +25975,21 @@ struct hwrm_cfa_flow_alloc_input {
*/
uint16_t target_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint16_t flags;
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
- UINT32_C(0x1)
- /* num_vlan is 2 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
- UINT32_C(0x6)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
- /* no tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
- (UINT32_C(0x0) << 1)
- /* 1 tag */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
- (UINT32_C(0x1) << 1)
- /* 2 tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
- (UINT32_C(0x2) << 1)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
- /* Enumeration denoting the Flow Type. */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
- UINT32_C(0x38)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
- /* L2 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
- (UINT32_C(0x0) << 3)
- /* IPV4 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
- (UINT32_C(0x1) << 3)
- /* IPV6 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
- (UINT32_C(0x2) << 3)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
- /*
- * when set to 1, indicates TX flow offload for function specified in src_fid and
- * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
- * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
- * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
- * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
- * belong to the children VFs of the same PF to indicate VM to VM flow.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x40)
- /*
- * when set to 1, indicates RX flow offload for function specified in dst_fid and
- * the src_fid should be set to invalid value.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x80)
- /*
- * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
- * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
- * This flag is only valid when the flow direction is RX.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
- UINT32_C(0x100)
- /*
- * Tx Flow: vf fid.
- * Rx Flow: pf fid.
- */
- uint16_t src_fid;
- /* Tunnel handle valid when tunnel flag is set. */
- uint32_t tunnel_handle;
- uint16_t action_flags;
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
- UINT32_C(0x1)
- /* recycle is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
- UINT32_C(0x4)
- /* meter is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
- UINT32_C(0x8)
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
- UINT32_C(0x10)
- /* nat_src is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
- UINT32_C(0x20)
- /* nat_dest is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
- UINT32_C(0x40)
- /* nat_ipv4_address is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
- UINT32_C(0x80)
- /* l2_header_rewrite is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
- UINT32_C(0x100)
- /* ttl_decrement is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
- UINT32_C(0x200)
- /*
- * If set to 1 and flow direction is TX, it indicates decap of L2 header
- * and encap of tunnel header. If set to 1 and flow direction is RX, it
- * indicates decap of tunnel header and encap L2 header. The type of tunnel
- * is specified in the tunnel_type field.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
- UINT32_C(0x400)
- /*
- * Tx Flow: pf or vf fid.
- * Rx Flow: vf fid.
- */
- uint16_t dst_fid;
- /* VLAN tpid, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tpid;
- /* VLAN tci, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tci;
- /* Meter id, valid when meter flag is set. */
- uint16_t act_meter_id;
- /* Flow with the same l2 context tcam key. */
- uint16_t ref_flow_handle;
- /* This value sets the match value for the ethertype. */
- uint16_t ethertype;
- /* valid when num tags is 1 or 2. */
- uint16_t outer_vlan_tci;
- /* This value sets the match value for the Destination MAC address. */
- uint16_t dmac[3];
- /* valid when num tags is 2. */
- uint16_t inner_vlan_tci;
- /* This value sets the match value for the Source MAC address. */
- uint16_t smac[3];
- /* The bit length of destination IP address mask. */
- uint8_t ip_dst_mask_len;
- /* The bit length of source IP address mask. */
- uint8_t ip_src_mask_len;
- /* The value of destination IPv4/IPv6 address. */
- uint32_t ip_dst[4];
- /* The source IPv4/IPv6 address. */
- uint32_t ip_src[4];
- /*
- * The value of source port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port;
- /*
- * The value of source port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port_mask;
- /*
- * The value of destination port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port;
- /*
- * The value of destination port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port_mask;
- /*
- * NAT IPv4/6 address based on address type flag.
- * 0 values are ignored.
- */
- uint32_t nat_ip_address[4];
- /* L2 header re-write Destination MAC address. */
- uint16_t l2_rewrite_dmac[3];
- /*
- * The NAT source/destination port based on direction flag.
- * Applies to UDP and TCP traffic.
- * 0 values are ignored.
- */
- uint16_t nat_port;
- /* L2 header re-write Source MAC address. */
- uint16_t l2_rewrite_smac[3];
- /* The value of ip protocol. */
- uint8_t ip_proto;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
-struct hwrm_cfa_flow_alloc_output {
+/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_timer_reset_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24210,20 +25998,7 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[2];
- /*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
- */
- uint32_t flow_id;
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24234,13 +26009,13 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_flow_free *
- **********************/
+/***************************
+ * hwrm_cfa_flow_aging_cfg *
+ ***************************/
-/* hwrm_cfa_flow_free_input (size:256b/32B) */
-struct hwrm_cfa_flow_free_input {
+/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24268,15 +26043,38 @@ struct hwrm_cfa_flow_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[6];
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
+ /* The bit field to enable per flow aging configuration. */
+ uint16_t enables;
+ /* This bit must be '1' for the tcp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
+ UINT32_C(0x1)
+ /* This bit must be '1' for the tcp finish timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
+ UINT32_C(0x2)
+ /* This bit must be '1' for the udp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
+ UINT32_C(0x4)
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_flow_timer;
+ /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_fin_timer;
+ /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
+ uint32_t udp_flow_timer;
} __attribute__((packed));
-/* hwrm_cfa_flow_free_output (size:256b/32B) */
-struct hwrm_cfa_flow_free_output {
+/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24285,10 +26083,6 @@ struct hwrm_cfa_flow_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet is 64 b */
- uint64_t packet;
- /* byte is 64 b */
- uint64_t byte;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24300,13 +26094,13 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_flush *
- ***********************/
+/****************************
+ * hwrm_cfa_flow_aging_qcfg *
+ ****************************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
-struct hwrm_cfa_flow_flush_input {
+/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24334,12 +26128,21 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- uint8_t unused_0[4];
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_flush_output (size:128b/16B) */
-struct hwrm_cfa_flow_flush_output {
+/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24348,7 +26151,13 @@ struct hwrm_cfa_flow_flush_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_flow_timer;
+ /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_fin_timer;
+ /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t udp_flow_timer;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24359,13 +26168,13 @@ struct hwrm_cfa_flow_flush_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_stats *
- ***********************/
+/*****************************
+ * hwrm_cfa_flow_aging_qcaps *
+ *****************************/
-/* hwrm_cfa_flow_stats_input (size:640b/80B) */
-struct hwrm_cfa_flow_stats_input {
+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24393,53 +26202,21 @@ struct hwrm_cfa_flow_stats_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow handle. */
- uint16_t num_flows;
- /* Flow handle. */
- uint16_t flow_handle_0;
- /* Flow handle. */
- uint16_t flow_handle_1;
- /* Flow handle. */
- uint16_t flow_handle_2;
- /* Flow handle. */
- uint16_t flow_handle_3;
- /* Flow handle. */
- uint16_t flow_handle_4;
- /* Flow handle. */
- uint16_t flow_handle_5;
- /* Flow handle. */
- uint16_t flow_handle_6;
- /* Flow handle. */
- uint16_t flow_handle_7;
- /* Flow handle. */
- uint16_t flow_handle_8;
- /* Flow handle. */
- uint16_t flow_handle_9;
- uint8_t unused_0[2];
- /* Flow ID of a flow. */
- uint32_t flow_id_0;
- /* Flow ID of a flow. */
- uint32_t flow_id_1;
- /* Flow ID of a flow. */
- uint32_t flow_id_2;
- /* Flow ID of a flow. */
- uint32_t flow_id_3;
- /* Flow ID of a flow. */
- uint32_t flow_id_4;
- /* Flow ID of a flow. */
- uint32_t flow_id_5;
- /* Flow ID of a flow. */
- uint32_t flow_id_6;
- /* Flow ID of a flow. */
- uint32_t flow_id_7;
- /* Flow ID of a flow. */
- uint32_t flow_id_8;
- /* Flow ID of a flow. */
- uint32_t flow_id_9;
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
-struct hwrm_cfa_flow_stats_output {
+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_flow_aging_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24448,46 +26225,14 @@ struct hwrm_cfa_flow_stats_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet_0 is 64 b */
- uint64_t packet_0;
- /* packet_1 is 64 b */
- uint64_t packet_1;
- /* packet_2 is 64 b */
- uint64_t packet_2;
- /* packet_3 is 64 b */
- uint64_t packet_3;
- /* packet_4 is 64 b */
- uint64_t packet_4;
- /* packet_5 is 64 b */
- uint64_t packet_5;
- /* packet_6 is 64 b */
- uint64_t packet_6;
- /* packet_7 is 64 b */
- uint64_t packet_7;
- /* packet_8 is 64 b */
- uint64_t packet_8;
- /* packet_9 is 64 b */
- uint64_t packet_9;
- /* byte_0 is 64 b */
- uint64_t byte_0;
- /* byte_1 is 64 b */
- uint64_t byte_1;
- /* byte_2 is 64 b */
- uint64_t byte_2;
- /* byte_3 is 64 b */
- uint64_t byte_3;
- /* byte_4 is 64 b */
- uint64_t byte_4;
- /* byte_5 is 64 b */
- uint64_t byte_5;
- /* byte_6 is 64 b */
- uint64_t byte_6;
- /* byte_7 is 64 b */
- uint64_t byte_7;
- /* byte_8 is 64 b */
- uint64_t byte_8;
- /* byte_9 is 64 b */
- uint64_t byte_9;
+ /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_flow_timer;
+ /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_fin_timer;
+ /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t max_udp_flow_timer;
+ /* The maximum aging flows that HW can support. */
+ uint32_t max_aging_flows;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24706,6 +26451,12 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24765,8 +26516,14 @@ struct hwrm_tunnel_dst_port_query_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0[7];
} __attribute__((packed));
@@ -24857,8 +26614,14 @@ struct hwrm_tunnel_dst_port_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* This field represents the value of L4 destination port used
@@ -24948,8 +26711,14 @@ struct hwrm_tunnel_dst_port_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -25025,6 +26794,52 @@ struct ctx_hw_stats {
uint64_t tpa_aborts;
} __attribute__((packed));
+/* Periodic Engine statistics context DMA to host. */
+/* ctx_eng_stats (size:512b/64B) */
+struct ctx_eng_stats {
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+} __attribute__((packed));
+
/***********************
* hwrm_stat_ctx_alloc *
***********************/
@@ -25081,7 +26896,7 @@ struct hwrm_stat_ctx_alloc_input {
* than offloaded RoCE traffic shall not be included in this
* statistic context.
* When this bit is set to '0', the statistics context shall be
- * used for the network traffic other than offloaded RoCE traffic.
+ * used for network traffic or engine traffic.
*/
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
uint8_t unused_0[3];
@@ -25272,6 +27087,107 @@ struct hwrm_stat_ctx_query_output {
uint8_t valid;
} __attribute__((packed));
+/***************************
+ * hwrm_stat_ctx_eng_query *
+ ***************************/
+
+
+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_eng_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
+struct hwrm_stat_ctx_eng_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***************************
* hwrm_stat_ctx_clr_stats *
***************************/
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH 09/11] net/bnxt: update HWRM version
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (7 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 08/11] net/bnxt: update HWRM API Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 10/11] net/bnxt: HWRM version update Ajit Khaparde
` (5 subsequent siblings)
14 siblings, 0 replies; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
Update HWRM version to 1.10.0.48
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3156 +++++++++++++++++++++---
1 file changed, 2874 insertions(+), 282 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index ea9a7d40e..00a8ff87e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -260,6 +260,7 @@ struct cmd_nums {
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
+ #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
@@ -372,6 +373,8 @@ struct cmd_nums {
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
+ #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
+ #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
@@ -397,6 +400,8 @@ struct cmd_nums {
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
/* Experimental */
+ #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
+ /* Experimental */
#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
@@ -407,6 +412,8 @@ struct cmd_nums {
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
/* Experimental */
+ #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
+ /* Experimental */
#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
/* Experimental */
#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
@@ -451,6 +458,34 @@ struct cmd_nums {
#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
+ /* Experimental */
+ #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
+ /* Experimental */
+ #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
+ /* Experimental */
+ #define HWRM_CFA_EEM_OP UINT32_C(0x123)
+ /* Experimental */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -469,6 +504,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
/* Engine CKV - Generate and encrypt a new AES key. */
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
+ /* Engine CKV - Configure a label index with a label value. */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -523,6 +560,8 @@ struct cmd_nums {
#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
/* Engine - Set the on-die RQE credit update location. */
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
+ /* Engine - Query the engine function configuration. */
+ #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
/* Experimental */
#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
/* Experimental */
@@ -573,6 +612,10 @@ struct cmd_nums {
/* */
#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
/* Experimental */
+ #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
+ /* Experimental */
+ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
+ /* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
#define HWRM_NVM_FLUSH UINT32_C(0xfff0)
@@ -724,8 +767,8 @@ struct hwrm_err_output {
#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
/* hwrm_func_buf_rgtr */
#define HWRM_MAX_REQ_LEN 128
-/* hwrm_selftest_qlist */
-#define HWRM_MAX_RESP_LEN 280
+/* hwrm_cfa_flow_info */
+#define HWRM_MAX_RESP_LEN 704
/* 7 bit indirection table index. */
#define HW_HASH_INDEX_SIZE 0x80
#define HW_HASH_KEY_SIZE 40
@@ -735,8 +778,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 19
-#define HWRM_VERSION_STR "1.10.0.19"
+#define HWRM_VERSION_RSVD 48
+#define HWRM_VERSION_STR "1.10.0.48"
/****************
* hwrm_ver_get *
@@ -993,6 +1036,32 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
UINT32_C(0x200)
+ /*
+ * If set to 1, firmware is capable to support advanced flow counters like,
+ * Meter drop counters and EEM counters.
+ * If set to 0, firmware is not capable to support advanced flow counters.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * If set to 1, the firmware is able to support the use of the CFA
+ * Extended Exact Match(EEM) feature.
+ * If set to 0, firmware is not capable to support the use of the
+ * CFA EEM feature.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
+ UINT32_C(0x800)
+ /*
+ * If set to 1, the firmware is able to support advance CFA flow management
+ * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
+ * If set to 0, then the firmware doesn’t support the advance CFA flow management
+ * features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
+ UINT32_C(0x1000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -3695,6 +3764,9 @@ struct hwrm_async_event_cmpl {
/* Reset notification to clients */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
UINT32_C(0x8)
+ /* Master function selection event */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
/* Function driver unloaded */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
UINT32_C(0x10)
@@ -3739,6 +3811,40 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
UINT32_C(0x37)
+ /*
+ * A EEM flow cached memory flush request event being posted to the PF
+ * driver.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ /*
+ * A EEM flow cache memory flush completion event being posted to the
+ * firmware by the PF driver. This is indication that host EEM flush
+ * has completed by the PF.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ /*
+ * A tcp flag action change event being posted to the PF or trusted VF
+ * driver by the firmware. The PF or trusted VF driver should query
+ * the firmware for the new TCP flag action update after receiving
+ * this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ /*
+ * A eem flow active event being posted to the PF or trusted VF driver
+ * by the firmware. The PF or trusted VF driver should update the
+ * flow's aging timer after receiving this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ /*
+ * A eem cfg change event being posted to the trusted VF driver by the
+ * firmware if the parent PF EEM configuration changed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -4450,6 +4556,75 @@ struct hwrm_async_event_cmpl_reset_notify {
16
} __attribute__((packed));
+/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_recovery {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message can be used for selecting or
+ * deselecting master function for error recovery,
+ * and to communicate to all the functions whether error recovery
+ * was enabled/disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates driver action requested */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
+ 0
+ /*
+ * If set to 1, this function is selected as Master function.
+ * This function has responsibility to do 'chip reset' when it
+ * detects a fatal error. If set to 0, master function functionality
+ * is disabled on this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, error recovery is enabled.
+ * If set to 0, error recovery is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
struct hwrm_async_event_cmpl_func_drvr_unload {
uint16_t type;
@@ -5182,8 +5357,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {
HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
} __attribute__((packed));
-/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
-struct hwrm_async_event_cmpl_hwrm_error {
+/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_req {
uint16_t type;
/*
* This field indicates the exact type of the completion.
@@ -5192,133 +5367,549 @@ struct hwrm_async_event_cmpl_hwrm_error {
* records. Odd values indicate 32B
* records.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
UINT32_C(0x3f)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
+ 0
/* HWRM Asynchronous Event Information */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
UINT32_C(0x2e)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
/* Identifiers of events. */
uint16_t event_id;
- /* HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Notification of a eem_cache_flush request */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
/* Event specific data */
uint32_t event_data2;
- /* Severity of HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
- /* Warning */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
- UINT32_C(0x0)
- /* Non-fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
- UINT32_C(0x1)
- /* Fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
- UINT32_C(0x2)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
+ UINT32_C(0x1)
/* opaque is 7 b */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
/* 8-lsb timestamp from POR (100-msec resolution) */
uint8_t timestamp_lo;
/* 16-lsb timestamp from POR (100-msec resolution) */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
- /* Time stamp for error event */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
- UINT32_C(0x1)
} __attribute__((packed));
-/*******************
- * hwrm_func_reset *
- *******************/
-
-
-/* hwrm_func_reset_input (size:192b/24B) */
-struct hwrm_func_reset_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_done {
+ uint16_t type;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t cmpl_ring;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Notification of a host eem_cache_flush has completed. This event
+ * is generated by the host driver.
*/
- uint16_t seq_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- uint16_t target_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates function ID that this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
+ 0
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_tcp_flag_action_change {
+ uint16_t type;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint64_t resp_addr;
- uint32_t enables;
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of tcp flag action change */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * This bit must be '1' for the vf_id_valid field to be
- * configured.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_flow_active {
+ uint16_t type;
/*
- * The ID of the VF that this PF is trying to reset.
- * Only the parent PF shall be allowed to reset a child VF.
- *
- * A parent PF driver shall use this field only when a specific child VF
- * is requested to be reset.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t vf_id;
- /* This value indicates the level of a function reset. */
- uint8_t func_reset_level;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of an active eem flow */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Indicates the 2nd global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
+ 0
/*
- * Reset the caller function and its children VFs (if any). If no
- * children functions exist, then reset the caller function only.
- */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
- UINT32_C(0x0)
- /* Reset the caller function only */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
- UINT32_C(0x1)
+ * Indicates flow direction of the flow identified by
+ * the global_id_2.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
+ uint8_t opaque_v;
/*
- * Reset all children VFs of the caller function driver if the
- * caller is a PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver with
- * no children VFs.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
- UINT32_C(0x2)
- /*
- * Reset a specific VF of the caller function driver if the caller
- * is the parent PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver that is not
- * the parent of the VF that is being requested to reset.
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the 1st global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
+ 0
+ /*
+ * Indicates flow direction of the flow identified by the
+ * global_id_1.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this is rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this is tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
+ /*
+ * Indicates EEM flow aging mode this event occured on. If
+ * this bit is set to 0, the event_data1 is the EEM global
+ * ID. If this bit is set to 1, the event_data1 is the number
+ * of global ID in the context memory.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
+ UINT32_C(0x80000000)
+ /* EEM flow aging mode 0. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
+ (UINT32_C(0x0) << 31)
+ /* EEM flow aging mode 1. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cfg_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of EEM configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Value of 1 to indicate EEM TX configuration is enabled. Value of
+ * 0 to indicate the EEM TX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
+ * to indicate the EEM RX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
+struct hwrm_async_event_cmpl_fw_trace_msg {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Firmware trace log message */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
+ /* Trace byte 0 to 3 */
+ uint32_t event_data2;
+ /* Trace byte0 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
+ /* Trace byte1 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
+ /* Trace byte2 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
+ /* Trace byte3 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
+ /* Trace flags */
+ uint8_t timestamp_lo;
+ /* Indicates if the string is partial or complete. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
+ UINT32_C(0x1)
+ /* Complete string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
+ UINT32_C(0x0)
+ /* Partial string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
+ UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
+ /* Indicates the firmware that sent the trace message. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
+ UINT32_C(0x2)
+ /* Primary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
+ (UINT32_C(0x0) << 1)
+ /* Secondary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
+ /* Trace byte 4 to 5 */
+ uint16_t timestamp_hi;
+ /* Trace byte4 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
+ /* Trace byte5 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
+ /* Trace byte 6 to 9 */
+ uint32_t event_data1;
+ /* Trace byte6 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
+ /* Trace byte7 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
+ /* Trace byte8 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
+ /* Trace byte9 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
+struct hwrm_async_event_cmpl_hwrm_error {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Severity of HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
+ /* Warning */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
+ UINT32_C(0x0)
+ /* Non-fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
+ UINT32_C(0x1)
+ /* Fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Time stamp for error event */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
+ UINT32_C(0x1)
+} __attribute__((packed));
+
+/*******************
+ * hwrm_func_reset *
+ *******************/
+
+
+/* hwrm_func_reset_input (size:192b/24B) */
+struct hwrm_func_reset_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vf_id_valid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ /*
+ * The ID of the VF that this PF is trying to reset.
+ * Only the parent PF shall be allowed to reset a child VF.
+ *
+ * A parent PF driver shall use this field only when a specific child VF
+ * is requested to be reset.
+ */
+ uint16_t vf_id;
+ /* This value indicates the level of a function reset. */
+ uint8_t func_reset_level;
+ /*
+ * Reset the caller function and its children VFs (if any). If no
+ * children functions exist, then reset the caller function only.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
+ UINT32_C(0x0)
+ /* Reset the caller function only */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
+ UINT32_C(0x1)
+ /*
+ * Reset all children VFs of the caller function driver if the
+ * caller is a PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver with
+ * no children VFs.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
+ UINT32_C(0x2)
+ /*
+ * Reset a specific VF of the caller function driver if the caller
+ * is the parent PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver that is not
+ * the parent of the VF that is being requested to reset.
*/
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
UINT32_C(0x3)
@@ -6066,6 +6657,12 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
UINT32_C(0x400000)
+ /*
+ * This flag will be set to 1 by the FW if FW supports adapter error
+ * recovery.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
+ UINT32_C(0x800000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6813,8 +7410,7 @@ struct hwrm_func_cfg_input {
* resident HWRM clients, only the parent PF driver shall be allowed
* to initiate this change on one of its children VFs. If this bit is
* set to 1, then the VF that is being configured is requested to be
- * trusted. If this bit is set to 0, then the VF that is being configured
- * is requested to be not trusted.
+ * trusted.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
@@ -6825,6 +7421,25 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
UINT32_C(0x400000)
+ /*
+ * This bit requests that the firmware test to see if all the assets
+ * requested in this command (i.e. number of NQ rings) are available.
+ * The firmware will return an error if the requested assets are
+ * not available. The firwmare will NOT reserve the assets if they
+ * are available.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
+ UINT32_C(0x800000)
+ /*
+ * This configuration change can be initiated by a PF driver. This
+ * configuration request shall be targeted to a VF. From local host
+ * resident HWRM clients, only the parent PF driver shall be allowed
+ * to initiate this change on one of its children VFs. If this bit is
+ * set to 1, then the VF that is being configured is requested to be
+ * untrusted.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
+ UINT32_C(0x1000000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7593,6 +8208,19 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
UINT32_C(0x10)
+ /*
+ * When this bit is 1, the function is indicating the support of the
+ * error recovery capability. Error recovery support will be used by
+ * firmware only if all the driver instances support error recovery
+ * process. By setting this bit, driver is indicating support for
+ * corresponding async event completion message. These will be
+ * delivered to the driver even if they did not register for it.
+ * If supported, after receiving reset notify async event with fatal
+ * flag set in event data1, then all the drivers have to tear down
+ * their resources without sending any HWRM commands to FW.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
+ UINT32_C(0x20)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10270,17 +10898,384 @@ struct hwrm_func_backing_store_qcfg_output {
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as 1
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
*/
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/****************************
+ * hwrm_error_recovery_qcfg *
+ ****************************/
+
+
+/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
+struct hwrm_error_recovery_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __attribute__((packed));
+
+/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
+struct hwrm_error_recovery_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When this flag is set to 1, error recovery will be initiated
+ * through master function driver.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
+ /*
+ * When this flag is set to 1, error recovery will be performed
+ * through Co processor.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
+ /*
+ * Driver Polling frequency. This value is in units of 100msec.
+ * Typical value would be 10 to indicate 1sec.
+ * Drivers can poll FW health status, Heartbeat, reset_counter with
+ * this frequency.
+ */
+ uint32_t driver_polling_freq;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 30 to indicate 3sec.
+ * Master function wait period from detecting a fatal error to
+ * initiating reset. In this time period Master PF expects every
+ * active driver will detect fatal error.
+ */
+ uint32_t master_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 50 to indicate 5sec.
+ * Normal function wait period from fatal error detection to
+ * polling FW health status. In this time period, drivers should not
+ * do any PCIe MMIO transaction and should not send any HWRM commands.
+ */
+ uint32_t normal_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 20 to indicate 2sec.
+ * This field indicates that, master function wait period after chip
+ * reset. After this time, master function should reinitialize with
+ * FW.
+ */
+ uint32_t master_func_wait_period_after_reset;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 60 to indicate 6sec.
+ * This field is applicable to both master and normal functions.
+ * Even after chip reset, if FW status not changed to ready,
+ * then all the functions can poll for this much time and bailout.
+ */
+ uint32_t max_bailout_time_after_reset;
+ /*
+ * FW health status register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates upper 30bits of the register address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_health_status_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
+ 2
+ /*
+ * FW HeartBeat register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_heartbeat_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
+ 2
+ /*
+ * FW reset counter.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_reset_cnt_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
+ 2
+ /*
+ * Reset Inprogress Register address for PFs.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_inprogress_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
+ 2
+ /* This field indicates the mask value for reset_inprogress_reg. */
+ uint32_t reset_inprogress_reg_mask;
+ uint8_t unused_0[3];
+ /*
+ * Array of registers and value count to reset the Chip
+ * Each array count has reset_reg, reset_reg_val, delay_after_reset
+ * in TLV format. Depending upon Chip type, number of reset registers
+ * will vary. Drivers have to write reset_reg_val in the reset_reg
+ * location in the same sequence in order to recover from a fatal
+ * error.
+ */
+ uint8_t reg_array_cnt;
+ /*
+ * Reset register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_reg[16];
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
+ /* Value to be written in reset_reg to reset the controller. */
+ uint32_t reset_reg_val[16];
+ /*
+ * This value is in units of 1msec.
+ * Typical value would be 10 to indicate 10msec.
+ * Some of the operations like Core reset require delay before
+ * accessing PCIE MMIO register space.
+ * If this value is non-zero, drivers have to wait for
+ * this much time after writing reset_reg_val in reset_reg.
+ */
+ uint8_t delay_after_reset[16];
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
@@ -10894,6 +11889,12 @@ struct hwrm_func_drv_if_change_output {
*/
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that the firmware got changed / reset.
+ * The driver should do complete re-initialization when that bit is set.
+ */
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
+ UINT32_C(0x2)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -14166,6 +15167,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for autonegotiation on this link.
@@ -14215,6 +15219,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for EEE on this link.
@@ -14281,13 +15288,13 @@ struct hwrm_port_phy_qcaps_output {
#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
} __attribute__((packed));
-/*********************
- * hwrm_port_led_cfg *
- *********************/
+/****************************
+ * hwrm_port_phy_mdio_write *
+ ****************************/
-/* hwrm_port_led_cfg_input (size:512b/64B) */
-struct hwrm_port_led_cfg_input {
+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
+struct hwrm_port_phy_mdio_write_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -14315,46 +15322,198 @@ struct hwrm_port_led_cfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ /*
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
+ */
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1[7];
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_write_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This bit must be '1' for the led0_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
- UINT32_C(0x1)
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_port_phy_mdio_read *
+ ***************************/
+
+
+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
+struct hwrm_port_phy_mdio_read_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This bit must be '1' for the led0_state field to be
- * configured.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
- UINT32_C(0x2)
+ uint16_t cmpl_ring;
/*
- * This bit must be '1' for the led0_color field to be
- * configured.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
- UINT32_C(0x4)
+ uint16_t seq_id;
/*
- * This bit must be '1' for the led0_blink_on field to be
- * configured.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
- UINT32_C(0x8)
+ uint16_t target_id;
/*
- * This bit must be '1' for the led0_blink_off field to be
- * configured.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
- UINT32_C(0x10)
+ uint64_t resp_addr;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
/*
- * This bit must be '1' for the led0_group_id field to be
- * configured.
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
- UINT32_C(0x20)
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1;
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_read_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ uint8_t unused_0[5];
/*
- * This bit must be '1' for the led1_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_led_cfg *
+ *********************/
+
+
+/* hwrm_port_led_cfg_input (size:512b/64B) */
+struct hwrm_port_led_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the led0_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the led0_state field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the led0_color field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the led0_blink_on field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the led0_blink_off field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the led0_group_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the led1_id field to be
+ * configured.
*/
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
UINT32_C(0x40)
@@ -20644,7 +21803,9 @@ struct hwrm_ring_reset_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t unused_0[4];
+ /* Position of consumer index after ring reset completes. */
+ uint8_t consumer_idx[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -21209,6 +22370,26 @@ struct hwrm_ring_grp_free_output {
*/
uint8_t valid;
} __attribute__((packed));
+/*
+ * special reserved flow ID to identify per function default
+ * flows for vSwitch offload
+ */
+#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
+/*
+ * special reserved flow ID to identify per function RoCEv1
+ * flows
+ */
+#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * flows
+ */
+#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * CNP flows
+ */
+#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
/****************************
* hwrm_cfa_l2_filter_alloc *
@@ -22968,6 +24149,13 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Setting of this flag indicates the applicability to the loopback path. */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
+ /*
+ * Setting of this flag indicates this encap record is external encap record.
+ * Resetting of this flag indicates this flag is internal encap record and
+ * this is the default setting.
+ */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
+ UINT32_C(0x2)
/* Encapsulation Type. */
uint8_t encap_type;
/* Virtual eXtensible Local Area Network (VXLAN) */
@@ -23003,8 +24191,11 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -23144,6 +24335,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
UINT32_C(0x4)
+ /*
+ * Setting of this flag indicates that the dest_id field contains function ID.
+ * If this is not set it indicates dest_id is VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x8)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
@@ -23605,7 +24802,13 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
UINT32_C(0x4)
- uint8_t unused_0[4];
+ uint32_t flags;
+ /*
+ * Setting this bit to 1 indicates that dest_id field contains FID.
+ * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x1)
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
@@ -24090,6 +25293,118 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/************************
+ * hwrm_cfa_meter_qcaps *
+ ************************/
+
+
+/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_meter_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
+struct hwrm_cfa_meter_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the clock at which the Meter is running with.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
+ /* 375 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
+ /* 625 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
+ HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
+ uint8_t unused_0[4];
+ /*
+ * The minimum guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_tx_profile;
+ /*
+ * The maximum non-guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_tx_profile;
+ /*
+ * The minimum guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_rx_profile;
+ /*
+ * The maximum non-guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_rx_profile;
+ /*
+ * The minimum guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t min_tx_instance;
+ /*
+ * The maximum non-guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t max_tx_instance;
+ /*
+ * The minimum guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t min_rx_instance;
+ /*
+ * The maximum non-guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t max_rx_instance;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/********************************
* hwrm_cfa_meter_profile_alloc *
********************************/
@@ -24200,11 +25515,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24243,7 +25558,7 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24286,11 +25601,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24564,11 +25879,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24607,7 +25922,7 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24650,11 +25965,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24775,7 +26090,7 @@ struct hwrm_cfa_meter_instance_alloc_input {
/* This value identifies a meter profile in CFA. */
uint16_t meter_profile_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* profile is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
@@ -24798,7 +26113,7 @@ struct hwrm_cfa_meter_instance_alloc_output {
/* This value identifies a meter instance in CFA. */
uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* instance is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
@@ -24816,13 +26131,13 @@ struct hwrm_cfa_meter_instance_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_meter_instance_free *
- ********************************/
+/*******************************
+ * hwrm_cfa_meter_instance_cfg *
+ *******************************/
-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
-struct hwrm_cfa_meter_instance_free_input {
+/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24856,31 +26171,39 @@ struct hwrm_cfa_meter_instance_free_input {
* This enumeration is used for resources that are similar for both
* TX and RX paths of the chip.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
uint8_t unused_0;
- /* This value identifies a meter instance in CFA. */
- uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
+ * This value identifies a new meter profile to be associated with
+ * the meter instance specified in this command.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xffff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[4];
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This value identifies the ID of a meter instance that needs to be updated with
+ * a new meter profile specified in this command.
+ */
+ uint16_t meter_instance_id;
+ uint8_t unused_1[2];
} __attribute__((packed));
-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
-struct hwrm_cfa_meter_instance_free_output {
+/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24900,13 +26223,13 @@ struct hwrm_cfa_meter_instance_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24934,22 +26257,106 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
/*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
UINT32_C(0x2)
/*
* This bit must be '1' for the src_macaddr field to be
@@ -25375,6 +26782,9 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
+ /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
+ UINT32_C(0x200)
/*
* Tx Flow: vf fid.
* Rx Flow: pf fid.
@@ -25430,6 +26840,13 @@ struct hwrm_cfa_flow_alloc_input {
/* If set to 1, flow aging is enabled for this flow. */
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
UINT32_C(0x800)
+ /*
+ * If set to 1 an attempt will be made to try to offload this flow to the
+ * most optimal flow table resource. If set to 0, the flow will be
+ * placed to the default flow table resource.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
+ UINT32_C(0x1000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -25569,7 +26986,8 @@ struct hwrm_cfa_flow_alloc_output {
uint32_t flow_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint32_t flow_counter_id;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25646,6 +27064,229 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_action_data (size:960b/120B) */
+struct hwrm_cfa_flow_action_data {
+ uint16_t action_flags;
+ /* Setting of this flag indicates accept action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* Setting of this flag indicates recycle action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /* Setting of this flag indicates drop action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* Setting of this flag indicates meter action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* Setting of this flag indicates tunnel action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /*
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header.
+ */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
+ UINT32_C(0x20)
+ /* Setting of this flag indicates ttl decrement action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
+ UINT32_C(0x40)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x80)
+ /* Setting of this flag indicates encap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
+ UINT32_C(0x100)
+ /* Setting of this flag indicates decap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
+ UINT32_C(0x200)
+ /* Meter id. */
+ uint16_t act_meter_id;
+ /* VNIC id. */
+ uint16_t vnic_id;
+ /* vport number. */
+ uint16_t vport_id;
+ /* The NAT source/destination. */
+ uint16_t nat_port;
+ uint16_t unused_0[3];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ /* Encapsulation Type. */
+ uint8_t encap_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
+ /* VLAN */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
+ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
+ uint8_t unused[7];
+ /* This value is encap data for the associated encap type. */
+ uint32_t encap_data[20];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
+struct hwrm_cfa_flow_tunnel_hdr_data {
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused[3];
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI).
+ */
+ uint32_t tunnel_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
+struct hwrm_cfa_flow_l4_key_data {
+ /* The value of source port. */
+ uint16_t l4_src_port;
+ /* The value of destination port. */
+ uint16_t l4_dst_port;
+ uint32_t unused;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
+struct hwrm_cfa_flow_l3_key_data {
+ /* The value of ip protocol. */
+ uint8_t ip_protocol;
+ uint8_t unused_0[7];
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ uint32_t unused[2];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
+struct hwrm_cfa_flow_l2_key_data {
+ /* Destination MAC address. */
+ uint16_t dmac[3];
+ uint16_t unused_0;
+ /* Source MAC address. */
+ uint16_t smac[3];
+ uint16_t unused_1;
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
+ uint16_t unused_2;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* Ethertype. */
+ uint16_t ethertype;
+ /* Number of VLAN tags. */
+ uint16_t num_vlan_tags;
+ /* VLAN tpid. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci. */
+ uint16_t l2_rewrite_vlan_tci;
+ uint8_t unused_3[2];
+ /* Outer VLAN TPID. */
+ uint16_t ovlan_tpid;
+ /* Outer VLAN TCI. */
+ uint16_t ovlan_tci;
+ /* Inner VLAN TPID. */
+ uint16_t ivlan_tpid;
+ /* Inner VLAN TCI. */
+ uint16_t ivlan_tci;
+ uint8_t unused[8];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_key_data (size:4160b/520B) */
+struct hwrm_cfa_flow_key_data {
+ /* Flow associated tunnel L2 header key info. */
+ uint32_t t_l2_key_data[14];
+ /* Flow associated tunnel L2 header mask info. */
+ uint32_t t_l2_key_mask[14];
+ /* Flow associated tunnel L3 header key info. */
+ uint32_t t_l3_key_data[16];
+ /* Flow associated tunnel L3 header mask info. */
+ uint32_t t_l3_key_mask[16];
+ /* Flow associated tunnel L4 header key info. */
+ uint32_t t_l4_key_data[2];
+ /* Flow associated tunnel L4 header mask info. */
+ uint32_t t_l4_key_mask[2];
+ /* Flow associated tunnel header info. */
+ uint32_t tunnel_hdr[2];
+ /* Flow associated L2 header key info. */
+ uint32_t l2_key_data[14];
+ /* Flow associated L2 header mask info. */
+ uint32_t l2_key_mask[14];
+ /* Flow associated L3 header key info. */
+ uint32_t l3_key_data[16];
+ /* Flow associated L3 header mask info. */
+ uint32_t l3_key_mask[16];
+ /* Flow associated L4 header key info. */
+ uint32_t l4_key_data[2];
+ /* Flow associated L4 header mask info. */
+ uint32_t l4_key_mask[2];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_info *
**********************/
@@ -25703,7 +27344,7 @@ struct hwrm_cfa_flow_info_input {
uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_info_output (size:448b/56B) */
+/* hwrm_cfa_flow_info_output (size:5632b/704B) */
struct hwrm_cfa_flow_info_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -25713,8 +27354,11 @@ struct hwrm_cfa_flow_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* flags is 8 b */
uint8_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
/* profile is 8 b */
uint8_t profile;
/* src_fid is 16 b */
@@ -25737,7 +27381,12 @@ struct hwrm_cfa_flow_info_output {
uint32_t tunnel_handle;
/* The flow aging timer for the flow, the unit is 100 milliseconds */
uint16_t flow_timer;
- uint8_t unused_0[5];
+ uint8_t unused_0[6];
+ /* Flow associated L2, L3 and L4 headers info. */
+ uint32_t flow_key_data[130];
+ /* Flow associated action record info. */
+ uint32_t flow_action_info[30];
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25753,7 +27402,7 @@ struct hwrm_cfa_flow_info_output {
***********************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+/* hwrm_cfa_flow_flush_input (size:256b/32B) */
struct hwrm_cfa_flow_flush_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -25782,8 +27431,73 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* flags is 32 b */
uint32_t flags;
- uint8_t unused_0[4];
+ /*
+ * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
+ * fields are valid. The flow flush operation should only flush the flows from the
+ * flow table specified. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
+ UINT32_C(0x1)
+ /*
+ * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
+ * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
+ UINT32_C(0x2)
+ /*
+ * This specifies the size of flow handle entries provided by the driver
+ * in the flow table specified below. Only two flow handle size enums are defined.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
+ UINT32_C(0xc0000000)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
+ 30
+ /* The flow handle is 16bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
+ (UINT32_C(0x0) << 30)
+ /* The flow handle is 64bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
+ /* Specify page size of the flow table memory. */
+ uint8_t page_size;
+ /* The page size is 4K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* The page size is 8K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* The page size is 64K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* The page size is 256K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* The page size is 1M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* The page size is 2M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* The page size is 4M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* The page size is 1G */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
+ /* FLow table memory indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
+ /* number of flows in the flow table */
+ uint16_t num_flows;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
} __attribute__((packed));
/* hwrm_cfa_flow_flush_output (size:128b/16B) */
@@ -25983,7 +27697,12 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint8_t unused_0[2];
+ /*
+ * New flow timer value for the flow specified in the ext_flow_handle.
+ * The flow timer unit is 100ms.
+ */
+ uint32_t flow_timer;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -26244,13 +27963,13 @@ struct hwrm_cfa_flow_aging_qcaps_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_pair_info *
- **********************/
+/**********************************
+ * hwrm_cfa_tcp_flag_process_qcfg *
+ **********************************/
-/* hwrm_cfa_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_pair_info_input {
+/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26278,23 +27997,10 @@ struct hwrm_cfa_pair_info_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* If this flag is set, lookup by name else lookup by index. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
- /* If this flag is set, lookup by PF id and VF id. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
- /* Pair table index. */
- uint16_t pair_index;
- /* Pair pf index. */
- uint8_t pair_pfid;
- /* Pair vf index. */
- uint8_t pair_vfid;
- /* Pair name (32 byte string). */
- char pair_name[32];
} __attribute__((packed));
-/* hwrm_cfa_pair_info_output (size:576b/72B) */
-struct hwrm_cfa_pair_info_output {
+/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26303,22 +28009,100 @@ struct hwrm_cfa_pair_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Pair table index. */
- uint16_t next_pair_index;
- /* Pair member a's fid. */
- uint16_t a_fid;
- /* Logical host number. */
- uint8_t host_a_index;
- /* Logical PF number. */
- uint8_t pf_a_index;
- /* Pair member a's Linux logical VF number. */
- uint16_t vf_a_index;
- /* Rx CFA code. */
- uint16_t rx_cfa_code_a;
- /* Tx CFA action. */
- uint16_t tx_cfa_action_a;
- /* Pair member b's fid. */
- uint16_t b_fid;
+ /* The port 0 RX mirror action record ID. */
+ uint16_t rx_ar_id_port0;
+ /* The port 1 RX mirror action record ID. */
+ uint16_t rx_ar_id_port1;
+ /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port0;
+ /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port1;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_pair_info *
+ **********************/
+
+
+/* hwrm_cfa_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_pair_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If this flag is set, lookup by name else lookup by index. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
+ /* If this flag is set, lookup by PF id and VF id. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
+ /* Pair table index. */
+ uint16_t pair_index;
+ /* Pair pf index. */
+ uint8_t pair_pfid;
+ /* Pair vf index. */
+ uint8_t pair_vfid;
+ /* Pair name (32 byte string). */
+ char pair_name[32];
+} __attribute__((packed));
+
+/* hwrm_cfa_pair_info_output (size:576b/72B) */
+struct hwrm_cfa_pair_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pair table index. */
+ uint16_t next_pair_index;
+ /* Pair member a's fid. */
+ uint16_t a_fid;
+ /* Logical host number. */
+ uint8_t host_a_index;
+ /* Logical PF number. */
+ uint8_t pf_a_index;
+ /* Pair member a's Linux logical VF number. */
+ uint16_t vf_a_index;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code_a;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action_a;
+ /* Pair member b's fid. */
+ uint16_t b_fid;
/* Logical host number. */
uint8_t host_b_index;
/* Logical PF number. */
@@ -26364,13 +28148,645 @@ struct hwrm_cfa_pair_info_output {
uint8_t valid;
} __attribute__((packed));
-/***************************************
- * hwrm_cfa_redirect_query_tunnel_type *
- ***************************************/
+/***************************************
+ * hwrm_cfa_redirect_query_tunnel_type *
+ ***************************************/
+
+
+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
+struct hwrm_cfa_redirect_query_tunnel_type_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The source function id. */
+ uint16_t src_fid;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
+struct hwrm_cfa_redirect_query_tunnel_type_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Tunnel Mask. */
+ uint32_t tunnel_mask;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ UINT32_C(0x1)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ UINT32_C(0x2)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ UINT32_C(0x4)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ UINT32_C(0x8)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ UINT32_C(0x10)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ UINT32_C(0x20)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ UINT32_C(0x40)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
+ UINT32_C(0x80)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
+ UINT32_C(0x100)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
+ UINT32_C(0x200)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
+ UINT32_C(0x400)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
+ UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_rgtr *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_rgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
+ uint32_t unused_0;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_rgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_cfa_ctx_mem_unrgtr *
+ ***************************/
+
+
+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_unrgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_unrgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_qctx *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_qctx_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_qctx_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
+ uint8_t unused_0[4];
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**************************
+ * hwrm_cfa_ctx_mem_qcaps *
+ **************************/
+
+
+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Indicates the maximum number of context memory which can be registered. */
+ uint16_t max_entries;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_eem_qcaps *
+ **********************/
+
+
+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_eem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
+ uint32_t supported;
+ /*
+ * If set to 1, then EEM KEY0 table is supported using crc32 hash.
+ * If set to 0 EEM KEY0 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
+ * If set to 0 EEM KEY1 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, then EEM External Record table is supported.
+ * If set to 0 EEM External Record table is not supported.
+ * (This table includes action record, EFC pointers, encap pointers)
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, then EEM External Flow Counters table is supported.
+ * If set to 0 EEM External Flow Counters table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+ UINT32_C(0x8)
+ /*
+ * The maximum number of entries supported by EEM. When configuring the host memory
+ * the number of numbers of entries that can supported are -
+ * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
+ * Any value that are not these values, the FW will round down to the closest support
+ * number of entries.
+ */
+ uint32_t max_entries_supported;
+ /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
+ uint16_t key_entry_size;
+ /* The entry size in bytes of each entry in the RECORD EEM tables. */
+ uint16_t record_entry_size;
+ /* The entry size in bytes of each entry in the EFC EEM tables. */
+ uint16_t efc_entry_size;
+ uint8_t unused_1;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************
+ * hwrm_cfa_eem_cfg *
+ ********************/
+
+
+/* hwrm_cfa_eem_cfg_input (size:320b/40B) */
+struct hwrm_cfa_eem_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+ /*
+ * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
+ * RECORD, EFC all have the same number of entries and all tables will be configured
+ * using this value. Current minimum value is 32k. Current maximum value is 128M.
+ */
+ uint32_t num_entries;
+ uint32_t unused_1;
+ /* Configured EEM with the given context if for KEY0 table. */
+ uint16_t key0_ctx_id;
+ /* Configured EEM with the given context if for KEY1 table. */
+ uint16_t key1_ctx_id;
+ /* Configured EEM with the given context if for RECORD table. */
+ uint16_t record_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t efc_ctx_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
+struct hwrm_cfa_eem_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_cfa_eem_qcfg *
+ *********************/
-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
-struct hwrm_cfa_redirect_query_tunnel_type_input {
+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26398,13 +28814,16 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The source function id. */
- uint16_t src_fid;
- uint8_t unused_0[6];
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
} __attribute__((packed));
-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
-struct hwrm_cfa_redirect_query_tunnel_type_output {
+/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26413,50 +28832,219 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Tunnel Mask. */
- uint32_t tunnel_mask;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
UINT32_C(0x1)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
UINT32_C(0x2)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ /* The number of entries the FW has configured for EEM. */
+ uint32_t num_entries;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************
+ * hwrm_cfa_eem_op *
+ *******************/
+
+
+/* hwrm_cfa_eem_op_input (size:192b/24B) */
+struct hwrm_cfa_eem_op_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the TX flow offload function specified in fid.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the RX flow offload function specified in fid.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint16_t unused_0;
+ /* The number of EEM key table entries to be configured. */
+ uint16_t op;
+ /* This value is reserved and should not be used. */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
+ /*
+ * To properly stop EEM and ensure there are no DMA's, the caller
+ * must disable EEM for the given PF, using this call. This will
+ * safely disable EEM and ensure that all DMA'ed to the
+ * keys/records/efc have been completed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
+ /*
+ * Once the EEM host memory has been configured, EEM options have
+ * been configured. Then the caller should enable EEM for the given
+ * PF. Note once this call has been made, then the EEM mechanism
+ * will be active and DMA's will occur as packets are processed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
+ /*
+ * Clear EEM settings for the given PF so that the register values
+ * are reset back to there initial state.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
+ #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
+ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_op_output (size:128b/16B) */
+struct hwrm_cfa_eem_op_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_adv_flow_mgnt_qcaps *
+ ********************************/
+
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Value of 1 to indicate firmware support 16-bit flow handle.
+ * Value of 0 to indicate firmware not support 16-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate firmware support 64-bit flow handle.
+ * Value of 0 to indicate firmware not support 64-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * Value of 1 to indicate firmware support flow batch delete operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 to indicate that the firmware does not support flow batch delete
+ * operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * Value of 1 to indicate that the firmware support flow reset all operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 indicates firmware does not support flow reset all operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
UINT32_C(0x8)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ /*
+ * Value of 1 to indicate that firmware supports use of FID as dest_id in
+ * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
+ * Value of 0 indicates firmware does not support use of FID as dest_id.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
UINT32_C(0x10)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ /*
+ * Value of 1 to indicate that firmware supports TX EEM flows.
+ * Value of 0 indicates firmware does not support TX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
UINT32_C(0x20)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ /*
+ * Value of 1 to indicate that firmware supports RX EEM flows.
+ * Value of 0 indicates firmware does not support RX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
- UINT32_C(0x80)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
- UINT32_C(0x100)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
- UINT32_C(0x200)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
- UINT32_C(0x400)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
- UINT32_C(0x800)
- /* Use fixed layer 2 ether type of 0xFFFF */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
- UINT32_C(0x1000)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
- UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -26874,7 +29462,11 @@ struct hwrm_stat_ctx_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This is the address for statistic block. */
+ /*
+ * This is the address for statistic block.
+ * > For new versions of the chip, this address should be 128B
+ * > aligned.
+ */
uint64_t stats_dma_addr;
/*
* The statistic block update period in ms.
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH 10/11] net/bnxt: HWRM version update
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (8 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 09/11] net/bnxt: update HWRM version Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-21 21:39 ` [dpdk-dev] [PATCH 11/11] net/bnxt: update release notes for bnxt Ajit Khaparde
` (4 subsequent siblings)
14 siblings, 0 replies; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit, Lance Richardson
Update HWRM API to version 1.10.0.74
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 1399 ++++++++++++++++++++----
1 file changed, 1168 insertions(+), 231 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 00a8ff87e..305ee09bc 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2019 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -27,7 +27,8 @@ struct hwrm_cmd_hdr {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -221,8 +222,14 @@ struct hwrm_short_input {
#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
#define HWRM_SHORT_INPUT_SIGNATURE_LAST \
HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
- /* Reserved for future use. */
- uint16_t unused_0;
+ /* The target ID of the command */
+ uint16_t target_id;
+ /* Default target_id (0x0) to maintain compatibility with old driver */
+ #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
+ /* Reserved for user-space HWRM interface */
+ #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
+ #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
+ HWRM_SHORT_INPUT_TARGET_ID_TOOLS
/* This value indicates the length of the request. */
uint16_t size;
/*
@@ -394,6 +401,8 @@ struct cmd_nums {
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
#define HWRM_OEM_CMD UINT32_C(0xd4)
+ /* Tells the fw to run PRBS test on a given port and lane. */
+ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
@@ -486,6 +495,8 @@ struct cmd_nums {
#define HWRM_CFA_EEM_OP UINT32_C(0x123)
/* Experimental */
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
+ /* Experimental */
+ #define HWRM_CFA_TFLIB UINT32_C(0x125)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -506,6 +517,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
/* Engine CKV - Configure a label index with a label value. */
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
+ /* Engine CKV - Query a label */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -587,6 +600,19 @@ struct cmd_nums {
/* Experimental */
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
/* Experimental */
+ #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
+ /* Returns the current value of a free running counter from the device. */
+ #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
+ /* Experimental */
+ #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
+ /* Experimental */
+ #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
+ /*
+ * Tells the fw to run the DMA read from the host and DMA write
+ * to the host test.
+ */
+ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
+ /* Experimental */
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
/* Experimental */
#define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
@@ -643,67 +669,85 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
/*
* This error code is only reported by firmware when the specific
* request is not able to process when the HOT reset in progress.
*/
- #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
/*
* This error code is only reported by firmware when the registered
* driver instances are not capable of hot reset.
*/
- #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ /*
+ * This error code is only reported by the firmware when during
+ * flow allocation when a requeest for a flow counter fails because
+ * the number of flow counters are exhausted.
+ */
+ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the requested key's hash collides with the installed keys.
+ */
+ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the same key has already been installed.
+ */
+ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
@@ -711,11 +755,11 @@ struct ret_codes {
* by itself, just an indicatation that the response should be parsed
* as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
*/
- #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -774,12 +818,25 @@ struct hwrm_err_output {
#define HW_HASH_KEY_SIZE 40
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
+/* Reserved for BONO processor */
+#define HWRM_TARGET_ID_BONO 0xFFF8
+/* Reserved for KONG processor */
+#define HWRM_TARGET_ID_KONG 0xFFF9
+/* Reserved for APE processor */
+#define HWRM_TARGET_ID_APE 0xFFFA
+/*
+ * This value will be used by tools for User-space HWRM Interface.
+ * When tool execute any HWRM command with this target_id, firmware
+ * will copy the response and/or data payload via register space instead
+ * of DMAing it.
+ */
+#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 48
-#define HWRM_VERSION_STR "1.10.0.48"
+#define HWRM_VERSION_RSVD 74
+#define HWRM_VERSION_STR "1.10.0.74"
/****************
* hwrm_ver_get *
@@ -804,7 +861,8 @@ struct hwrm_ver_get_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -1062,6 +1120,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
UINT32_C(0x1000)
+ /*
+ * If set to 1, the firmware is able to support TFLIB features.
+ * If set to 0, then the firmware doesn’t support TFLIB features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
+ UINT32_C(0x2000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -1099,12 +1164,8 @@ struct hwrm_ver_get_output {
* firmware (ASCII chars with NULL at the end).
*/
char netctrl_fw_name[16];
- /*
- * This field is reserved for future use.
- * The responder should set it to 0.
- * The requester should ignore this field.
- */
- uint8_t reserved2[16];
+ /* This field represents the active board package name. */
+ char active_pkg_name[16];
/*
* This field represents the name of RoCE FW (ASCII chars
* with NULL at the end).
@@ -3845,6 +3906,12 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
UINT32_C(0x3c)
+ /* TFLIB unique default VNIC Configuration Change */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
+ UINT32_C(0x3d)
+ /* TFLIB unique link status changed */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
+ UINT32_C(0x3e)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -5859,7 +5926,8 @@ struct hwrm_func_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -5962,7 +6030,8 @@ struct hwrm_func_getfid_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6038,7 +6107,8 @@ struct hwrm_func_vf_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6110,7 +6180,8 @@ struct hwrm_func_vf_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6183,7 +6254,8 @@ struct hwrm_func_vf_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6446,7 +6518,8 @@ struct hwrm_func_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6663,6 +6736,13 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
UINT32_C(0x800000)
+ /*
+ * If the query is for a VF, then this flag shall be ignored.
+ * If this query is for a PF and this flag is set to 1, then
+ * the PF has the capability to support extended stats.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
+ UINT32_C(0x1000000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6807,7 +6887,8 @@ struct hwrm_func_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7247,7 +7328,8 @@ struct hwrm_func_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7889,7 +7971,8 @@ struct hwrm_func_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8014,7 +8097,8 @@ struct hwrm_func_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8078,7 +8162,8 @@ struct hwrm_func_vf_resc_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8141,7 +8226,8 @@ struct hwrm_func_drv_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8382,7 +8468,8 @@ struct hwrm_func_drv_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8447,7 +8534,8 @@ struct hwrm_func_buf_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8581,7 +8669,8 @@ struct hwrm_func_buf_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8650,7 +8739,8 @@ struct hwrm_func_drv_qver_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8757,7 +8847,8 @@ struct hwrm_func_resource_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8886,7 +8977,8 @@ struct hwrm_func_backing_store_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8973,7 +9065,10 @@ struct hwrm_func_backing_store_qcaps_output {
* the backing store.
*/
uint32_t tqm_max_entries_per_ring;
- /* Maximum number of MR/AV context entries supported for this function. */
+ /*
+ * Maximum number of MR plus AV context entries supported for this
+ * function.
+ */
uint32_t mrav_max_entries;
/* Number of bytes that must be allocated for each context entry. */
uint16_t mrav_entry_size;
@@ -8981,7 +9076,22 @@ struct hwrm_func_backing_store_qcaps_output {
uint16_t tim_entry_size;
/* Maximum number of Timer context entries supported for this function. */
uint32_t tim_max_entries;
- uint8_t unused_0[2];
+ /*
+ * When this field is zero, the 32b `mrav_num_entries` field in the
+ * `backing_store_cfg` and `backing_store_qcfg` commands represents
+ * the total number of MR plus AV entries allowed in the MR/AV backing
+ * store PBL.
+ *
+ * When this field is non-zero, the 32b `mrav_num_entries` field in
+ * the `backing_store_cfg` and `backing_store_qcfg` commands is
+ * logically divided into two 16b fields. Bits `[31:16]` represents
+ * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
+ * Both of these values are represented in a unit granularity
+ * specified by this field. For example, if this field is 16 and
+ * `mrav_num_entries` is `0x02000100`, then the number of MR entries
+ * is 8192 and the number of AV entries is 4096.
+ */
+ uint16_t mrav_num_entries_units;
/*
* The number of entries specified for any TQM ring must be a
* multiple of this value to prevent any resource allocation
@@ -9021,7 +9131,8 @@ struct hwrm_func_backing_store_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -9041,6 +9152,12 @@ struct hwrm_func_backing_store_cfg_input {
*/
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint32_t enables;
/*
* This bit must be '1' for the qp fields to be
@@ -9958,7 +10075,20 @@ struct hwrm_func_backing_store_cfg_input {
* the backing store.
*/
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10036,7 +10166,8 @@ struct hwrm_func_backing_store_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -10068,6 +10199,12 @@ struct hwrm_func_backing_store_qcfg_output {
*/
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint8_t unused_0[4];
/*
* This bit must be '1' for the qp fields to be
@@ -10891,7 +11028,20 @@ struct hwrm_func_backing_store_qcfg_output {
uint32_t tqm_ring6_num_entries;
/* Number of TQM ring 7 entries. */
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10930,7 +11080,8 @@ struct hwrm_error_recovery_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11296,7 +11447,8 @@ struct hwrm_func_vlan_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11386,7 +11538,8 @@ struct hwrm_func_vlan_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11507,7 +11660,8 @@ struct hwrm_func_vf_vnic_ids_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11580,7 +11734,8 @@ struct hwrm_func_vf_bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11704,7 +11859,8 @@ struct hwrm_func_vf_bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11841,7 +11997,8 @@ struct hwrm_func_drv_if_change_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11929,7 +12086,8 @@ struct hwrm_port_phy_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -12520,7 +12678,8 @@ struct hwrm_port_phy_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13389,7 +13548,7 @@ struct hwrm_port_phy_qcfg_output {
*********************/
-/* hwrm_port_mac_cfg_input (size:320b/40B) */
+/* hwrm_port_mac_cfg_input (size:384b/48B) */
struct hwrm_port_mac_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13407,7 +13566,8 @@ struct hwrm_port_mac_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13527,6 +13687,13 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
UINT32_C(0x1000)
+ /*
+ * When this bit is set to '1', and the ptp_tx_ts_capture_enable
+ * bit is set, then the device uses one step Tx timestamping.
+ * This bit is temporary and used for experimental purposes.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
+ UINT32_C(0x2000)
uint32_t enables;
/*
* This bit must be '1' for the ipg field to be
@@ -13576,6 +13743,12 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ppb field to be
+ * configured.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
+ UINT32_C(0x200)
/* Port ID of port that is to be configured. */
uint16_t port_id;
/*
@@ -13763,6 +13936,12 @@ struct hwrm_port_mac_cfg_input {
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
5
uint8_t unused_0[3];
+ /*
+ * This signed field specifies by how much to adjust the frequency
+ * of sync timer updates (measured in parts per billion).
+ */
+ int32_t ptp_freq_adj_ppb;
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_port_mac_cfg_output (size:128b/16B) */
@@ -13842,7 +14021,8 @@ struct hwrm_port_mac_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14131,7 +14311,8 @@ struct hwrm_port_mac_ptp_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14174,6 +14355,12 @@ struct hwrm_port_mac_ptp_qcfg_output {
*/
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', the device supports one-step
+ * Tx timestamping.
+ */
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
+ UINT32_C(0x4)
uint8_t unused_0[3];
/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
uint32_t rx_ts_reg_off_lower;
@@ -14595,7 +14782,8 @@ struct hwrm_port_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14716,7 +14904,7 @@ struct tx_port_stats_ext {
} __attribute__((packed));
/* Port Rx Statistics extended Formats */
-/* rx_port_stats_ext (size:2368b/296B) */
+/* rx_port_stats_ext (size:3648b/456B) */
struct rx_port_stats_ext {
/* Number of times link state changed to down */
uint64_t link_down_events;
@@ -14792,6 +14980,49 @@ struct rx_port_stats_ext {
uint64_t pfc_pri7_rx_duration_us;
/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
uint64_t pfc_pri7_rx_transitions;
+ /* Total number of received bits */
+ uint64_t rx_bits;
+ /* The number of events where the port receive buffer was over 85% full */
+ uint64_t rx_buffer_passed_threshold;
+ /*
+ * The number of symbol errors that wasn't corrected by FEC correction
+ * alogirithm
+ */
+ uint64_t rx_pcs_symbol_err;
+ /* The number of corrected bits on the port according to active FEC */
+ uint64_t rx_corrected_bits;
+ /* Total number of rx discard bytes count on cos queue 0 */
+ uint64_t rx_discard_bytes_cos0;
+ /* Total number of rx discard bytes count on cos queue 1 */
+ uint64_t rx_discard_bytes_cos1;
+ /* Total number of rx discard bytes count on cos queue 2 */
+ uint64_t rx_discard_bytes_cos2;
+ /* Total number of rx discard bytes count on cos queue 3 */
+ uint64_t rx_discard_bytes_cos3;
+ /* Total number of rx discard bytes count on cos queue 4 */
+ uint64_t rx_discard_bytes_cos4;
+ /* Total number of rx discard bytes count on cos queue 5 */
+ uint64_t rx_discard_bytes_cos5;
+ /* Total number of rx discard bytes count on cos queue 6 */
+ uint64_t rx_discard_bytes_cos6;
+ /* Total number of rx discard bytes count on cos queue 7 */
+ uint64_t rx_discard_bytes_cos7;
+ /* Total number of rx discard packets count on cos queue 0 */
+ uint64_t rx_discard_packets_cos0;
+ /* Total number of rx discard packets count on cos queue 1 */
+ uint64_t rx_discard_packets_cos1;
+ /* Total number of rx discard packets count on cos queue 2 */
+ uint64_t rx_discard_packets_cos2;
+ /* Total number of rx discard packets count on cos queue 3 */
+ uint64_t rx_discard_packets_cos3;
+ /* Total number of rx discard packets count on cos queue 4 */
+ uint64_t rx_discard_packets_cos4;
+ /* Total number of rx discard packets count on cos queue 5 */
+ uint64_t rx_discard_packets_cos5;
+ /* Total number of rx discard packets count on cos queue 6 */
+ uint64_t rx_discard_packets_cos6;
+ /* Total number of rx discard packets count on cos queue 7 */
+ uint64_t rx_discard_packets_cos7;
} __attribute__((packed));
/************************
@@ -14817,7 +15048,8 @@ struct hwrm_port_qstats_ext_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14909,7 +15141,8 @@ struct hwrm_port_lpbk_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14986,7 +15219,8 @@ struct hwrm_port_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15057,7 +15291,8 @@ struct hwrm_port_phy_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15311,7 +15546,8 @@ struct hwrm_port_phy_mdio_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15387,7 +15623,8 @@ struct hwrm_port_phy_mdio_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15463,7 +15700,8 @@ struct hwrm_port_led_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15886,7 +16124,8 @@ struct hwrm_port_led_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16191,7 +16430,8 @@ struct hwrm_port_led_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16519,6 +16759,137 @@ struct hwrm_port_led_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/***********************
+ * hwrm_port_prbs_test *
+ ***********************/
+
+
+/* hwrm_port_prbs_test_input (size:384b/48B) */
+struct hwrm_port_prbs_test_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Host address data is to DMA'd to. */
+ uint64_t resp_data_addr;
+ /*
+ * Size of the buffer pointed to by resp_data_addr. The firmware may
+ * use this entire buffer or less than the entire buffer, but never more.
+ */
+ uint16_t data_len;
+ uint16_t unused_0;
+ uint32_t unused_1;
+ /* Port ID of port where PRBS test to be run. */
+ uint16_t port_id;
+ /* Polynomial selection for PRBS test. */
+ uint16_t poly;
+ /* PRBS7 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
+ /* PRBS9 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
+ /* PRBS11 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
+ /* PRBS15 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
+ /* PRBS23 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
+ /* PRBS31 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
+ /* PRBS58 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* Invalid */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
+ HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
+ /*
+ * Configuration bits for PRBS test.
+ * Use enable bit to start/stop test.
+ * Use tx/rx lane map bits to run test on specific lanes,
+ * if set to 0 test will be run on all lanes.
+ */
+ uint16_t prbs_config;
+ /*
+ * Set 0 to stop test currently in progress
+ * Set 1 to start test with configuration provided.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, tx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, rx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
+ UINT32_C(0x4)
+ /* Duration in seconds to run the PRBS test. */
+ uint16_t timeout;
+ /*
+ * If tx_lane_map_valid is set to 1, this field is a bitmap
+ * of tx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t tx_lane_map;
+ /*
+ * If rx_lane_map_valid is set to 1, this field is a bitmap
+ * of rx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t rx_lane_map;
+} __attribute__((packed));
+
+/* hwrm_port_prbs_test_output (size:128b/16B) */
+struct hwrm_port_prbs_test_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -16542,7 +16913,8 @@ struct hwrm_queue_qportcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16994,7 +17366,8 @@ struct hwrm_queue_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17091,7 +17464,8 @@ struct hwrm_queue_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17194,7 +17568,8 @@ struct hwrm_queue_pfcenable_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17283,7 +17658,8 @@ struct hwrm_queue_pfcenable_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17372,7 +17748,8 @@ struct hwrm_queue_pri2cos_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17522,7 +17899,8 @@ struct hwrm_queue_pri2cos_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17698,7 +18076,8 @@ struct hwrm_queue_cos2bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -18740,7 +19119,8 @@ struct hwrm_queue_cos2bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19831,7 +20211,8 @@ struct hwrm_vnic_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19897,7 +20278,8 @@ struct hwrm_vnic_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19957,7 +20339,8 @@ struct hwrm_vnic_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20172,7 +20555,8 @@ struct hwrm_vnic_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20327,7 +20711,8 @@ struct hwrm_vnic_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20419,7 +20804,13 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
UINT32_C(0x80)
- uint8_t unused_1[7];
+ /*
+ * This field advertises the maximum concurrent TPA aggregations
+ * supported by the VNIC on new devices that support TPA v2.
+ * '0' means that TPA v2 is not supported.
+ */
+ uint16_t max_aggs_supported;
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -20453,7 +20844,8 @@ struct hwrm_vnic_tpa_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20529,6 +20921,15 @@ struct hwrm_vnic_tpa_cfg_input {
*/
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
UINT32_C(0x80)
+ /*
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall DMA payload data using GRO rules.
+ * When this bit is '0', the VNIC shall DMA payload data
+ * using the more efficient LRO rules of filling all
+ * aggregation buffers.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
+ UINT32_C(0x100)
uint32_t enables;
/*
* This bit must be '1' for the max_agg_segs field to be
@@ -20545,16 +20946,15 @@ struct hwrm_vnic_tpa_cfg_input {
* configured.
*/
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
- /*
- * This bit must be '1' for the min_agg_len field to be
- * configured.
- */
+ /* deprecated bit. Do not use!!! */
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
/* Logical vnic ID */
uint16_t vnic_id;
/*
* This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31.
+ * be aggregated (unit is Log2). Max value is 31. On new
+ * devices supporting TPA v2, the unit is multiples of 4 and
+ * valid values are > 0 and <= 63.
*/
uint16_t max_agg_segs;
/* 1 segment */
@@ -20571,7 +20971,10 @@ struct hwrm_vnic_tpa_cfg_input {
HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
/*
* This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7
+ * allowed (unit is Log2). Max value is 7. On new devices
+ * supporting TPA v2, this is in unit of 1 and must be > 0
+ * and <= max_aggs_supported in the hwrm_vnic_qcaps response
+ * to enable TPA v2.
*/
uint16_t max_aggs;
/* 1 aggregation */
@@ -20596,7 +20999,9 @@ struct hwrm_vnic_tpa_cfg_input {
uint32_t max_agg_timer;
/*
* This is the minimum amount of payload length required to
- * start an aggregation context.
+ * start an aggregation context. This field is deprecated and
+ * should be set to 0. The minimum length is set by firmware
+ * and can be queried using hwrm_vnic_tpa_qcfg.
*/
uint32_t min_agg_len;
} __attribute__((packed));
@@ -20645,7 +21050,8 @@ struct hwrm_vnic_rss_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20795,7 +21201,8 @@ struct hwrm_vnic_rss_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20937,7 +21344,8 @@ struct hwrm_vnic_plcmodes_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21100,7 +21508,8 @@ struct hwrm_vnic_plcmodes_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21228,7 +21637,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21287,7 +21697,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21347,7 +21758,8 @@ struct hwrm_ring_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21687,7 +22099,8 @@ struct hwrm_ring_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21764,7 +22177,8 @@ struct hwrm_ring_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21839,7 +22253,8 @@ struct hwrm_ring_aggint_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21988,7 +22403,8 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22094,7 +22510,8 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22250,7 +22667,8 @@ struct hwrm_ring_grp_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22334,7 +22752,8 @@ struct hwrm_ring_grp_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22414,7 +22833,8 @@ struct hwrm_cfa_l2_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22476,6 +22896,22 @@ struct hwrm_cfa_l2_filter_alloc_input {
(UINT32_C(0x2) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
+ /*
+ * Setting of this flag indicates that no XDP filter is created with
+ * L2 filter.
+ * 0 - legacy behavior, XDP filter is created with L2 filter
+ * 1 - XDP filter won't be created with L2 filter
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
+ UINT32_C(0x40)
+ /*
+ * Setting this flag to 1 indicate the L2 fields in this command
+ * pertain to source fields. Setting this flag to 0 indicate the
+ * L2 fields in this command pertain to the destination fields
+ * and this is the default/legacy behavior.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
+ UINT32_C(0x80)
uint32_t enables;
/*
* This bit must be '1' for the l2_addr field to be
@@ -22579,13 +23015,31 @@ struct hwrm_cfa_l2_filter_alloc_input {
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
+ UINT32_C(0x20000)
+ /*
+ * This bit must be '1' for the t_num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
+ UINT32_C(0x40000)
/*
* This value sets the match value for the L2 MAC address.
* Destination MAC address for RX path.
* Source MAC address for TX path.
*/
uint8_t l2_addr[6];
- uint8_t unused_0[2];
+ /* This value sets the match value for the number of VLANs. */
+ uint8_t num_vlans;
+ /*
+ * This value sets the match value for the number of VLANs
+ * in the tunnel headers.
+ */
+ uint8_t t_num_vlans;
/*
* This value sets the mask value for the L2 address.
* A value of 0 will mask the corresponding bit from
@@ -22784,13 +23238,45 @@ struct hwrm_cfa_l2_filter_alloc_output {
*/
uint64_t l2_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -22825,7 +23311,8 @@ struct hwrm_cfa_l2_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22887,7 +23374,8 @@ struct hwrm_cfa_l2_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23014,7 +23502,8 @@ struct hwrm_cfa_l2_set_rx_mask_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23213,7 +23702,8 @@ struct hwrm_cfa_vlan_antispoof_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23287,7 +23777,8 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23366,7 +23857,8 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23602,13 +24094,45 @@ struct hwrm_cfa_tunnel_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t tunnel_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -23643,7 +24167,8 @@ struct hwrm_cfa_tunnel_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23702,7 +24227,8 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23813,7 +24339,8 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23919,7 +24446,8 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24134,7 +24662,8 @@ struct hwrm_cfa_encap_record_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24247,7 +24776,8 @@ struct hwrm_cfa_encap_record_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24289,7 +24819,7 @@ struct hwrm_cfa_encap_record_free_output {
********************************/
-/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
+/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
struct hwrm_cfa_ntuple_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -24307,7 +24837,8 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24456,6 +24987,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
UINT32_C(0x40000)
+ /*
+ * This bit must be '1' for the rfs_ring_tbl_idx field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
+ UINT32_C(0x80000)
/*
* This value identifies a set of CFA data structures used for an L2
* context.
@@ -24639,6 +25176,13 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
* the pri_hint.
*/
uint64_t ntuple_filter_id_hint;
+ /*
+ * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
+ * This index is used in lieu of the RSS hash when selecting the
+ * index into the RSS table to determine the rx ring.
+ */
+ uint16_t rfs_ring_tbl_idx;
+ uint8_t unused_0[6];
} __attribute__((packed));
/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
@@ -24654,13 +25198,45 @@ struct hwrm_cfa_ntuple_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24713,7 +25289,8 @@ struct hwrm_cfa_ntuple_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24772,7 +25349,8 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24884,7 +25462,8 @@ struct hwrm_cfa_em_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25216,13 +25795,45 @@ struct hwrm_cfa_em_flow_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t em_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -25257,7 +25868,8 @@ struct hwrm_cfa_em_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25316,7 +25928,8 @@ struct hwrm_cfa_meter_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25428,7 +26041,8 @@ struct hwrm_cfa_meter_profile_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25705,7 +26319,8 @@ struct hwrm_cfa_meter_profile_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25789,7 +26404,8 @@ struct hwrm_cfa_meter_profile_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26059,7 +26675,8 @@ struct hwrm_cfa_meter_instance_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26154,7 +26771,8 @@ struct hwrm_cfa_meter_instance_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26246,7 +26864,8 @@ struct hwrm_cfa_meter_instance_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26330,7 +26949,8 @@ struct hwrm_cfa_decap_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26654,7 +27274,8 @@ struct hwrm_cfa_decap_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26714,7 +27335,8 @@ struct hwrm_cfa_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26847,6 +27469,15 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
UINT32_C(0x1000)
+ /*
+ * If set to 1 there will be no attempt to allocate an on-chip try to
+ * offload this flow. If set to 0, which will keep compatibility with the
+ * older drivers, will cause the FW to attempt to allocate an on-chip flow
+ * counter for the newly created flow. This will keep the existing behavior
+ * with EM flows which always had an associated flow counter.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
+ UINT32_C(0x2000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -26977,13 +27608,45 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t flow_handle;
uint8_t unused_0[2];
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
uint32_t flow_counter_id;
@@ -26998,6 +27661,34 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
+struct hwrm_cfa_flow_alloc_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* No more L2 Context TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
+ /* No more action records */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
+ /* No more flow counters */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
+ /* No more wild-card TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
+ /* Hash collsion in exact match tables */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
+ /* Key is already installed */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
+ /* Flow Context DB is out of resource */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
+ HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_free *
**********************/
@@ -27021,7 +27712,8 @@ struct hwrm_cfa_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27034,7 +27726,9 @@ struct hwrm_cfa_flow_free_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint16_t unused_0;
+ /* Flow counter id to be freed. */
+ uint32_t flow_counter_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -27310,7 +28004,8 @@ struct hwrm_cfa_flow_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27420,7 +28115,8 @@ struct hwrm_cfa_flow_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27448,6 +28144,9 @@ struct hwrm_cfa_flow_flush_input {
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
UINT32_C(0x2)
+ /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
+ UINT32_C(0x8000000)
/*
* This specifies the size of flow handle entries provided by the driver
* in the flow table specified below. Only two flow handle size enums are defined.
@@ -27544,7 +28243,8 @@ struct hwrm_cfa_flow_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27684,7 +28384,8 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27733,7 +28434,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output {
***************************/
-/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -27751,7 +28452,8 @@ struct hwrm_cfa_flow_aging_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27773,16 +28475,40 @@ struct hwrm_cfa_flow_aging_cfg_input {
/* This bit must be '1' for the udp flow timer field to be configured */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
UINT32_C(0x4)
- /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ /* This bit must be '1' for the eem dma interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
+ UINT32_C(0x8)
+ /* This bit must be '1' for the eem notice interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
+ UINT32_C(0x10)
+ /* This bit must be '1' for the eem context memory maximum entries field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
+ UINT32_C(0x20)
+ /* This bit must be '1' for the eem context memory ID field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
+ UINT32_C(0x40)
+ /* This bit must be '1' for the eem context memory type field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
+ UINT32_C(0x80)
uint8_t flags;
/* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ /* Enumeration denoting the enable, disable eem flow aging configuration. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
+ (UINT32_C(0x0) << 1)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
uint8_t unused_0;
/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
uint32_t tcp_flow_timer;
@@ -27790,6 +28516,21 @@ struct hwrm_cfa_flow_aging_cfg_input {
uint32_t tcp_fin_timer;
/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
uint32_t udp_flow_timer;
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ uint16_t eem_ctx_mem_type;
+ /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
+ UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
@@ -27836,7 +28577,8 @@ struct hwrm_cfa_flow_aging_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27860,7 +28602,7 @@ struct hwrm_cfa_flow_aging_qcfg_input {
uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -27876,7 +28618,17 @@ struct hwrm_cfa_flow_aging_qcfg_output {
uint32_t tcp_fin_timer;
/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
uint32_t udp_flow_timer;
- uint8_t unused_0[3];
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ /* The context memory type for eem flow aging. */
+ uint16_t eem_ctx_mem_type;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -27910,7 +28662,8 @@ struct hwrm_cfa_flow_aging_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27986,7 +28739,8 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28051,7 +28805,8 @@ struct hwrm_cfa_pair_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28171,7 +28926,8 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28275,7 +29031,8 @@ struct hwrm_cfa_ctx_mem_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28371,7 +29128,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28434,7 +29192,8 @@ struct hwrm_cfa_ctx_mem_qctx_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28531,7 +29290,8 @@ struct hwrm_cfa_ctx_mem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28582,7 +29342,8 @@ struct hwrm_cfa_eem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28630,13 +29391,31 @@ struct hwrm_cfa_eem_qcaps_output {
* which are to be offloaded.
* Note if this bit is set then the path_rx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
/*
* When set to 1, indicates the configuration will apply to RX flows
* which are to be offloaded.
* Note if this bit is set then the path_tx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /*
+ * When set to 1, indicates the the FW supports the Centralized
+ * Memory Model. The concept designates one entity for the
+ * memory allocation while all others ‘subscribe’ to it.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * When set to 1, indicates the the FW supports the Detached
+ * Centralized Memory Model. The memory is allocated and managed
+ * as a separate entity. All PFs and VFs will be granted direct
+ * or semi-direct access to the allocated memory while none of
+ * which can interfere with the management of the memory.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x8)
uint32_t unused_0;
uint32_t supported;
/*
@@ -28712,7 +29491,8 @@ struct hwrm_cfa_eem_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28741,7 +29521,15 @@ struct hwrm_cfa_eem_cfg_input {
/* When set to 1, all offloaded flows will be sent to EEM. */
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- uint32_t unused_0;
+ /* When set to 1, secondary, 0 means primary. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
+ UINT32_C(0x8)
+ /*
+ * Group_id which used by Firmware to identify memory pools belonging
+ * to certain group.
+ */
+ uint16_t group_id;
+ uint16_t unused_0;
/*
* Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
* RECORD, EFC all have the same number of entries and all tables will be configured
@@ -28803,7 +29591,8 @@ struct hwrm_cfa_eem_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28878,7 +29667,8 @@ struct hwrm_cfa_eem_op_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28974,7 +29764,8 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29045,6 +29836,42 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
+ /*
+ * Value of 1 to indicate that firmware supports the dynamic allocation of an
+ * on-chip flow counter which can be used for EEM flows.
+ * Value of 0 indicates firmware does not support the dynamic allocation of an
+ * on-chip flow counter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
+ * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * Value of 1 to indicate that firmware supports untagged matching
+ * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
+ * indicates firmware does not support untagged matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * Value of 1 to indicate that firmware supports XDP filter. Value
+ * of 0 indicates firmware does not support XDP filter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * Value of 1 to indicate that the firmware support L2 header source
+ * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
+ * Value of 0 indicates firmware does not support L2 header source
+ * fields matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
+ UINT32_C(0x800)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -29056,6 +29883,81 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/******************
+ * hwrm_cfa_tflib *
+ ******************/
+
+
+/* hwrm_cfa_tflib_input (size:1024b/128B) */
+struct hwrm_cfa_tflib_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* unused. */
+ uint8_t unused0[4];
+ /* TFLIB request data. */
+ uint32_t tf_req[26];
+} __attribute__((packed));
+
+/* hwrm_cfa_tflib_output (size:5632b/704B) */
+struct hwrm_cfa_tflib_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* TFLIB response code */
+ uint32_t tf_resp_code;
+ /* TFLIB response data. */
+ uint32_t tf_resp[170];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/******************************
* hwrm_tunnel_dst_port_query *
******************************/
@@ -29079,7 +29981,8 @@ struct hwrm_tunnel_dst_port_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29177,7 +30080,8 @@ struct hwrm_tunnel_dst_port_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29274,7 +30178,8 @@ struct hwrm_tunnel_dst_port_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29451,7 +30356,8 @@ struct hwrm_stat_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29540,7 +30446,8 @@ struct hwrm_stat_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29602,7 +30509,8 @@ struct hwrm_stat_ctx_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29702,7 +30610,8 @@ struct hwrm_stat_ctx_eng_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29803,7 +30712,8 @@ struct hwrm_stat_ctx_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29863,7 +30773,8 @@ struct hwrm_pcie_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29970,7 +30881,8 @@ struct hwrm_exec_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30043,7 +30955,8 @@ struct hwrm_reject_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30116,7 +31029,8 @@ struct hwrm_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30204,7 +31118,8 @@ struct hwrm_fwd_async_event_cmpl_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30273,7 +31188,8 @@ struct hwrm_nvm_raw_write_blk_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30342,7 +31258,8 @@ struct hwrm_nvm_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30412,7 +31329,8 @@ struct hwrm_nvm_raw_dump_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30478,7 +31396,8 @@ struct hwrm_nvm_get_dir_entries_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30540,7 +31459,8 @@ struct hwrm_nvm_get_dir_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30601,7 +31521,8 @@ struct hwrm_nvm_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30722,7 +31643,8 @@ struct hwrm_nvm_modify_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30795,7 +31717,8 @@ struct hwrm_nvm_find_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30897,7 +31820,8 @@ struct hwrm_nvm_erase_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30957,7 +31881,8 @@ struct hwrm_nvm_get_dev_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30991,7 +31916,12 @@ struct hwrm_nvm_get_dev_info_output {
uint32_t reserved_size;
/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
uint32_t available_size;
- uint8_t unused_0[3];
+ /* This field represents the major version of NVM cfg */
+ uint8_t nvm_cfg_ver_maj;
+ /* This field represents the minor version of NVM cfg */
+ uint8_t nvm_cfg_ver_min;
+ /* This field represents the update version of NVM cfg */
+ uint8_t nvm_cfg_ver_upd;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -31025,7 +31955,8 @@ struct hwrm_nvm_mod_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31104,7 +32035,8 @@ struct hwrm_nvm_verify_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31177,7 +32109,8 @@ struct hwrm_nvm_install_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31340,7 +32273,8 @@ struct hwrm_nvm_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31413,7 +32347,8 @@ struct hwrm_nvm_get_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31548,7 +32483,8 @@ struct hwrm_nvm_set_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31678,7 +32614,8 @@ struct hwrm_nvm_validate_option_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH 11/11] net/bnxt: update release notes for bnxt
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (9 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 10/11] net/bnxt: HWRM version update Ajit Khaparde
@ 2019-05-21 21:39 ` Ajit Khaparde
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (3 subsequent siblings)
14 siblings, 0 replies; 75+ messages in thread
From: Ajit Khaparde @ 2019-05-21 21:39 UTC (permalink / raw)
To: dev; +Cc: ferruh.yigit
Update release doc briefly describing updates to bnxt PMD.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/rel_notes/release_19_08.rst | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index b9510f93a..2ff9d4b1c 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -54,6 +54,12 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
+* **Updated the bnxt PMD.**
+
+ Updated the bnxt PMD. The major enhancements include:
+ * Update HWRM version to 1.10.74
+ * Added vector RX/TX
+ * Performance optimizations in non-vector Tx path
Removed Items
-------------
--
2.20.1 (Apple Git-117)
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 00/10] bnxt patchset
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (10 preceding siblings ...)
2019-05-21 21:39 ` [dpdk-dev] [PATCH 11/11] net/bnxt: update release notes for bnxt Ajit Khaparde
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file Lance Richardson
` (10 more replies)
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
` (2 subsequent siblings)
14 siblings, 11 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
This patchset bsae on top of the previous submission adds the following:
1) Support for vector mode TX and RX.
2) HWRM API update (split into multiple patches).
3) Fixes for RSS reta update and query.
It also updates the release notes.
v2:
* Squashed patches 3 and 4 from v1 patchset.
* Added Meson build support for vector mode PMD.
* Dropped two unnecessary code style changes from patch 3.
Ajit Khaparde (5):
net/bnxt: fix RSS reta indirection table update
net/bnxt: update HWRM API
net/bnxt: update HWRM version
net/bnxt: HWRM version update
net/bnxt: update release notes for bnxt
Lance Richardson (5):
net/bnxt: move tx bd checking to header file
net/bnxt: compute and store scattered RX status
net/bnxt: implement vector mode driver
net/bnxt: use reta update mask and translate qid to grp id
net/bnxt: fix reta query op
config/common_base | 1 +
doc/guides/rel_notes/release_19_08.rst | 6 +
drivers/net/bnxt/Makefile | 1 +
drivers/net/bnxt/bnxt_ethdev.c | 198 +-
drivers/net/bnxt/bnxt_hwrm.c | 1 +
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 ++
drivers/net/bnxt/bnxt_txr.c | 15 -
drivers/net/bnxt/bnxt_txr.h | 20 +
drivers/net/bnxt/hsi_struct_def_dpdk.h | 7573 ++++++++++++++++++++----
drivers/net/bnxt/meson.build | 5 +
14 files changed, 7217 insertions(+), 1105 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-27 9:36 ` Ferruh Yigit
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 02/10] net/bnxt: compute and store scattered RX status Lance Richardson
` (9 subsequent siblings)
10 siblings, 1 reply; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
vector-mode and non-vector transmit functions, move these functions
into bnxt_txr.h.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/net/bnxt/bnxt_txr.c | 15 ---------------
drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 9de12e0d0..16598ba63 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
return 0;
}
-static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
-{
- return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
- txq->tx_ring->tx_ring_struct->ring_mask);
-}
-
-static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
-{
- /* Tell compiler to fetch tx indices from memory. */
- rte_compiler_barrier();
-
- return ((txq->tx_ring->tx_ring_struct->ring_size -
- bnxt_tx_bds_in_hw(txq)) - 1);
-}
-
static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
struct bnxt_tx_queue *txq,
uint16_t *coal_pkts,
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index f802d5080..13ca04676 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -37,6 +37,21 @@ struct bnxt_sw_tx_bd {
unsigned short nr_bds;
};
+static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
+{
+ return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
+ txq->tx_ring->tx_ring_struct->ring_mask);
+}
+
+static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
+{
+ /* Tell compiler to fetch tx indices from memory. */
+ rte_compiler_barrier();
+
+ return ((txq->tx_ring->tx_ring_struct->ring_size -
+ bnxt_tx_bds_in_hw(txq)) - 1);
+}
+
void bnxt_free_tx_rings(struct bnxt *bp);
int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file Lance Richardson
@ 2019-05-27 9:36 ` Ferruh Yigit
2019-05-27 15:24 ` Ferruh Yigit
0 siblings, 1 reply; 75+ messages in thread
From: Ferruh Yigit @ 2019-05-27 9:36 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin
On 5/24/2019 3:49 PM, Lance Richardson wrote:
> To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
> vector-mode and non-vector transmit functions, move these functions
> into bnxt_txr.h.
>
> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
> ---
> drivers/net/bnxt/bnxt_txr.c | 15 ---------------
> drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
> 2 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
> index 9de12e0d0..16598ba63 100644
> --- a/drivers/net/bnxt/bnxt_txr.c
> +++ b/drivers/net/bnxt/bnxt_txr.c
> @@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
> return 0;
> }
>
> -static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
> -{
> - return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
> - txq->tx_ring->tx_ring_struct->ring_mask);
> -}
I can't find this function at all, am I doing something wrong?
Can you please confirm if this function is upstreamed at all?
$ git co v19.05
$ git grep bnxt_tx_bds_in_hw
$ echo $?
1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file
2019-05-27 9:36 ` Ferruh Yigit
@ 2019-05-27 15:24 ` Ferruh Yigit
2019-05-27 18:50 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Ferruh Yigit @ 2019-05-27 15:24 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin
On 5/27/2019 10:36 AM, Ferruh Yigit wrote:
> On 5/24/2019 3:49 PM, Lance Richardson wrote:
>> To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
>> vector-mode and non-vector transmit functions, move these functions
>> into bnxt_txr.h.
>>
>> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
>> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
>> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
>> ---
>> drivers/net/bnxt/bnxt_txr.c | 15 ---------------
>> drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
>> 2 files changed, 15 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
>> index 9de12e0d0..16598ba63 100644
>> --- a/drivers/net/bnxt/bnxt_txr.c
>> +++ b/drivers/net/bnxt/bnxt_txr.c
>> @@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
>> return 0;
>> }
>>
>> -static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
>> -{
>> - return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
>> - txq->tx_ring->tx_ring_struct->ring_mask);
>> -}
>
> I can't find this function at all, am I doing something wrong?
> Can you please confirm if this function is upstreamed at all?
>
> $ git co v19.05
> $ git grep bnxt_tx_bds_in_hw
> $ echo $?
> 1
>
Ah, it is coming from "bnxt patchset for Tx performance optimization" patchset,
I will check it first.
(It is good to write dependency information clearly in the cover letter of the
patchset)
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file
2019-05-27 15:24 ` Ferruh Yigit
@ 2019-05-27 18:50 ` Lance Richardson
0 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-27 18:50 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: dev, Ajit Khaparde, Maxime Coquelin
Apologies for the confusion.
Regards,
Lance
On Mon, May 27, 2019 at 11:24 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 5/27/2019 10:36 AM, Ferruh Yigit wrote:
> > On 5/24/2019 3:49 PM, Lance Richardson wrote:
> >> To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
> >> vector-mode and non-vector transmit functions, move these functions
> >> into bnxt_txr.h.
> >>
> >> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
> >> Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> >> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
> >> ---
> >> drivers/net/bnxt/bnxt_txr.c | 15 ---------------
> >> drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
> >> 2 files changed, 15 insertions(+), 15 deletions(-)
> >>
> >> diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
> >> index 9de12e0d0..16598ba63 100644
> >> --- a/drivers/net/bnxt/bnxt_txr.c
> >> +++ b/drivers/net/bnxt/bnxt_txr.c
> >> @@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
> >> return 0;
> >> }
> >>
> >> -static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
> >> -{
> >> - return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
> >> - txq->tx_ring->tx_ring_struct->ring_mask);
> >> -}
> >
> > I can't find this function at all, am I doing something wrong?
> > Can you please confirm if this function is upstreamed at all?
> >
> > $ git co v19.05
> > $ git grep bnxt_tx_bds_in_hw
> > $ echo $?
> > 1
> >
>
> Ah, it is coming from "bnxt patchset for Tx performance optimization" patchset,
> I will check it first.
> (It is good to write dependency information clearly in the cover letter of the
> patchset)
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v2 02/10] net/bnxt: compute and store scattered RX status
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver Lance Richardson
` (8 subsequent siblings)
10 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
In preparation for a bnxt vector-mode driver, compute and store
scattered_rx status for the device when started.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index da0de211d..e0e0b72c6 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -624,6 +624,27 @@ static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
return 0;
}
+/*
+ * Determine whether the current configuration requires support for scattered
+ * receive; return 1 if scattered receive is required and 0 if not.
+ */
+static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
+{
+ uint16_t buf_size;
+ int i;
+
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
+
+ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
+ RTE_PKTMBUF_HEADROOM);
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
+ return 1;
+ }
+ return 0;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -642,6 +663,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
+
bnxt_link_update_op(eth_dev, 1);
if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 01/10] net/bnxt: move tx bd checking to header file Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 02/10] net/bnxt: compute and store scattered RX status Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-28 9:05 ` Ferruh Yigit
2019-05-28 9:08 ` Ferruh Yigit
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 04/10] net/bnxt: fix RSS reta indirection table update Lance Richardson
` (7 subsequent siblings)
10 siblings, 2 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
Introduce vector mode support for the bnxt pmd.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
v2:
* Squashed with v1 patch 4 ("fix double counting VLAN tags").
* Dropped two unnecessary coding style changes from bnxt_txr.h.
config/common_base | 1 +
drivers/net/bnxt/Makefile | 1 +
drivers/net/bnxt/bnxt_ethdev.c | 95 +++++-
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 +++++++++++++++++++++++++++
drivers/net/bnxt/bnxt_txr.h | 5 +
drivers/net/bnxt/meson.build | 5 +
10 files changed, 600 insertions(+), 9 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
diff --git a/config/common_base b/config/common_base
index 6b96e0e80..1bbb7c10b 100644
--- a/config/common_base
+++ b/config/common_base
@@ -212,6 +212,7 @@ CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC=n
# Compile burst-oriented Broadcom BNXT PMD driver
#
CONFIG_RTE_LIBRTE_BNXT_PMD=y
+CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR=n
#
# Compile burst-oriented Chelsio Terminator (CXGBE) PMD
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
index 8be3cb0e4..9e006b5d1 100644
--- a/drivers/net/bnxt/Makefile
+++ b/drivers/net/bnxt/Makefile
@@ -41,6 +41,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_util.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += rte_pmd_bnxt.c
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR) += bnxt_rxtx_vec_sse.c
#
# Export include files
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index e0e0b72c6..52a6b94e0 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -638,13 +638,73 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
RTE_PKTMBUF_HEADROOM);
- if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
- VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
return 1;
}
return 0;
}
+static eth_rx_burst_t
+bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ /*
+ * Vector mode receive can be enabled only if scatter rx is not
+ * in use and rx offloads are limited to VLAN stripping and
+ * CRC stripping.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.rxmode.offloads &
+ ~(DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_KEEP_CRC |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM |
+ DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_VLAN_FILTER))) {
+ PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_recv_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d rx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.rxmode.offloads);
+#endif
+ return bnxt_recv_pkts;
+}
+
+static eth_tx_burst_t
+bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ /*
+ * Vector mode receive can be enabled only if scatter tx is not
+ * in use and tx offloads other than VLAN insertion are not
+ * in use.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.txmode.offloads &
+ ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
+ PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_xmit_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d tx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.txmode.offloads);
+#endif
+ return bnxt_xmit_pkts;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -675,6 +735,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
+ eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
bp->flags |= BNXT_FLAG_INIT_DONE;
return 0;
@@ -1597,6 +1659,8 @@ bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
+ uint32_t new_pkt_size = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS;
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_dev_info dev_info;
uint32_t rc = 0;
@@ -1610,6 +1674,23 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
return -EINVAL;
}
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ /*
+ * If vector-mode tx/rx is active, disallow any MTU change that would
+ * require scattered receive support.
+ */
+ if (eth_dev->data->dev_started &&
+ (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
+ eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
+ (new_pkt_size >
+ eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
+ PMD_DRV_LOG(ERR,
+ "MTU change would require scattered rx support. ");
+ PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
+ return -EINVAL;
+ }
+#endif
+
if (new_mtu > ETHER_MTU) {
bp->flags |= BNXT_FLAG_JUMBO;
bp->eth_dev->data->dev_conf.rxmode.offloads |=
@@ -1620,8 +1701,7 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
bp->flags &= ~BNXT_FLAG_JUMBO;
}
- eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
- new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2;
+ eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
eth_dev->data->mtu = new_mtu;
PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
@@ -2655,9 +2735,10 @@ bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
RTE_PTYPE_UNKNOWN
};
- if (dev->rx_pkt_burst == bnxt_recv_pkts)
- return ptypes;
- return NULL;
+ if (!dev->rx_pkt_burst)
+ return NULL;
+
+ return ptypes;
}
static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index 1446d784f..fd3d0bd73 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -10,7 +10,8 @@
#include <rte_memory.h>
-#define RING_NEXT(ring, idx) (((idx) + 1) & (ring)->ring_mask)
+#define RING_ADV(ring, idx, n) (((idx) + (n)) & (ring)->ring_mask)
+#define RING_NEXT(ring, idx) RING_ADV(ring, idx, 1)
#define DB_IDX_MASK 0xffffff
#define DB_IDX_VALID (0x1 << 26)
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index 17e2909a7..ff219f4b8 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -355,6 +355,11 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
RTE_ETH_QUEUE_STATE_STARTED;
eth_dev->data->rx_queue_state[queue_idx] = queue_state;
rte_spinlock_init(&rxq->lock);
+
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ bnxt_rxq_vec_setup(rxq);
+#endif
+
out:
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h
index e5d6001d3..057a59e2c 100644
--- a/drivers/net/bnxt/bnxt_rxq.h
+++ b/drivers/net/bnxt/bnxt_rxq.h
@@ -22,6 +22,10 @@ struct bnxt_rx_queue {
uint16_t nb_rx_hold; /* num held free RX desc */
uint16_t rx_free_thresh; /* max free RX desc to hold */
uint16_t queue_id; /* RX queue index */
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+ uint16_t rxrearm_nb; /* number of descs to reinit. */
+ uint16_t rxrearm_start; /* next desc index to reinit. */
+#endif
uint16_t reg_idx; /* RX queue register index */
uint16_t port_id; /* Device port identifier */
uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 3815a2199..cf1c7e5cf 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -7,7 +7,7 @@
#define _BNXT_RXR_H_
#define B_RX_DB(db, prod) \
- (*(uint32_t *)db = (DB_KEY_RX | prod))
+ (*(uint32_t *)db = (DB_KEY_RX | (prod)))
#define BNXT_TPA_L4_SIZE(x) \
{ \
@@ -110,4 +110,11 @@ int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
+int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
+#endif
+
#endif
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
new file mode 100644
index 000000000..1c32c986c
--- /dev/null
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright(c) 2019 Broadcom All rights reserved. */
+
+#include <inttypes.h>
+#include <stdbool.h>
+
+#include <rte_bitmap.h>
+#include <rte_byteorder.h>
+#include <rte_malloc.h>
+#include <rte_memory.h>
+#if defined(RTE_ARCH_X86)
+#include <tmmintrin.h>
+#else
+#error "bnxt vector pmd: unsupported target."
+#endif
+
+#include "bnxt.h"
+#include "bnxt_cpr.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxr.h"
+#include "bnxt_rxq.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "bnxt_txq.h"
+#include "bnxt_txr.h"
+
+/*
+ * RX Ring handling
+ */
+
+#define RTE_BNXT_MAX_RX_BURST 32
+#define RTE_BNXT_MAX_TX_BURST 32
+#define RTE_BNXT_RXQ_REARM_THRESH 32
+#define RTE_BNXT_DESCS_PER_LOOP 4
+
+static inline void
+bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
+{
+ struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
+ struct bnxt_sw_rx_bd *rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
+ struct rte_mbuf *mb0, *mb1;
+ int i;
+
+ const __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, 0);
+ const __m128i addrmask = _mm_set_epi64x(UINT64_MAX, 0);
+
+ /* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
+ if (rte_mempool_get_bulk(rxq->mb_pool,
+ (void *)rx_bufs,
+ RTE_BNXT_RXQ_REARM_THRESH) < 0) {
+ rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
+ RTE_BNXT_RXQ_REARM_THRESH;
+
+ return;
+ }
+
+ /* Initialize the mbufs in vector, process 2 mbufs in one loop */
+ for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
+ __m128i buf_addr0, buf_addr1;
+ __m128i rxbd0, rxbd1;
+
+ mb0 = rx_bufs[0].mbuf;
+ mb1 = rx_bufs[1].mbuf;
+
+ /* Load address fields from both mbufs */
+ buf_addr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
+ buf_addr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
+
+ /* Load both rx descriptors (preserving some existing fields) */
+ rxbd0 = _mm_loadu_si128((__m128i *)(rxbds + 0));
+ rxbd1 = _mm_loadu_si128((__m128i *)(rxbds + 1));
+
+ /* Add default offset to buffer address. */
+ buf_addr0 = _mm_add_epi64(buf_addr0, hdr_room);
+ buf_addr1 = _mm_add_epi64(buf_addr1, hdr_room);
+
+ /* Clear all fields except address. */
+ buf_addr0 = _mm_and_si128(buf_addr0, addrmask);
+ buf_addr1 = _mm_and_si128(buf_addr1, addrmask);
+
+ /* Clear address field in descriptor. */
+ rxbd0 = _mm_andnot_si128(addrmask, rxbd0);
+ rxbd1 = _mm_andnot_si128(addrmask, rxbd1);
+
+ /* Set address field in descriptor. */
+ rxbd0 = _mm_add_epi64(rxbd0, buf_addr0);
+ rxbd1 = _mm_add_epi64(rxbd1, buf_addr1);
+
+ /* Store descriptors to memory. */
+ _mm_store_si128((__m128i *)(rxbds++), rxbd0);
+ _mm_store_si128((__m128i *)(rxbds++), rxbd1);
+ }
+
+ rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
+ B_RX_DB(rxr->rx_doorbell, rxq->rxrearm_start - 1);
+ if (rxq->rxrearm_start >= rxq->nb_rx_desc)
+ rxq->rxrearm_start = 0;
+
+ rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
+}
+
+static uint32_t
+bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ uint32_t l3, pkt_type = 0;
+ uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
+ uint32_t flags_type;
+
+ vlan = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ t_ipcs = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
+ ip6 = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
+
+ flags_type = rxcmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
+
+ if (!t_ipcs && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_ipcs && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_ipcs && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ return pkt_type;
+}
+
+uint16_t
+bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_rx_queue *rxq = rx_queue;
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ int nb_rx_pkts = 0;
+ struct rx_pkt_cmpl *rxcmp;
+ bool evt = false;
+ const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
+ const __m128i shuf_msk =
+ _mm_set_epi8(15, 14, 13, 12, /* rss */
+ 0xFF, 0xFF, /* vlan_tci (zeroes) */
+ 3, 2, /* data_len */
+ 0xFF, 0xFF, 3, 2, /* pkt_len */
+ 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
+
+ /* If Rx Q was stopped return */
+ if (rxq->rx_deferred_start)
+ return 0;
+
+ if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
+ bnxt_rxq_rearm(rxq, rxr);
+
+ /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
+ nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
+
+ /* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP */
+ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
+
+ /* Handle RX burst request */
+ while (1) {
+ cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
+
+ rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
+
+ if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
+ break;
+
+ cpr->valid = FLIP_VALID(cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ if (likely(CMP_TYPE(rxcmp) == RX_PKT_CMPL_TYPE_RX_L2)) {
+ struct rx_pkt_cmpl_hi *rxcmp1;
+ uint32_t tmp_raw_cons;
+ uint16_t cp_cons;
+ struct rte_mbuf *mbuf;
+ __m128i mm_rxcmp, pkt_mb;
+
+ tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
+ cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
+ rxcmp1 = (struct rx_pkt_cmpl_hi *)
+ &cpr->cp_desc_ring[cp_cons];
+
+ if (!CMP_VALID(rxcmp1, tmp_raw_cons,
+ cpr->cp_ring_struct))
+ break;
+
+ raw_cons = tmp_raw_cons;
+ cons = rxcmp->opaque;
+
+ mbuf = rxr->rx_buf_ring[cons].mbuf;
+ rte_prefetch0(mbuf);
+ rxr->rx_buf_ring[cons].mbuf = NULL;
+
+ cpr->valid = FLIP_VALID(cp_cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ /* Set constant fields from mbuf initializer. */
+ _mm_store_si128((__m128i *)&mbuf->rearm_data,
+ mbuf_init);
+
+ /* Set mbuf pkt_len, data_len, and rss_hash fields. */
+ mm_rxcmp = _mm_load_si128((__m128i *)rxcmp);
+ pkt_mb = _mm_shuffle_epi8(mm_rxcmp, shuf_msk);
+ _mm_storeu_si128((void *)&mbuf->rx_descriptor_fields1,
+ pkt_mb);
+
+ rte_compiler_barrier();
+
+ if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
+ mbuf->ol_flags |= PKT_RX_RSS_HASH;
+
+ if (rxcmp1->flags2 &
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
+ mbuf->vlan_tci = rxcmp1->metadata &
+ (RX_PKT_CMPL_METADATA_VID_MASK |
+ RX_PKT_CMPL_METADATA_DE |
+ RX_PKT_CMPL_METADATA_PRI_MASK);
+ mbuf->ol_flags |= PKT_RX_VLAN;
+ }
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
+ rx_pkts[nb_rx_pkts++] = mbuf;
+ } else {
+ evt =
+ bnxt_event_hwrm_resp_handler(rxq->bp,
+ (struct cmpl_base *)rxcmp);
+ }
+
+ raw_cons = NEXT_RAW_CMP(raw_cons);
+ if (nb_rx_pkts == nb_pkts || evt)
+ break;
+ }
+ rxr->rx_prod = RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
+
+ rxq->rxrearm_nb += nb_rx_pkts;
+ cpr->cp_raw_cons = raw_cons;
+ if (nb_rx_pkts || evt)
+ B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
+
+ return nb_rx_pkts;
+}
+
+static inline void bnxt_next_cmpl(struct bnxt_cp_ring_info *cpr, uint32_t *idx,
+ bool *v, uint32_t inc)
+{
+ *idx += inc;
+ if (unlikely(*idx == cpr->cp_ring_struct->ring_size)) {
+ *v = !*v;
+ *idx = 0;
+ }
+}
+
+static void
+bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
+{
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ struct rte_mbuf **free = txq->free;
+ uint16_t cons = txr->tx_cons;
+ unsigned int blk = 0;
+
+ while (nr_pkts--) {
+ struct bnxt_sw_tx_bd *tx_buf;
+ struct rte_mbuf *mbuf;
+
+ tx_buf = &txr->tx_buf_ring[cons];
+ cons = RING_NEXT(txr->tx_ring_struct, cons);
+ mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
+ tx_buf->mbuf = NULL;
+
+ if (blk && mbuf->pool != free[0]->pool) {
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+ blk = 0;
+ }
+ free[blk++] = mbuf;
+ }
+ if (blk)
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+
+ txr->tx_cons = cons;
+}
+
+static void
+bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
+{
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ uint32_t nb_tx_pkts = 0;
+ struct tx_cmpl *txcmp;
+ struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
+ struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
+ uint32_t ring_mask = cp_ring_struct->ring_mask;
+
+ do {
+ cons = RING_CMPL(ring_mask, raw_cons);
+ txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
+
+ if (!CMPL_VALID(txcmp, cpr->valid))
+ break;
+ bnxt_next_cmpl(cpr, &cons, &cpr->valid, 1);
+ rte_prefetch0(&cp_desc_ring[cons]);
+
+ if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ nb_tx_pkts += txcmp->opaque;
+ else
+ RTE_LOG_DP(ERR, PMD,
+ "Unhandled CMP type %02x\n",
+ CMP_TYPE(txcmp));
+ raw_cons = cons;
+ } while (nb_tx_pkts < ring_mask);
+
+ if (nb_tx_pkts) {
+ bnxt_tx_cmp_vec(txq, nb_tx_pkts);
+ cpr->cp_raw_cons = raw_cons;
+ B_CP_DB(cpr, raw_cons, ring_mask);
+ }
+}
+
+#define TX_BD_FLAGS_CMPL ((1 << TX_BD_LONG_FLAGS_BD_CNT_SFT) | \
+ TX_BD_SHORT_FLAGS_COAL_NOW | \
+ TX_BD_SHORT_TYPE_TX_BD_SHORT | \
+ TX_BD_LONG_FLAGS_PACKET_END)
+
+#define TX_BD_FLAGS_NOCMPL (TX_BD_FLAGS_CMPL | TX_BD_LONG_FLAGS_NO_CMPL)
+
+static inline uint32_t
+bnxt_xmit_flags_len(uint16_t len, uint16_t flags)
+{
+ switch (len >> 9) {
+ case 0:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT512;
+ case 1:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT1K;
+ case 2:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ case 3:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ default:
+ return flags | TX_BD_LONG_FLAGS_LHINT_GTE2K;
+ }
+}
+
+static uint16_t
+bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_tx_queue *txq = tx_queue;
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ uint16_t prod = txr->tx_prod;
+ struct rte_mbuf *tx_mbuf;
+ struct tx_bd_long *txbd = NULL;
+ struct bnxt_sw_tx_bd *tx_buf;
+ uint16_t to_send;
+
+ nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
+
+ if (unlikely(nb_pkts == 0))
+ return 0;
+
+ /* Handle TX burst request */
+ to_send = nb_pkts;
+ while (to_send) {
+ tx_mbuf = *tx_pkts++;
+ rte_prefetch0(tx_mbuf);
+
+ tx_buf = &txr->tx_buf_ring[prod];
+ tx_buf->mbuf = tx_mbuf;
+ tx_buf->nr_bds = 1;
+
+ txbd = &txr->tx_desc_ring[prod];
+ txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
+ txbd->len = tx_mbuf->data_len;
+ txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
+ TX_BD_FLAGS_NOCMPL);
+ prod = RING_NEXT(txr->tx_ring_struct, prod);
+ to_send--;
+ }
+
+ /* Request a completion for last packet in burst */
+ if (txbd) {
+ txbd->opaque = nb_pkts;
+ txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
+ }
+
+ rte_compiler_barrier();
+ B_TX_DB(txr->tx_doorbell, prod);
+
+ txr->tx_prod = prod;
+
+ return nb_pkts;
+}
+
+uint16_t
+bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ int nb_sent = 0;
+ struct bnxt_tx_queue *txq = tx_queue;
+
+ /* Tx queue was stopped; wait for it to be restarted */
+ if (unlikely(txq->tx_deferred_start)) {
+ PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
+ return 0;
+ }
+
+ /* Handle TX completions */
+ if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
+ bnxt_handle_tx_cp_vec(txq);
+
+ while (nb_pkts) {
+ uint16_t ret, num;
+
+ num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
+ ret = bnxt_xmit_fixed_burst_vec(tx_queue,
+ &tx_pkts[nb_sent],
+ num);
+ nb_sent += ret;
+ nb_pkts -= ret;
+ if (ret < num)
+ break;
+ }
+
+ return nb_sent;
+}
+
+int __attribute__((cold))
+bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
+{
+ uintptr_t p;
+ struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
+
+ mb_def.nb_segs = 1;
+ mb_def.data_off = RTE_PKTMBUF_HEADROOM;
+ mb_def.port = rxq->port_id;
+ rte_mbuf_refcnt_set(&mb_def, 1);
+
+ /* prevent compiler reordering: rearm_data covers previous fields */
+ rte_compiler_barrier();
+ p = (uintptr_t)&mb_def.rearm_data;
+ rxq->mbuf_initializer = *(uint64_t *)p;
+ rxq->rxrearm_nb = 0;
+ rxq->rxrearm_start = 0;
+ return 0;
+}
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index 13ca04676..5d6a531a6 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -57,6 +57,11 @@ int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+#ifdef RTE_LIBRTE_BNXT_INC_VECTOR
+uint16_t bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
+#endif
+
int bnxt_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
int bnxt_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index e130f2712..0d2e24848 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -18,3 +18,8 @@ sources = files('bnxt_cpr.c',
'bnxt_util.c',
'bnxt_vnic.c',
'rte_pmd_bnxt.c')
+
+if arch_subdir == 'x86'
+ dpdk_conf.set('RTE_LIBRTE_BNXT_INC_VECTOR', 1)
+ sources += files('bnxt_rxtx_vec_sse.c')
+endif
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver Lance Richardson
@ 2019-05-28 9:05 ` Ferruh Yigit
2019-05-28 9:08 ` Ferruh Yigit
1 sibling, 0 replies; 75+ messages in thread
From: Ferruh Yigit @ 2019-05-28 9:05 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin
On 5/24/2019 3:49 PM, Lance Richardson wrote:
> Introduce vector mode support for the bnxt pmd.
>
> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> ---
> v2:
> * Squashed with v1 patch 4 ("fix double counting VLAN tags").
> * Dropped two unnecessary coding style changes from bnxt_txr.h.
>
> config/common_base | 1 +
> drivers/net/bnxt/Makefile | 1 +
> drivers/net/bnxt/bnxt_ethdev.c | 95 +++++-
> drivers/net/bnxt/bnxt_ring.h | 3 +-
> drivers/net/bnxt/bnxt_rxq.c | 5 +
> drivers/net/bnxt/bnxt_rxq.h | 4 +
> drivers/net/bnxt/bnxt_rxr.h | 9 +-
> drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 +++++++++++++++++++++++++++
> drivers/net/bnxt/bnxt_txr.h | 5 +
> drivers/net/bnxt/meson.build | 5 +
> 10 files changed, 600 insertions(+), 9 deletions(-)
> create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
>
> diff --git a/config/common_base b/config/common_base
> index 6b96e0e80..1bbb7c10b 100644
> --- a/config/common_base
> +++ b/config/common_base
> @@ -212,6 +212,7 @@ CONFIG_RTE_LIBRTE_BNX2X_DEBUG_PERIODIC=n
> # Compile burst-oriented Broadcom BNXT PMD driver
> #
> CONFIG_RTE_LIBRTE_BNXT_PMD=y
> +CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR=n
I think this compile flag can be omitted, it should be possible to detect if
vector PMD can be run dynamically. And indeed meson build is doing something
similar. Please check 'ice' driver for sample.
>
> #
> # Compile burst-oriented Chelsio Terminator (CXGBE) PMD
> diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
> index 8be3cb0e4..9e006b5d1 100644
> --- a/drivers/net/bnxt/Makefile
> +++ b/drivers/net/bnxt/Makefile
> @@ -41,6 +41,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
> SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
> SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_util.c
> SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += rte_pmd_bnxt.c
> +SRCS-$(CONFIG_RTE_LIBRTE_BNXT_INC_VECTOR) += bnxt_rxtx_vec_sse.c
You need a x86 protect for this, since DPDK supports multiple arch
<...>
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver Lance Richardson
2019-05-28 9:05 ` Ferruh Yigit
@ 2019-05-28 9:08 ` Ferruh Yigit
2019-05-28 11:23 ` Lance Richardson
1 sibling, 1 reply; 75+ messages in thread
From: Ferruh Yigit @ 2019-05-28 9:08 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin
On 5/24/2019 3:49 PM, Lance Richardson wrote:
> @@ -1597,6 +1659,8 @@
>
> bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
>
> static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
> {
> + uint32_t new_pkt_size = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
> + VLAN_TAG_SIZE * BNXT_NUM_VLANS;
'ETHER_HDR_LEN' & 'ETHER_CRC_LEN' are renamed to
'RTE_ETHER_HDR_LEN' & 'RTE_ETHER_CRC_LEN'
I am mostly fixing these while applying but since there will be a new version,
can you please rebase on top of latest next-net, to be able to catch these.
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver
2019-05-28 9:08 ` Ferruh Yigit
@ 2019-05-28 11:23 ` Lance Richardson
0 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 11:23 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: dev, Ajit Khaparde, Maxime Coquelin
On Tue, May 28, 2019 at 5:08 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 5/24/2019 3:49 PM, Lance Richardson wrote:
> > @@ -1597,6 +1659,8 @@
> >
> > bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id,
> >
> > static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
> > {
> > + uint32_t new_pkt_size = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN +
> > + VLAN_TAG_SIZE * BNXT_NUM_VLANS;
>
> 'ETHER_HDR_LEN' & 'ETHER_CRC_LEN' are renamed to
> 'RTE_ETHER_HDR_LEN' & 'RTE_ETHER_CRC_LEN'
>
> I am mostly fixing these while applying but since there will be a new version,
> can you please rebase on top of latest next-net, to be able to catch these.
Sure. Will rebase on next-net and resend after addressing feedback.
Thanks,
Lance
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v2 04/10] net/bnxt: fix RSS reta indirection table update
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (2 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 03/10] net/bnxt: implement vector mode driver Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 05/10] net/bnxt: use reta update mask and translate qid to grp id Lance Richardson
` (6 subsequent siblings)
10 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
We are trying to update the indirection table for all the VNICs.
We should update the table only for the default vnic0.
This patch fixes the above issue.
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Rahul Gupta <rahul.gupta@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 18 ++++++++++--------
drivers/net/bnxt/bnxt_hwrm.c | 1 +
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 52a6b94e0..2d892cd4f 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -983,8 +983,13 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
- struct bnxt_vnic_info *vnic;
- int i;
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+
+ /* Update the default RSS VNIC */
+ if (!vnic)
+ return -EINVAL;
+ if (!vnic->rss_table)
+ return -EINVAL;
if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
return -EINVAL;
@@ -995,12 +1000,9 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
"(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
return -EINVAL;
}
- /* Update the RSS VNIC(s) */
- for (i = 0; i < bp->max_vnics; i++) {
- vnic = &bp->vnic_info[i];
- memcpy(vnic->rss_table, reta_conf, reta_size);
- bnxt_hwrm_vnic_rss_cfg(bp, vnic);
- }
+
+ memcpy(vnic->rss_table, reta_conf, reta_size);
+ bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index eb5c41ebb..8c4fa556d 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1607,6 +1607,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
req.hash_key_tbl_addr =
rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
+ req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 05/10] net/bnxt: use reta update mask and translate qid to grp id
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (3 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 04/10] net/bnxt: fix RSS reta indirection table update Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 06/10] net/bnxt: fix reta query op Lance Richardson
` (5 subsequent siblings)
10 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
Fix the reta update function to only update table entries that are
selected by the update mask. Translate queue number to firmware
group ID when updating an entry.
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 39 ++++++++++++++++++++++++++++------
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 2d892cd4f..d2b89a217 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -977,6 +977,15 @@ static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
}
+/* Return bnxt_rx_queue pointer corresponding to a given rxq. */
+static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
+{
+ if (qid >= bp->rx_nr_rings)
+ return NULL;
+
+ return bp->eth_dev->data->rx_queues[qid];
+}
+
static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
@@ -984,24 +993,42 @@ static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft;
+ int i;
- /* Update the default RSS VNIC */
- if (!vnic)
- return -EINVAL;
if (!vnic->rss_table)
return -EINVAL;
if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- memcpy(vnic->rss_table, reta_conf, reta_size);
+ for (i = 0; i < reta_size; i++) {
+ struct bnxt_rx_queue *rxq;
+
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (!(reta_conf[idx].mask & (1ULL << sft)))
+ continue;
+
+ rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
+ if (!rxq) {
+ PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
+ return -EINVAL;
+ }
+
+ vnic->rss_table[i] =
+ vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
+ }
+
bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 06/10] net/bnxt: fix reta query op
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (4 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 05/10] net/bnxt: use reta update mask and translate qid to grp id Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 07/10] net/bnxt: update HWRM API Lance Richardson
` (4 subsequent siblings)
10 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
Fix reta query op to only return table entries as identfied by the
provided mask. Translate firmware group IDs to queue numbers.
Removed extraneous code from bnxt_reta_query_op().
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 47 +++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 15 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index d2b89a217..70924d93d 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -618,12 +618,6 @@ static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
eth_dev->data->port_id);
}
-static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
-{
- bnxt_print_link_info(eth_dev);
- return 0;
-}
-
/*
* Determine whether the current configuration requires support for scattered
* receive; return 1 if scattered receive is required and 0 if not.
@@ -986,6 +980,19 @@ static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
return bp->eth_dev->data->rx_queues[qid];
}
+/* Return rxq corresponding to a given rss table ring/group ID. */
+static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
+{
+ unsigned int i;
+
+ for (i = 0; i < bp->rx_nr_rings; i++) {
+ if (bp->grp_info[i].fw_grp_id == fwr)
+ return i;
+ }
+
+ return INVALID_HW_RING_ID;
+}
+
static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
@@ -1039,8 +1046,8 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
- struct rte_intr_handle *intr_handle
- = &bp->pdev->intr_handle;
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft, i;
/* Retrieve from the default VNIC */
if (!vnic)
@@ -1048,18 +1055,28 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
if (!vnic->rss_table)
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* EW - need to revisit here copying from uint64_t to uint16_t */
- memcpy(reta_conf, vnic->rss_table, reta_size);
- if (rte_intr_allow_others(intr_handle)) {
- if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
- bnxt_dev_lsc_intr_setup(eth_dev);
+ for (idx = 0, i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (reta_conf[idx].mask & (1ULL << sft)) {
+ uint16_t qid;
+
+ qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
+
+ if (qid == INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
+ return -EINVAL;
+ }
+ reta_conf[idx].reta[sft] = qid;
+ }
}
return 0;
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 07/10] net/bnxt: update HWRM API
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (5 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 06/10] net/bnxt: fix reta query op Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 08/10] net/bnxt: update HWRM version Lance Richardson
` (3 subsequent siblings)
10 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.19
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3112 +++++++++++++++++++-----
1 file changed, 2514 insertions(+), 598 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index e80057936..ea9a7d40e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2018 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Limited
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -68,9 +68,9 @@ struct hwrm_resp_hdr {
/* RoCE slow path command */
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
/* RoCE slow path command to query CC Gen1 support. */
-#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
/* RoCE slow path command to modify CC Gen1 support. */
-#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
/* Engine CKV - The device's serial number. */
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
/* Engine CKV - Per-function random nonce data. */
@@ -366,6 +366,7 @@ struct cmd_nums {
#define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
#define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
#define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
+ #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
#define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
#define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
@@ -442,6 +443,14 @@ struct cmd_nums {
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -591,61 +600,79 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ /*
+ * This error code is only reported by firmware when the specific
+ * request is not able to process when the HOT reset in progress.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances are not capable of hot reset.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ /*
+ * This value indicates that the HWRM response is in TLV format and
+ * should be interpreted as one or more TLVs starting with the
+ * hwrm_resp_hdr TLV. This value is not an indicatation of any error
+ * by itself, just an indicatation that the response should be parsed
+ * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
+ */
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -705,11 +732,11 @@ struct hwrm_err_output {
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
#define HWRM_VERSION_MAJOR 1
-#define HWRM_VERSION_MINOR 9
-#define HWRM_VERSION_UPDATE 2
+#define HWRM_VERSION_MINOR 10
+#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 53
-#define HWRM_VERSION_STR "1.9.2.53"
+#define HWRM_VERSION_RSVD 19
+#define HWRM_VERSION_STR "1.10.0.19"
/****************
* hwrm_ver_get *
@@ -959,6 +986,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
UINT32_C(0x100)
+ /*
+ * If set to 1, firmware is capable to support flow aging.
+ * If set to 0, firmware is not capable to support flow aging.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
+ UINT32_C(0x200)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -2031,7 +2065,7 @@ struct cmpl_base {
#define CMPL_BASE_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
/*
@@ -2116,7 +2150,7 @@ struct tx_cmpl {
#define TX_CMPL_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
@@ -2408,30 +2442,31 @@ struct rx_pkt_cmpl_hi {
* inner packet and that the ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the t_ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the t_l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
+ (UINT32_C(0x0) << 4)
/*
* The metadata field contains the VLAN tag and TPID value.
* - metadata[11:0] contains the vlan VID value.
@@ -2439,16 +2474,70 @@ struct rx_pkt_cmpl_hi {
* - metadata[15:13] contains the vlan PRI value.
* - metadata[31:16] contains the vlan TPID value.
*/
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
+ (UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
* This value is only valid if itype indicates a packet
* with an IP header.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2511,8 +2600,14 @@ struct rx_pkt_cmpl_hi {
*/
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
(UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
+ RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This indicates that there was an error in the IP header
* checksum.
@@ -2553,7 +2648,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 9)
@@ -2611,7 +2706,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 12)
@@ -2854,28 +2949,33 @@ struct rx_tpa_start_cmpl_hi {
* inner packet and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
+ UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the sum passed
* for all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
+ UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
+ UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the sum passed for
* all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
+ UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
+ UINT32_C(0xf0)
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
(UINT32_C(0x0) << 4)
@@ -2888,13 +2988,71 @@ struct rx_tpa_start_cmpl_hi {
*/
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
(UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
+ UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
+ UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
+ UINT32_C(0xc00)
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set. For TPA Start completions,
+ * the complete checksum is calculated for the first packet in the
+ * aggregation only.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2911,13 +3069,41 @@ struct rx_tpa_start_cmpl_hi {
/* When meta_format=1, this value is the VLAN TPID. */
#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
- uint16_t v2;
+ uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define RX_TPA_START_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for the packet that was found after part of the
+ * packet was already placed. The packet should be treated as
+ * invalid.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This field identifies the CFA action rule that was used for this
* packet.
@@ -3034,11 +3220,11 @@ struct rx_tpa_end_cmpl {
/*
* This value indicates what the inner packet determined for the
* packet was.
- * - 2 TCP Packet
- * Indicates that the packet was IP and TCP. This indicates
- * that the ip_cs field is valid and that the tcp_udp_cs
- * field is valid and contains the TCP checksum.
- * This also indicates that the payload_offset field is valid.
+ * - 2 TCP Packet
+ * Indicates that the packet was IP and TCP. This indicates
+ * that the ip_cs field is valid and that the tcp_udp_cs
+ * field is valid and contains the TCP checksum.
+ * This also indicates that the payload_offset field is valid.
*/
#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
@@ -3117,13 +3303,28 @@ struct rx_tpa_end_cmpl_hi {
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
- uint32_t tpa_dup_acks;
+ uint16_t tpa_dup_acks;
/*
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+ /*
+ * This value indicated the offset in bytes from the beginning of
+ * the packet where the inner payload starts. This value is valid
+ * for TCP, UDP, FCoE and RoCE packets
+ */
+ uint8_t payload_offset;
+ /*
+ * The value is the total number of aggregation buffers that were
+ * used in the TPA operation. All TPA aggregation buffer completions
+ * preceed the TPA End completion. If the value is zero, then the
+ * aggregation is completely contained in the buffer space provided
+ * in the aggregation start completion.
+ * Note that the field is simply provided as a cross check.
+ */
+ uint8_t tpa_agg_bufs;
/*
* This value is the valid when TPA completion is active. It
* indicates the length of the longest segment of the TPA operation
@@ -3154,6 +3355,9 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
/*
* This error occurs when there is a fatal HW problem in
* the chip only. It indicates that there were not
@@ -3162,6 +3366,12 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
(UINT32_C(0x2) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
/*
* This error occurs when TPA block was not configured to
* reserve adequate BDs for TPA operations on this RX
@@ -3174,8 +3384,14 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
(UINT32_C(0x4) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
+ RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/* unused5 is 16 b */
uint16_t unused_4;
/*
@@ -3239,15 +3455,23 @@ struct eject_cmpl {
* records. Odd values indicate 32B
* records.
*/
- #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
- #define EJECT_CMPL_TYPE_SFT 0
+ #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define EJECT_CMPL_TYPE_SFT 0
/*
* Statistics Ejection Completion:
* Completion of statistics data ejection buffer.
* Length = 16B
*/
- #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
- #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
+ #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
+ #define EJECT_CMPL_FLAGS_SFT 6
+ /*
+ * When this bit is '1', it indicates a packet that has an
+ * error of some type. Type of error is indicated in
+ * error_flags.
+ */
+ #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
/*
* This is the length of the statistics data stored in this
* buffer.
@@ -3258,13 +3482,47 @@ struct eject_cmpl {
* buffer corresponds to.
*/
uint32_t opaque;
- uint32_t v;
+ uint16_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
+ #define EJECT_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for statistics ejection. The statistics ejection should
+ * be treated as invalid
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Did Not Fit:
+ * Statistics did not fit into aggregation buffer provided.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
+ (UINT32_C(0x1) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+ /* reserved16 is 16 b */
+ uint16_t reserved16;
/* unused3 is 32 b */
uint32_t unused_2;
} __attribute__((packed));
@@ -3470,6 +3728,24 @@ struct hwrm_async_event_cmpl {
/* Default VNIC Configuration Change */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
UINT32_C(0x35)
+ /* HW flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ /*
+ * A debug notification being posted to the driver. These
+ * notifications are purely for diagnostic purpose and should not be
+ * used for functional purpose. The driver is not supposed to act
+ * on these messages except to log/record it.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
+ UINT32_C(0x37)
+ /*
+ * A trace log message. This contains firmware trace logs string
+ * embedded in the asynchronous message. This is an experimental
+ * event, not meant for production use at this time.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
/* HWRM Error */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
UINT32_C(0xff)
@@ -4111,9 +4387,19 @@ struct hwrm_async_event_cmpl_reset_notify {
/* opaque is 7 b */
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
- /* 8-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 8-lsb timestamp (100-msec resolution)
+ * The Minimum time required for the Firmware readiness after sending this
+ * notification to the driver instances.
+ */
uint8_t timestamp_lo;
- /* 16-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 16-lsb timestamp (100-msec resolution)
+ * The Maximum Firmware Reset bail out value in the order of 100
+ * milli seconds. The driver instances will use this value to re-initiate the
+ * registration process again if the core firmware didn’t set the ready
+ * state bit.
+ */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
@@ -4829,6 +5115,73 @@ struct hwrm_async_event_cmpl_default_vnic_change {
10
} __attribute__((packed));
+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_flow_aged {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of a hw flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates flow ID this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
+ UINT32_C(0x7fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
+ 0
+ /* Indicates flow direction this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x80000000)
+ /*
+ * If this bit set to 0, then it indicates that the aged
+ * event was rx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 31)
+ /*
+ * If this bit is set to 1, then it indicates that the aged
+ * event was tx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
struct hwrm_async_event_cmpl_hwrm_error {
uint16_t type;
@@ -5682,7 +6035,7 @@ struct hwrm_func_qcaps_output {
/*
* If the query is for a VF, then this flag shall be ignored,
* If this query is for a PF and this flag is set to 1,
- * then the PF has the capability to administer another PF.
+ * then the PF has the administrative privilege to configure another PF
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
UINT32_C(0x40000)
@@ -5700,6 +6053,19 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
UINT32_C(0x100000)
+ /*
+ * If 1, then FW has capability to allocate TX rings dynamically
+ * in ring alloc even if PF reserved pool is zero.
+ * This bit will be used only for PFs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x200000)
+ /*
+ * When this bit is '1', it indicates that core firmware is
+ * capable of Hot Reset.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
+ UINT32_C(0x400000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5864,7 +6230,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_func_qcfg_output (size:640b/80B) */
+/* hwrm_func_qcfg_output (size:704b/88B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -5951,6 +6317,13 @@ struct hwrm_func_qcfg_output {
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
UINT32_C(0x40)
+ /*
+ * If set to 1, then secure mode is enabled for this function or device.
+ * If set to 0, then secure mode is disabled (or normal mode) for this
+ * function or device.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
+ UINT32_C(0x80)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5995,7 +6368,8 @@ struct hwrm_func_qcfg_output {
uint16_t alloc_vnics;
/*
* The maximum transmission unit of the function.
- * For rings allocated on this function, this default
+ * If the reported mtu value is non-zero then it will used for the
+ * rings allocated on this function. otherwise the default
* value is used if ring MTU is not specified.
*/
uint16_t mtu;
@@ -6222,7 +6596,27 @@ struct hwrm_func_qcfg_output {
* reserved for itself (since the NQs must be contiguous in HW).
*/
uint16_t alloc_msix;
- uint8_t unused_2[5];
+ /*
+ * The number of registered VF’s associated with the PF. This field
+ * should be ignored when the request received on the VF interface.
+ * This field will be updated on the PF interface to initiate
+ * the unregister request on PF in the HOT Reset Process.
+ */
+ uint16_t registered_vfs;
+ uint8_t unused_1[3];
+ /*
+ * For backward compatibility this field must be set to 1.
+ * Older drivers might look for this field to be 1 before
+ * processing the message.
+ */
+ uint8_t always_1;
+ /*
+ * This GRC address location is used by the Host driver interfaces to poll
+ * the adapter ready state to re-initiate the registration process again
+ * after receiving the RESET Notify event.
+ */
+ uint32_t reset_addr_poll;
+ uint8_t unused_2[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -6424,6 +6818,13 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
+ /*
+ * When this bit it set, even if PF reserved pool size is zero,
+ * FW will allow driver to create TX rings in ring alloc,
+ * by reserving TX ring, S3 node dynamically.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x400000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7181,6 +7582,17 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
UINT32_C(0x8)
+ /*
+ * When this bit is '1', the function is indicating support of
+ * Hot Reset. The driver interface will destroy the resources,
+ * unregister the function and register again up on receiving
+ * the RESET_NOTIFY Async notification from the core firmware.
+ * The core firmware will this use flag and trigger the Hot Reset
+ * process only if all the registered driver instances are capable
+ * of this support.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
+ UINT32_C(0x10)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10774,6 +11186,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
@@ -10878,6 +11292,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
@@ -10930,6 +11346,9 @@ struct hwrm_port_phy_cfg_input {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* This value controls the wirespeed feature. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11159,6 +11578,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
@@ -11238,6 +11659,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
+ UINT32_C(0x4000)
/*
* Current setting of forced link speed.
* When the link speed is not being forced, this
@@ -11267,6 +11691,9 @@ struct hwrm_port_phy_qcfg_output {
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
+ UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11353,6 +11780,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11408,6 +11837,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* Current setting for wirespeed. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11574,8 +12006,20 @@ struct hwrm_port_phy_qcfg_output {
/* 1G_baseCX */
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
UINT32_C(0x1b)
+ /* 100G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
+ UINT32_C(0x1c)
+ /* 100G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
+ UINT32_C(0x1d)
+ /* 100G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
+ UINT32_C(0x1e)
+ /* 100G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
+ UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
+ HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
/* This value represents a media type. */
uint8_t media_type;
/* Unknown */
@@ -21081,6 +21525,15 @@ struct hwrm_cfa_l2_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -21887,6 +22340,15 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22107,6 +22569,12 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22212,6 +22680,12 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22312,6 +22786,12 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22517,8 +22997,14 @@ struct hwrm_cfa_encap_record_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -22872,6 +23358,15 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23381,6 +23876,15 @@ struct hwrm_cfa_em_flow_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23586,13 +24090,13 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_profile_alloc *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23620,266 +24124,1670 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
- */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
/*
- * This bit must be '1' for the src_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
- UINT32_C(0x4)
+ uint16_t reserved1;
/*
- * This bit must be '1' for the dst_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
- UINT32_C(0x8)
- /*
+ uint32_t reserved2;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_meter_profile_free *
+ *******************************/
+
+
+/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_profile_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_meter_profile_cfg *
+ ******************************/
+
+
+/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
+ UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint32_t reserved;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************************
+ * hwrm_cfa_meter_instance_alloc *
+ *********************************/
+
+
+/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
+ UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
+
+
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the src_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x8)
+ /*
* This bit must be '1' for the ovlan_vid field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
- UINT32_C(0x10)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the t_ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the t_ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the ethertype field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the src_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the dst_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the ipaddr_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the ip_protocol field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the src_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the dst_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x10000)
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
+ */
+ uint32_t tunnel_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0;
+ uint16_t unused_1;
+ /*
+ * This value indicates the source MAC address in
+ * the Ethernet header.
+ */
+ uint8_t src_macaddr[6];
+ uint8_t unused_2[2];
/*
- * This bit must be '1' for the ivlan_vid field to be
- * configured.
+ * This value indicates the destination MAC address in
+ * the Ethernet header.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
- UINT32_C(0x20)
+ uint8_t dst_macaddr[6];
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ivlan_vid;
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ivlan_vid;
+ /* This value indicates the ethertype in the Ethernet header. */
+ uint16_t ethertype;
+ /*
+ * This value indicates the type of IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
+ */
+ uint8_t ip_addr_type;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* IPv4 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ UINT32_C(0x4)
+ /* IPv6 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+ UINT32_C(0x6)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ /*
+ * The value of protocol filed in IP header.
+ * Applies to UDP and TCP traffic.
+ * 6 - TCP
+ * 17 - UDP
+ */
+ uint8_t ip_protocol;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+ UINT32_C(0x0)
+ /* TCP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+ UINT32_C(0x6)
+ /* UDP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+ UINT32_C(0x11)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint16_t unused_3;
+ uint32_t unused_4;
+ /*
+ * The value of source IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t src_ipaddr[4];
+ /*
+ * The value of destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t dst_ipaddr[4];
+ /*
+ * The value of source port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t src_port;
+ /*
+ * The value of destination port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t dst_port;
+ /*
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path.
+ */
+ uint16_t dst_id;
+ /*
+ * If set, this value shall represent the L2 context that matches the L2
+ * information of the decap filter.
+ */
+ uint16_t l2_ctxt_ref_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_decap_filter_free *
+ ******************************/
+
+
+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_decap_filter_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_flow_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
+ UINT32_C(0x1)
+ /* num_vlan is 2 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
+ UINT32_C(0x6)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
+ /* no tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
+ (UINT32_C(0x0) << 1)
+ /* 1 tag */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
+ (UINT32_C(0x1) << 1)
+ /* 2 tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
+ (UINT32_C(0x2) << 1)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
+ /* Enumeration denoting the Flow Type. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
+ UINT32_C(0x38)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
+ /* L2 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
+ (UINT32_C(0x0) << 3)
+ /* IPV4 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
+ (UINT32_C(0x1) << 3)
+ /* IPV6 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
+ (UINT32_C(0x2) << 3)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
/*
- * This bit must be '1' for the t_ovlan_vid field to be
- * configured.
+ * when set to 1, indicates TX flow offload for function specified in src_fid and
+ * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
+ * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
+ * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
+ * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
+ * belong to the children VFs of the same PF to indicate VM to VM flow.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
UINT32_C(0x40)
/*
- * This bit must be '1' for the t_ivlan_vid field to be
- * configured.
+ * when set to 1, indicates RX flow offload for function specified in dst_fid and
+ * the src_fid should be set to invalid value.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x80)
/*
- * This bit must be '1' for the ethertype field to be
- * configured.
+ * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
+ * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
+ * This flag is only valid when the flow direction is RX.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
/*
- * This bit must be '1' for the src_ipaddr field to be
- * configured.
+ * Tx Flow: vf fid.
+ * Rx Flow: pf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ uint16_t src_fid;
+ /* Tunnel handle valid when tunnel flag is set. */
+ uint32_t tunnel_handle;
+ uint16_t action_flags;
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* recycle is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* meter is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /* nat_src is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
+ UINT32_C(0x20)
+ /* nat_dest is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
+ UINT32_C(0x40)
+ /* nat_ipv4_address is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
+ UINT32_C(0x80)
+ /* l2_header_rewrite is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
+ UINT32_C(0x100)
+ /* ttl_decrement is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
UINT32_C(0x200)
/*
- * This bit must be '1' for the dst_ipaddr field to be
- * configured.
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header. The type of tunnel
+ * is specified in the tunnel_type field.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
UINT32_C(0x400)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x800)
/*
- * This bit must be '1' for the ipaddr_type field to be
- * configured.
+ * Tx Flow: pf or vf fid.
+ * Rx Flow: vf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
- UINT32_C(0x800)
+ uint16_t dst_fid;
+ /* VLAN tpid, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tci;
+ /* Meter id, valid when meter flag is set. */
+ uint16_t act_meter_id;
+ /* Flow with the same l2 context tcam key. */
+ uint16_t ref_flow_handle;
+ /* This value sets the match value for the ethertype. */
+ uint16_t ethertype;
+ /* valid when num tags is 1 or 2. */
+ uint16_t outer_vlan_tci;
+ /* This value sets the match value for the Destination MAC address. */
+ uint16_t dmac[3];
+ /* valid when num tags is 2. */
+ uint16_t inner_vlan_tci;
+ /* This value sets the match value for the Source MAC address. */
+ uint16_t smac[3];
+ /* The bit length of destination IP address mask. */
+ uint8_t ip_dst_mask_len;
+ /* The bit length of source IP address mask. */
+ uint8_t ip_src_mask_len;
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
/*
- * This bit must be '1' for the ip_protocol field to be
- * configured.
+ * The value of source port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
- UINT32_C(0x1000)
+ uint16_t l4_src_port;
/*
- * This bit must be '1' for the src_port field to be
- * configured.
+ * The value of source port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
- UINT32_C(0x2000)
+ uint16_t l4_src_port_mask;
/*
- * This bit must be '1' for the dst_port field to be
- * configured.
+ * The value of destination port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
- UINT32_C(0x4000)
+ uint16_t l4_dst_port;
/*
- * This bit must be '1' for the dst_id field to be
- * configured.
+ * The value of destination port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x8000)
+ uint16_t l4_dst_port_mask;
/*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
+ * NAT IPv4/6 address based on address type flag.
+ * 0 values are ignored.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x10000)
+ uint32_t nat_ip_address[4];
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
/*
- * Tunnel identifier.
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
+ * The NAT source/destination port based on direction flag.
+ * Applies to UDP and TCP traffic.
+ * 0 values are ignored.
*/
- uint32_t tunnel_id;
+ uint16_t nat_port;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* The value of ip protocol. */
+ uint8_t ip_proto;
/* Tunnel Type. */
uint8_t tunnel_type;
/* Non-tunnel */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
/* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
UINT32_C(0x3)
/* IP in IP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
/* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
UINT32_C(0x7)
/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
UINT32_C(0x8)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0;
- uint16_t unused_1;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
+struct hwrm_cfa_flow_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[2];
/*
- * This value indicates the source MAC address in
- * the Ethernet header.
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_free *
+ **********************/
+
+
+/* hwrm_cfa_flow_free_input (size:256b/32B) */
+struct hwrm_cfa_flow_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t src_macaddr[6];
- uint8_t unused_2[2];
+ uint16_t cmpl_ring;
/*
- * This value indicates the destination MAC address in
- * the Ethernet header.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t dst_macaddr[6];
+ uint16_t seq_id;
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the Ethernet header.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t ovlan_vid;
+ uint16_t target_id;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the Ethernet header.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t ivlan_vid;
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_free_output (size:256b/32B) */
+struct hwrm_cfa_flow_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* packet is 64 b */
+ uint64_t packet;
+ /* byte is 64 b */
+ uint64_t byte;
+ uint8_t unused_0[7];
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the tunnel Ethernet header.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t t_ovlan_vid;
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_info *
+ **********************/
+
+
+/* hwrm_cfa_flow_info_input (size:256b/32B) */
+struct hwrm_cfa_flow_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the tunnel Ethernet header.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t t_ivlan_vid;
- /* This value indicates the ethertype in the Ethernet header. */
- uint16_t ethertype;
+ uint16_t cmpl_ring;
/*
- * This value indicates the type of IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t ip_addr_type;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* IPv4 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
- UINT32_C(0x4)
- /* IPv6 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
- UINT32_C(0x6)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ uint16_t seq_id;
/*
- * The value of protocol filed in IP header.
- * Applies to UDP and TCP traffic.
- * 6 - TCP
- * 17 - UDP
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint8_t ip_protocol;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
- UINT32_C(0x0)
- /* TCP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
- UINT32_C(0x6)
- /* UDP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
- UINT32_C(0x11)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
- uint16_t unused_3;
- uint32_t unused_4;
+ uint16_t target_id;
/*
- * The value of source IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t src_ipaddr[4];
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ /* Max flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
+ UINT32_C(0xfff)
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
+ /* CNP flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
+ UINT32_C(0x1000)
+ /* RoCEv1 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
+ UINT32_C(0x2000)
+ /* RoCEv2 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
+ UINT32_C(0x4000)
+ /* Direction rx = 1 */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
+ UINT32_C(0x8000)
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_info_output (size:448b/56B) */
+struct hwrm_cfa_flow_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* flags is 8 b */
+ uint8_t flags;
+ /* profile is 8 b */
+ uint8_t profile;
+ /* src_fid is 16 b */
+ uint16_t src_fid;
+ /* dst_fid is 16 b */
+ uint16_t dst_fid;
+ /* l2_ctxt_id is 16 b */
+ uint16_t l2_ctxt_id;
+ /* em_info is 64 b */
+ uint64_t em_info;
+ /* tcam_info is 64 b */
+ uint64_t tcam_info;
+ /* vfp_tcam_info is 64 b */
+ uint64_t vfp_tcam_info;
+ /* ar_id is 16 b */
+ uint16_t ar_id;
+ /* flow_handle is 16 b */
+ uint16_t flow_handle;
+ /* tunnel_handle is 32 b */
+ uint32_t tunnel_handle;
+ /* The flow aging timer for the flow, the unit is 100 milliseconds */
+ uint16_t flow_timer;
+ uint8_t unused_0[5];
/*
- * The value of destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint32_t dst_ipaddr[4];
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_flush *
+ ***********************/
+
+
+/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+struct hwrm_cfa_flow_flush_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * The value of source port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t src_port;
+ uint16_t cmpl_ring;
/*
- * The value of destination port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t dst_port;
+ uint16_t seq_id;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t dst_id;
+ uint16_t target_id;
/*
- * If set, this value shall represent the L2 context that matches the L2
- * information of the decap filter.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t l2_ctxt_ref_id;
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_alloc_output {
+/* hwrm_cfa_flow_flush_output (size:128b/16B) */
+struct hwrm_cfa_flow_flush_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23888,9 +25796,7 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -23901,13 +25807,13 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_decap_filter_free *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_stats *
+ ***********************/
-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_decap_filter_free_input {
+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
+struct hwrm_cfa_flow_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23935,13 +25841,53 @@ struct hwrm_cfa_decap_filter_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[4];
+ /* Flow handle. */
+ uint16_t num_flows;
+ /* Flow handle. */
+ uint16_t flow_handle_0;
+ /* Flow handle. */
+ uint16_t flow_handle_1;
+ /* Flow handle. */
+ uint16_t flow_handle_2;
+ /* Flow handle. */
+ uint16_t flow_handle_3;
+ /* Flow handle. */
+ uint16_t flow_handle_4;
+ /* Flow handle. */
+ uint16_t flow_handle_5;
+ /* Flow handle. */
+ uint16_t flow_handle_6;
+ /* Flow handle. */
+ uint16_t flow_handle_7;
+ /* Flow handle. */
+ uint16_t flow_handle_8;
+ /* Flow handle. */
+ uint16_t flow_handle_9;
+ uint8_t unused_0[2];
+ /* Flow ID of a flow. */
+ uint32_t flow_id_0;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_1;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_2;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_3;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_4;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_5;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_6;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_7;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_8;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_9;
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_free_output {
+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
+struct hwrm_cfa_flow_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23950,6 +25896,46 @@ struct hwrm_cfa_decap_filter_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* packet_0 is 64 b */
+ uint64_t packet_0;
+ /* packet_1 is 64 b */
+ uint64_t packet_1;
+ /* packet_2 is 64 b */
+ uint64_t packet_2;
+ /* packet_3 is 64 b */
+ uint64_t packet_3;
+ /* packet_4 is 64 b */
+ uint64_t packet_4;
+ /* packet_5 is 64 b */
+ uint64_t packet_5;
+ /* packet_6 is 64 b */
+ uint64_t packet_6;
+ /* packet_7 is 64 b */
+ uint64_t packet_7;
+ /* packet_8 is 64 b */
+ uint64_t packet_8;
+ /* packet_9 is 64 b */
+ uint64_t packet_9;
+ /* byte_0 is 64 b */
+ uint64_t byte_0;
+ /* byte_1 is 64 b */
+ uint64_t byte_1;
+ /* byte_2 is 64 b */
+ uint64_t byte_2;
+ /* byte_3 is 64 b */
+ uint64_t byte_3;
+ /* byte_4 is 64 b */
+ uint64_t byte_4;
+ /* byte_5 is 64 b */
+ uint64_t byte_5;
+ /* byte_6 is 64 b */
+ uint64_t byte_6;
+ /* byte_7 is 64 b */
+ uint64_t byte_7;
+ /* byte_8 is 64 b */
+ uint64_t byte_8;
+ /* byte_9 is 64 b */
+ uint64_t byte_9;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -23961,13 +25947,13 @@ struct hwrm_cfa_decap_filter_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_alloc *
- ***********************/
+/***********************************
+ * hwrm_cfa_flow_aging_timer_reset *
+ ***********************************/
-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_flow_alloc_input {
+/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_timer_reset_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23989,219 +25975,21 @@ struct hwrm_cfa_flow_alloc_input {
*/
uint16_t target_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint16_t flags;
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
- UINT32_C(0x1)
- /* num_vlan is 2 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
- UINT32_C(0x6)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
- /* no tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
- (UINT32_C(0x0) << 1)
- /* 1 tag */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
- (UINT32_C(0x1) << 1)
- /* 2 tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
- (UINT32_C(0x2) << 1)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
- /* Enumeration denoting the Flow Type. */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
- UINT32_C(0x38)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
- /* L2 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
- (UINT32_C(0x0) << 3)
- /* IPV4 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
- (UINT32_C(0x1) << 3)
- /* IPV6 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
- (UINT32_C(0x2) << 3)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
- /*
- * when set to 1, indicates TX flow offload for function specified in src_fid and
- * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
- * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
- * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
- * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
- * belong to the children VFs of the same PF to indicate VM to VM flow.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x40)
- /*
- * when set to 1, indicates RX flow offload for function specified in dst_fid and
- * the src_fid should be set to invalid value.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x80)
- /*
- * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
- * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
- * This flag is only valid when the flow direction is RX.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
- UINT32_C(0x100)
- /*
- * Tx Flow: vf fid.
- * Rx Flow: pf fid.
- */
- uint16_t src_fid;
- /* Tunnel handle valid when tunnel flag is set. */
- uint32_t tunnel_handle;
- uint16_t action_flags;
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
- UINT32_C(0x1)
- /* recycle is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
- UINT32_C(0x4)
- /* meter is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
- UINT32_C(0x8)
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
- UINT32_C(0x10)
- /* nat_src is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
- UINT32_C(0x20)
- /* nat_dest is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
- UINT32_C(0x40)
- /* nat_ipv4_address is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
- UINT32_C(0x80)
- /* l2_header_rewrite is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
- UINT32_C(0x100)
- /* ttl_decrement is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
- UINT32_C(0x200)
- /*
- * If set to 1 and flow direction is TX, it indicates decap of L2 header
- * and encap of tunnel header. If set to 1 and flow direction is RX, it
- * indicates decap of tunnel header and encap L2 header. The type of tunnel
- * is specified in the tunnel_type field.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
- UINT32_C(0x400)
- /*
- * Tx Flow: pf or vf fid.
- * Rx Flow: vf fid.
- */
- uint16_t dst_fid;
- /* VLAN tpid, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tpid;
- /* VLAN tci, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tci;
- /* Meter id, valid when meter flag is set. */
- uint16_t act_meter_id;
- /* Flow with the same l2 context tcam key. */
- uint16_t ref_flow_handle;
- /* This value sets the match value for the ethertype. */
- uint16_t ethertype;
- /* valid when num tags is 1 or 2. */
- uint16_t outer_vlan_tci;
- /* This value sets the match value for the Destination MAC address. */
- uint16_t dmac[3];
- /* valid when num tags is 2. */
- uint16_t inner_vlan_tci;
- /* This value sets the match value for the Source MAC address. */
- uint16_t smac[3];
- /* The bit length of destination IP address mask. */
- uint8_t ip_dst_mask_len;
- /* The bit length of source IP address mask. */
- uint8_t ip_src_mask_len;
- /* The value of destination IPv4/IPv6 address. */
- uint32_t ip_dst[4];
- /* The source IPv4/IPv6 address. */
- uint32_t ip_src[4];
- /*
- * The value of source port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port;
- /*
- * The value of source port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port_mask;
- /*
- * The value of destination port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port;
- /*
- * The value of destination port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port_mask;
- /*
- * NAT IPv4/6 address based on address type flag.
- * 0 values are ignored.
- */
- uint32_t nat_ip_address[4];
- /* L2 header re-write Destination MAC address. */
- uint16_t l2_rewrite_dmac[3];
- /*
- * The NAT source/destination port based on direction flag.
- * Applies to UDP and TCP traffic.
- * 0 values are ignored.
- */
- uint16_t nat_port;
- /* L2 header re-write Source MAC address. */
- uint16_t l2_rewrite_smac[3];
- /* The value of ip protocol. */
- uint8_t ip_proto;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
-struct hwrm_cfa_flow_alloc_output {
+/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_timer_reset_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24210,20 +25998,7 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[2];
- /*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
- */
- uint32_t flow_id;
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24234,13 +26009,13 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_flow_free *
- **********************/
+/***************************
+ * hwrm_cfa_flow_aging_cfg *
+ ***************************/
-/* hwrm_cfa_flow_free_input (size:256b/32B) */
-struct hwrm_cfa_flow_free_input {
+/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24268,15 +26043,38 @@ struct hwrm_cfa_flow_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[6];
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
+ /* The bit field to enable per flow aging configuration. */
+ uint16_t enables;
+ /* This bit must be '1' for the tcp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
+ UINT32_C(0x1)
+ /* This bit must be '1' for the tcp finish timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
+ UINT32_C(0x2)
+ /* This bit must be '1' for the udp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
+ UINT32_C(0x4)
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_flow_timer;
+ /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_fin_timer;
+ /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
+ uint32_t udp_flow_timer;
} __attribute__((packed));
-/* hwrm_cfa_flow_free_output (size:256b/32B) */
-struct hwrm_cfa_flow_free_output {
+/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24285,10 +26083,6 @@ struct hwrm_cfa_flow_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet is 64 b */
- uint64_t packet;
- /* byte is 64 b */
- uint64_t byte;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24300,13 +26094,13 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_flush *
- ***********************/
+/****************************
+ * hwrm_cfa_flow_aging_qcfg *
+ ****************************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
-struct hwrm_cfa_flow_flush_input {
+/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24334,12 +26128,21 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- uint8_t unused_0[4];
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_flush_output (size:128b/16B) */
-struct hwrm_cfa_flow_flush_output {
+/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24348,7 +26151,13 @@ struct hwrm_cfa_flow_flush_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_flow_timer;
+ /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_fin_timer;
+ /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t udp_flow_timer;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24359,13 +26168,13 @@ struct hwrm_cfa_flow_flush_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_stats *
- ***********************/
+/*****************************
+ * hwrm_cfa_flow_aging_qcaps *
+ *****************************/
-/* hwrm_cfa_flow_stats_input (size:640b/80B) */
-struct hwrm_cfa_flow_stats_input {
+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24393,53 +26202,21 @@ struct hwrm_cfa_flow_stats_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow handle. */
- uint16_t num_flows;
- /* Flow handle. */
- uint16_t flow_handle_0;
- /* Flow handle. */
- uint16_t flow_handle_1;
- /* Flow handle. */
- uint16_t flow_handle_2;
- /* Flow handle. */
- uint16_t flow_handle_3;
- /* Flow handle. */
- uint16_t flow_handle_4;
- /* Flow handle. */
- uint16_t flow_handle_5;
- /* Flow handle. */
- uint16_t flow_handle_6;
- /* Flow handle. */
- uint16_t flow_handle_7;
- /* Flow handle. */
- uint16_t flow_handle_8;
- /* Flow handle. */
- uint16_t flow_handle_9;
- uint8_t unused_0[2];
- /* Flow ID of a flow. */
- uint32_t flow_id_0;
- /* Flow ID of a flow. */
- uint32_t flow_id_1;
- /* Flow ID of a flow. */
- uint32_t flow_id_2;
- /* Flow ID of a flow. */
- uint32_t flow_id_3;
- /* Flow ID of a flow. */
- uint32_t flow_id_4;
- /* Flow ID of a flow. */
- uint32_t flow_id_5;
- /* Flow ID of a flow. */
- uint32_t flow_id_6;
- /* Flow ID of a flow. */
- uint32_t flow_id_7;
- /* Flow ID of a flow. */
- uint32_t flow_id_8;
- /* Flow ID of a flow. */
- uint32_t flow_id_9;
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
-struct hwrm_cfa_flow_stats_output {
+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_flow_aging_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24448,46 +26225,14 @@ struct hwrm_cfa_flow_stats_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet_0 is 64 b */
- uint64_t packet_0;
- /* packet_1 is 64 b */
- uint64_t packet_1;
- /* packet_2 is 64 b */
- uint64_t packet_2;
- /* packet_3 is 64 b */
- uint64_t packet_3;
- /* packet_4 is 64 b */
- uint64_t packet_4;
- /* packet_5 is 64 b */
- uint64_t packet_5;
- /* packet_6 is 64 b */
- uint64_t packet_6;
- /* packet_7 is 64 b */
- uint64_t packet_7;
- /* packet_8 is 64 b */
- uint64_t packet_8;
- /* packet_9 is 64 b */
- uint64_t packet_9;
- /* byte_0 is 64 b */
- uint64_t byte_0;
- /* byte_1 is 64 b */
- uint64_t byte_1;
- /* byte_2 is 64 b */
- uint64_t byte_2;
- /* byte_3 is 64 b */
- uint64_t byte_3;
- /* byte_4 is 64 b */
- uint64_t byte_4;
- /* byte_5 is 64 b */
- uint64_t byte_5;
- /* byte_6 is 64 b */
- uint64_t byte_6;
- /* byte_7 is 64 b */
- uint64_t byte_7;
- /* byte_8 is 64 b */
- uint64_t byte_8;
- /* byte_9 is 64 b */
- uint64_t byte_9;
+ /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_flow_timer;
+ /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_fin_timer;
+ /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t max_udp_flow_timer;
+ /* The maximum aging flows that HW can support. */
+ uint32_t max_aging_flows;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24706,6 +26451,12 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24765,8 +26516,14 @@ struct hwrm_tunnel_dst_port_query_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0[7];
} __attribute__((packed));
@@ -24857,8 +26614,14 @@ struct hwrm_tunnel_dst_port_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* This field represents the value of L4 destination port used
@@ -24948,8 +26711,14 @@ struct hwrm_tunnel_dst_port_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -25025,6 +26794,52 @@ struct ctx_hw_stats {
uint64_t tpa_aborts;
} __attribute__((packed));
+/* Periodic Engine statistics context DMA to host. */
+/* ctx_eng_stats (size:512b/64B) */
+struct ctx_eng_stats {
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+} __attribute__((packed));
+
/***********************
* hwrm_stat_ctx_alloc *
***********************/
@@ -25081,7 +26896,7 @@ struct hwrm_stat_ctx_alloc_input {
* than offloaded RoCE traffic shall not be included in this
* statistic context.
* When this bit is set to '0', the statistics context shall be
- * used for the network traffic other than offloaded RoCE traffic.
+ * used for network traffic or engine traffic.
*/
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
uint8_t unused_0[3];
@@ -25272,6 +27087,107 @@ struct hwrm_stat_ctx_query_output {
uint8_t valid;
} __attribute__((packed));
+/***************************
+ * hwrm_stat_ctx_eng_query *
+ ***************************/
+
+
+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_eng_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
+struct hwrm_stat_ctx_eng_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***************************
* hwrm_stat_ctx_clr_stats *
***************************/
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 08/10] net/bnxt: update HWRM version
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (6 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 07/10] net/bnxt: update HWRM API Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 09/10] net/bnxt: HWRM version update Lance Richardson
` (2 subsequent siblings)
10 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM version to 1.10.0.48
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3156 +++++++++++++++++++++---
1 file changed, 2874 insertions(+), 282 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index ea9a7d40e..00a8ff87e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -260,6 +260,7 @@ struct cmd_nums {
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
+ #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
@@ -372,6 +373,8 @@ struct cmd_nums {
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
+ #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
+ #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
@@ -397,6 +400,8 @@ struct cmd_nums {
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
/* Experimental */
+ #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
+ /* Experimental */
#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
@@ -407,6 +412,8 @@ struct cmd_nums {
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
/* Experimental */
+ #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
+ /* Experimental */
#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
/* Experimental */
#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
@@ -451,6 +458,34 @@ struct cmd_nums {
#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
+ /* Experimental */
+ #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
+ /* Experimental */
+ #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
+ /* Experimental */
+ #define HWRM_CFA_EEM_OP UINT32_C(0x123)
+ /* Experimental */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -469,6 +504,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
/* Engine CKV - Generate and encrypt a new AES key. */
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
+ /* Engine CKV - Configure a label index with a label value. */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -523,6 +560,8 @@ struct cmd_nums {
#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
/* Engine - Set the on-die RQE credit update location. */
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
+ /* Engine - Query the engine function configuration. */
+ #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
/* Experimental */
#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
/* Experimental */
@@ -573,6 +612,10 @@ struct cmd_nums {
/* */
#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
/* Experimental */
+ #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
+ /* Experimental */
+ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
+ /* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
#define HWRM_NVM_FLUSH UINT32_C(0xfff0)
@@ -724,8 +767,8 @@ struct hwrm_err_output {
#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
/* hwrm_func_buf_rgtr */
#define HWRM_MAX_REQ_LEN 128
-/* hwrm_selftest_qlist */
-#define HWRM_MAX_RESP_LEN 280
+/* hwrm_cfa_flow_info */
+#define HWRM_MAX_RESP_LEN 704
/* 7 bit indirection table index. */
#define HW_HASH_INDEX_SIZE 0x80
#define HW_HASH_KEY_SIZE 40
@@ -735,8 +778,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 19
-#define HWRM_VERSION_STR "1.10.0.19"
+#define HWRM_VERSION_RSVD 48
+#define HWRM_VERSION_STR "1.10.0.48"
/****************
* hwrm_ver_get *
@@ -993,6 +1036,32 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
UINT32_C(0x200)
+ /*
+ * If set to 1, firmware is capable to support advanced flow counters like,
+ * Meter drop counters and EEM counters.
+ * If set to 0, firmware is not capable to support advanced flow counters.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * If set to 1, the firmware is able to support the use of the CFA
+ * Extended Exact Match(EEM) feature.
+ * If set to 0, firmware is not capable to support the use of the
+ * CFA EEM feature.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
+ UINT32_C(0x800)
+ /*
+ * If set to 1, the firmware is able to support advance CFA flow management
+ * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
+ * If set to 0, then the firmware doesn’t support the advance CFA flow management
+ * features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
+ UINT32_C(0x1000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -3695,6 +3764,9 @@ struct hwrm_async_event_cmpl {
/* Reset notification to clients */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
UINT32_C(0x8)
+ /* Master function selection event */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
/* Function driver unloaded */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
UINT32_C(0x10)
@@ -3739,6 +3811,40 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
UINT32_C(0x37)
+ /*
+ * A EEM flow cached memory flush request event being posted to the PF
+ * driver.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ /*
+ * A EEM flow cache memory flush completion event being posted to the
+ * firmware by the PF driver. This is indication that host EEM flush
+ * has completed by the PF.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ /*
+ * A tcp flag action change event being posted to the PF or trusted VF
+ * driver by the firmware. The PF or trusted VF driver should query
+ * the firmware for the new TCP flag action update after receiving
+ * this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ /*
+ * A eem flow active event being posted to the PF or trusted VF driver
+ * by the firmware. The PF or trusted VF driver should update the
+ * flow's aging timer after receiving this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ /*
+ * A eem cfg change event being posted to the trusted VF driver by the
+ * firmware if the parent PF EEM configuration changed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -4450,6 +4556,75 @@ struct hwrm_async_event_cmpl_reset_notify {
16
} __attribute__((packed));
+/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_recovery {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message can be used for selecting or
+ * deselecting master function for error recovery,
+ * and to communicate to all the functions whether error recovery
+ * was enabled/disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates driver action requested */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
+ 0
+ /*
+ * If set to 1, this function is selected as Master function.
+ * This function has responsibility to do 'chip reset' when it
+ * detects a fatal error. If set to 0, master function functionality
+ * is disabled on this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, error recovery is enabled.
+ * If set to 0, error recovery is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
struct hwrm_async_event_cmpl_func_drvr_unload {
uint16_t type;
@@ -5182,8 +5357,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {
HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
} __attribute__((packed));
-/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
-struct hwrm_async_event_cmpl_hwrm_error {
+/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_req {
uint16_t type;
/*
* This field indicates the exact type of the completion.
@@ -5192,133 +5367,549 @@ struct hwrm_async_event_cmpl_hwrm_error {
* records. Odd values indicate 32B
* records.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
UINT32_C(0x3f)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
+ 0
/* HWRM Asynchronous Event Information */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
UINT32_C(0x2e)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
/* Identifiers of events. */
uint16_t event_id;
- /* HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Notification of a eem_cache_flush request */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
/* Event specific data */
uint32_t event_data2;
- /* Severity of HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
- /* Warning */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
- UINT32_C(0x0)
- /* Non-fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
- UINT32_C(0x1)
- /* Fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
- UINT32_C(0x2)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
+ UINT32_C(0x1)
/* opaque is 7 b */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
/* 8-lsb timestamp from POR (100-msec resolution) */
uint8_t timestamp_lo;
/* 16-lsb timestamp from POR (100-msec resolution) */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
- /* Time stamp for error event */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
- UINT32_C(0x1)
} __attribute__((packed));
-/*******************
- * hwrm_func_reset *
- *******************/
-
-
-/* hwrm_func_reset_input (size:192b/24B) */
-struct hwrm_func_reset_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_done {
+ uint16_t type;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t cmpl_ring;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Notification of a host eem_cache_flush has completed. This event
+ * is generated by the host driver.
*/
- uint16_t seq_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- uint16_t target_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates function ID that this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
+ 0
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_tcp_flag_action_change {
+ uint16_t type;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint64_t resp_addr;
- uint32_t enables;
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of tcp flag action change */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * This bit must be '1' for the vf_id_valid field to be
- * configured.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_flow_active {
+ uint16_t type;
/*
- * The ID of the VF that this PF is trying to reset.
- * Only the parent PF shall be allowed to reset a child VF.
- *
- * A parent PF driver shall use this field only when a specific child VF
- * is requested to be reset.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t vf_id;
- /* This value indicates the level of a function reset. */
- uint8_t func_reset_level;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of an active eem flow */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Indicates the 2nd global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
+ 0
/*
- * Reset the caller function and its children VFs (if any). If no
- * children functions exist, then reset the caller function only.
- */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
- UINT32_C(0x0)
- /* Reset the caller function only */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
- UINT32_C(0x1)
+ * Indicates flow direction of the flow identified by
+ * the global_id_2.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
+ uint8_t opaque_v;
/*
- * Reset all children VFs of the caller function driver if the
- * caller is a PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver with
- * no children VFs.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
- UINT32_C(0x2)
- /*
- * Reset a specific VF of the caller function driver if the caller
- * is the parent PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver that is not
- * the parent of the VF that is being requested to reset.
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the 1st global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
+ 0
+ /*
+ * Indicates flow direction of the flow identified by the
+ * global_id_1.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this is rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this is tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
+ /*
+ * Indicates EEM flow aging mode this event occured on. If
+ * this bit is set to 0, the event_data1 is the EEM global
+ * ID. If this bit is set to 1, the event_data1 is the number
+ * of global ID in the context memory.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
+ UINT32_C(0x80000000)
+ /* EEM flow aging mode 0. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
+ (UINT32_C(0x0) << 31)
+ /* EEM flow aging mode 1. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cfg_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of EEM configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Value of 1 to indicate EEM TX configuration is enabled. Value of
+ * 0 to indicate the EEM TX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
+ * to indicate the EEM RX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
+struct hwrm_async_event_cmpl_fw_trace_msg {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Firmware trace log message */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
+ /* Trace byte 0 to 3 */
+ uint32_t event_data2;
+ /* Trace byte0 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
+ /* Trace byte1 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
+ /* Trace byte2 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
+ /* Trace byte3 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
+ /* Trace flags */
+ uint8_t timestamp_lo;
+ /* Indicates if the string is partial or complete. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
+ UINT32_C(0x1)
+ /* Complete string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
+ UINT32_C(0x0)
+ /* Partial string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
+ UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
+ /* Indicates the firmware that sent the trace message. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
+ UINT32_C(0x2)
+ /* Primary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
+ (UINT32_C(0x0) << 1)
+ /* Secondary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
+ /* Trace byte 4 to 5 */
+ uint16_t timestamp_hi;
+ /* Trace byte4 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
+ /* Trace byte5 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
+ /* Trace byte 6 to 9 */
+ uint32_t event_data1;
+ /* Trace byte6 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
+ /* Trace byte7 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
+ /* Trace byte8 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
+ /* Trace byte9 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
+struct hwrm_async_event_cmpl_hwrm_error {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Severity of HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
+ /* Warning */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
+ UINT32_C(0x0)
+ /* Non-fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
+ UINT32_C(0x1)
+ /* Fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Time stamp for error event */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
+ UINT32_C(0x1)
+} __attribute__((packed));
+
+/*******************
+ * hwrm_func_reset *
+ *******************/
+
+
+/* hwrm_func_reset_input (size:192b/24B) */
+struct hwrm_func_reset_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vf_id_valid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ /*
+ * The ID of the VF that this PF is trying to reset.
+ * Only the parent PF shall be allowed to reset a child VF.
+ *
+ * A parent PF driver shall use this field only when a specific child VF
+ * is requested to be reset.
+ */
+ uint16_t vf_id;
+ /* This value indicates the level of a function reset. */
+ uint8_t func_reset_level;
+ /*
+ * Reset the caller function and its children VFs (if any). If no
+ * children functions exist, then reset the caller function only.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
+ UINT32_C(0x0)
+ /* Reset the caller function only */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
+ UINT32_C(0x1)
+ /*
+ * Reset all children VFs of the caller function driver if the
+ * caller is a PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver with
+ * no children VFs.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
+ UINT32_C(0x2)
+ /*
+ * Reset a specific VF of the caller function driver if the caller
+ * is the parent PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver that is not
+ * the parent of the VF that is being requested to reset.
*/
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
UINT32_C(0x3)
@@ -6066,6 +6657,12 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
UINT32_C(0x400000)
+ /*
+ * This flag will be set to 1 by the FW if FW supports adapter error
+ * recovery.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
+ UINT32_C(0x800000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6813,8 +7410,7 @@ struct hwrm_func_cfg_input {
* resident HWRM clients, only the parent PF driver shall be allowed
* to initiate this change on one of its children VFs. If this bit is
* set to 1, then the VF that is being configured is requested to be
- * trusted. If this bit is set to 0, then the VF that is being configured
- * is requested to be not trusted.
+ * trusted.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
@@ -6825,6 +7421,25 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
UINT32_C(0x400000)
+ /*
+ * This bit requests that the firmware test to see if all the assets
+ * requested in this command (i.e. number of NQ rings) are available.
+ * The firmware will return an error if the requested assets are
+ * not available. The firwmare will NOT reserve the assets if they
+ * are available.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
+ UINT32_C(0x800000)
+ /*
+ * This configuration change can be initiated by a PF driver. This
+ * configuration request shall be targeted to a VF. From local host
+ * resident HWRM clients, only the parent PF driver shall be allowed
+ * to initiate this change on one of its children VFs. If this bit is
+ * set to 1, then the VF that is being configured is requested to be
+ * untrusted.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
+ UINT32_C(0x1000000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7593,6 +8208,19 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
UINT32_C(0x10)
+ /*
+ * When this bit is 1, the function is indicating the support of the
+ * error recovery capability. Error recovery support will be used by
+ * firmware only if all the driver instances support error recovery
+ * process. By setting this bit, driver is indicating support for
+ * corresponding async event completion message. These will be
+ * delivered to the driver even if they did not register for it.
+ * If supported, after receiving reset notify async event with fatal
+ * flag set in event data1, then all the drivers have to tear down
+ * their resources without sending any HWRM commands to FW.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
+ UINT32_C(0x20)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10270,17 +10898,384 @@ struct hwrm_func_backing_store_qcfg_output {
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as 1
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
*/
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/****************************
+ * hwrm_error_recovery_qcfg *
+ ****************************/
+
+
+/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
+struct hwrm_error_recovery_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __attribute__((packed));
+
+/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
+struct hwrm_error_recovery_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When this flag is set to 1, error recovery will be initiated
+ * through master function driver.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
+ /*
+ * When this flag is set to 1, error recovery will be performed
+ * through Co processor.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
+ /*
+ * Driver Polling frequency. This value is in units of 100msec.
+ * Typical value would be 10 to indicate 1sec.
+ * Drivers can poll FW health status, Heartbeat, reset_counter with
+ * this frequency.
+ */
+ uint32_t driver_polling_freq;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 30 to indicate 3sec.
+ * Master function wait period from detecting a fatal error to
+ * initiating reset. In this time period Master PF expects every
+ * active driver will detect fatal error.
+ */
+ uint32_t master_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 50 to indicate 5sec.
+ * Normal function wait period from fatal error detection to
+ * polling FW health status. In this time period, drivers should not
+ * do any PCIe MMIO transaction and should not send any HWRM commands.
+ */
+ uint32_t normal_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 20 to indicate 2sec.
+ * This field indicates that, master function wait period after chip
+ * reset. After this time, master function should reinitialize with
+ * FW.
+ */
+ uint32_t master_func_wait_period_after_reset;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 60 to indicate 6sec.
+ * This field is applicable to both master and normal functions.
+ * Even after chip reset, if FW status not changed to ready,
+ * then all the functions can poll for this much time and bailout.
+ */
+ uint32_t max_bailout_time_after_reset;
+ /*
+ * FW health status register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates upper 30bits of the register address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_health_status_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
+ 2
+ /*
+ * FW HeartBeat register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_heartbeat_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
+ 2
+ /*
+ * FW reset counter.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_reset_cnt_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
+ 2
+ /*
+ * Reset Inprogress Register address for PFs.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_inprogress_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
+ 2
+ /* This field indicates the mask value for reset_inprogress_reg. */
+ uint32_t reset_inprogress_reg_mask;
+ uint8_t unused_0[3];
+ /*
+ * Array of registers and value count to reset the Chip
+ * Each array count has reset_reg, reset_reg_val, delay_after_reset
+ * in TLV format. Depending upon Chip type, number of reset registers
+ * will vary. Drivers have to write reset_reg_val in the reset_reg
+ * location in the same sequence in order to recover from a fatal
+ * error.
+ */
+ uint8_t reg_array_cnt;
+ /*
+ * Reset register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_reg[16];
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
+ /* Value to be written in reset_reg to reset the controller. */
+ uint32_t reset_reg_val[16];
+ /*
+ * This value is in units of 1msec.
+ * Typical value would be 10 to indicate 10msec.
+ * Some of the operations like Core reset require delay before
+ * accessing PCIE MMIO register space.
+ * If this value is non-zero, drivers have to wait for
+ * this much time after writing reset_reg_val in reset_reg.
+ */
+ uint8_t delay_after_reset[16];
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
@@ -10894,6 +11889,12 @@ struct hwrm_func_drv_if_change_output {
*/
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that the firmware got changed / reset.
+ * The driver should do complete re-initialization when that bit is set.
+ */
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
+ UINT32_C(0x2)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -14166,6 +15167,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for autonegotiation on this link.
@@ -14215,6 +15219,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for EEE on this link.
@@ -14281,13 +15288,13 @@ struct hwrm_port_phy_qcaps_output {
#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
} __attribute__((packed));
-/*********************
- * hwrm_port_led_cfg *
- *********************/
+/****************************
+ * hwrm_port_phy_mdio_write *
+ ****************************/
-/* hwrm_port_led_cfg_input (size:512b/64B) */
-struct hwrm_port_led_cfg_input {
+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
+struct hwrm_port_phy_mdio_write_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -14315,46 +15322,198 @@ struct hwrm_port_led_cfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ /*
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
+ */
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1[7];
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_write_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This bit must be '1' for the led0_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
- UINT32_C(0x1)
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_port_phy_mdio_read *
+ ***************************/
+
+
+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
+struct hwrm_port_phy_mdio_read_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This bit must be '1' for the led0_state field to be
- * configured.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
- UINT32_C(0x2)
+ uint16_t cmpl_ring;
/*
- * This bit must be '1' for the led0_color field to be
- * configured.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
- UINT32_C(0x4)
+ uint16_t seq_id;
/*
- * This bit must be '1' for the led0_blink_on field to be
- * configured.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
- UINT32_C(0x8)
+ uint16_t target_id;
/*
- * This bit must be '1' for the led0_blink_off field to be
- * configured.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
- UINT32_C(0x10)
+ uint64_t resp_addr;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
/*
- * This bit must be '1' for the led0_group_id field to be
- * configured.
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
- UINT32_C(0x20)
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1;
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_read_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ uint8_t unused_0[5];
/*
- * This bit must be '1' for the led1_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_led_cfg *
+ *********************/
+
+
+/* hwrm_port_led_cfg_input (size:512b/64B) */
+struct hwrm_port_led_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the led0_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the led0_state field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the led0_color field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the led0_blink_on field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the led0_blink_off field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the led0_group_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the led1_id field to be
+ * configured.
*/
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
UINT32_C(0x40)
@@ -20644,7 +21803,9 @@ struct hwrm_ring_reset_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t unused_0[4];
+ /* Position of consumer index after ring reset completes. */
+ uint8_t consumer_idx[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -21209,6 +22370,26 @@ struct hwrm_ring_grp_free_output {
*/
uint8_t valid;
} __attribute__((packed));
+/*
+ * special reserved flow ID to identify per function default
+ * flows for vSwitch offload
+ */
+#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
+/*
+ * special reserved flow ID to identify per function RoCEv1
+ * flows
+ */
+#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * flows
+ */
+#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * CNP flows
+ */
+#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
/****************************
* hwrm_cfa_l2_filter_alloc *
@@ -22968,6 +24149,13 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Setting of this flag indicates the applicability to the loopback path. */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
+ /*
+ * Setting of this flag indicates this encap record is external encap record.
+ * Resetting of this flag indicates this flag is internal encap record and
+ * this is the default setting.
+ */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
+ UINT32_C(0x2)
/* Encapsulation Type. */
uint8_t encap_type;
/* Virtual eXtensible Local Area Network (VXLAN) */
@@ -23003,8 +24191,11 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -23144,6 +24335,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
UINT32_C(0x4)
+ /*
+ * Setting of this flag indicates that the dest_id field contains function ID.
+ * If this is not set it indicates dest_id is VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x8)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
@@ -23605,7 +24802,13 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
UINT32_C(0x4)
- uint8_t unused_0[4];
+ uint32_t flags;
+ /*
+ * Setting this bit to 1 indicates that dest_id field contains FID.
+ * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x1)
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
@@ -24090,6 +25293,118 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/************************
+ * hwrm_cfa_meter_qcaps *
+ ************************/
+
+
+/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_meter_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
+struct hwrm_cfa_meter_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the clock at which the Meter is running with.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
+ /* 375 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
+ /* 625 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
+ HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
+ uint8_t unused_0[4];
+ /*
+ * The minimum guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_tx_profile;
+ /*
+ * The maximum non-guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_tx_profile;
+ /*
+ * The minimum guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_rx_profile;
+ /*
+ * The maximum non-guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_rx_profile;
+ /*
+ * The minimum guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t min_tx_instance;
+ /*
+ * The maximum non-guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t max_tx_instance;
+ /*
+ * The minimum guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t min_rx_instance;
+ /*
+ * The maximum non-guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t max_rx_instance;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/********************************
* hwrm_cfa_meter_profile_alloc *
********************************/
@@ -24200,11 +25515,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24243,7 +25558,7 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24286,11 +25601,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24564,11 +25879,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24607,7 +25922,7 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24650,11 +25965,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24775,7 +26090,7 @@ struct hwrm_cfa_meter_instance_alloc_input {
/* This value identifies a meter profile in CFA. */
uint16_t meter_profile_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* profile is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
@@ -24798,7 +26113,7 @@ struct hwrm_cfa_meter_instance_alloc_output {
/* This value identifies a meter instance in CFA. */
uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* instance is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
@@ -24816,13 +26131,13 @@ struct hwrm_cfa_meter_instance_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_meter_instance_free *
- ********************************/
+/*******************************
+ * hwrm_cfa_meter_instance_cfg *
+ *******************************/
-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
-struct hwrm_cfa_meter_instance_free_input {
+/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24856,31 +26171,39 @@ struct hwrm_cfa_meter_instance_free_input {
* This enumeration is used for resources that are similar for both
* TX and RX paths of the chip.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
uint8_t unused_0;
- /* This value identifies a meter instance in CFA. */
- uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
+ * This value identifies a new meter profile to be associated with
+ * the meter instance specified in this command.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xffff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[4];
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This value identifies the ID of a meter instance that needs to be updated with
+ * a new meter profile specified in this command.
+ */
+ uint16_t meter_instance_id;
+ uint8_t unused_1[2];
} __attribute__((packed));
-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
-struct hwrm_cfa_meter_instance_free_output {
+/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24900,13 +26223,13 @@ struct hwrm_cfa_meter_instance_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24934,22 +26257,106 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
/*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
UINT32_C(0x2)
/*
* This bit must be '1' for the src_macaddr field to be
@@ -25375,6 +26782,9 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
+ /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
+ UINT32_C(0x200)
/*
* Tx Flow: vf fid.
* Rx Flow: pf fid.
@@ -25430,6 +26840,13 @@ struct hwrm_cfa_flow_alloc_input {
/* If set to 1, flow aging is enabled for this flow. */
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
UINT32_C(0x800)
+ /*
+ * If set to 1 an attempt will be made to try to offload this flow to the
+ * most optimal flow table resource. If set to 0, the flow will be
+ * placed to the default flow table resource.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
+ UINT32_C(0x1000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -25569,7 +26986,8 @@ struct hwrm_cfa_flow_alloc_output {
uint32_t flow_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint32_t flow_counter_id;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25646,6 +27064,229 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_action_data (size:960b/120B) */
+struct hwrm_cfa_flow_action_data {
+ uint16_t action_flags;
+ /* Setting of this flag indicates accept action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* Setting of this flag indicates recycle action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /* Setting of this flag indicates drop action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* Setting of this flag indicates meter action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* Setting of this flag indicates tunnel action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /*
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header.
+ */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
+ UINT32_C(0x20)
+ /* Setting of this flag indicates ttl decrement action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
+ UINT32_C(0x40)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x80)
+ /* Setting of this flag indicates encap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
+ UINT32_C(0x100)
+ /* Setting of this flag indicates decap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
+ UINT32_C(0x200)
+ /* Meter id. */
+ uint16_t act_meter_id;
+ /* VNIC id. */
+ uint16_t vnic_id;
+ /* vport number. */
+ uint16_t vport_id;
+ /* The NAT source/destination. */
+ uint16_t nat_port;
+ uint16_t unused_0[3];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ /* Encapsulation Type. */
+ uint8_t encap_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
+ /* VLAN */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
+ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
+ uint8_t unused[7];
+ /* This value is encap data for the associated encap type. */
+ uint32_t encap_data[20];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
+struct hwrm_cfa_flow_tunnel_hdr_data {
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused[3];
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI).
+ */
+ uint32_t tunnel_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
+struct hwrm_cfa_flow_l4_key_data {
+ /* The value of source port. */
+ uint16_t l4_src_port;
+ /* The value of destination port. */
+ uint16_t l4_dst_port;
+ uint32_t unused;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
+struct hwrm_cfa_flow_l3_key_data {
+ /* The value of ip protocol. */
+ uint8_t ip_protocol;
+ uint8_t unused_0[7];
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ uint32_t unused[2];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
+struct hwrm_cfa_flow_l2_key_data {
+ /* Destination MAC address. */
+ uint16_t dmac[3];
+ uint16_t unused_0;
+ /* Source MAC address. */
+ uint16_t smac[3];
+ uint16_t unused_1;
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
+ uint16_t unused_2;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* Ethertype. */
+ uint16_t ethertype;
+ /* Number of VLAN tags. */
+ uint16_t num_vlan_tags;
+ /* VLAN tpid. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci. */
+ uint16_t l2_rewrite_vlan_tci;
+ uint8_t unused_3[2];
+ /* Outer VLAN TPID. */
+ uint16_t ovlan_tpid;
+ /* Outer VLAN TCI. */
+ uint16_t ovlan_tci;
+ /* Inner VLAN TPID. */
+ uint16_t ivlan_tpid;
+ /* Inner VLAN TCI. */
+ uint16_t ivlan_tci;
+ uint8_t unused[8];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_key_data (size:4160b/520B) */
+struct hwrm_cfa_flow_key_data {
+ /* Flow associated tunnel L2 header key info. */
+ uint32_t t_l2_key_data[14];
+ /* Flow associated tunnel L2 header mask info. */
+ uint32_t t_l2_key_mask[14];
+ /* Flow associated tunnel L3 header key info. */
+ uint32_t t_l3_key_data[16];
+ /* Flow associated tunnel L3 header mask info. */
+ uint32_t t_l3_key_mask[16];
+ /* Flow associated tunnel L4 header key info. */
+ uint32_t t_l4_key_data[2];
+ /* Flow associated tunnel L4 header mask info. */
+ uint32_t t_l4_key_mask[2];
+ /* Flow associated tunnel header info. */
+ uint32_t tunnel_hdr[2];
+ /* Flow associated L2 header key info. */
+ uint32_t l2_key_data[14];
+ /* Flow associated L2 header mask info. */
+ uint32_t l2_key_mask[14];
+ /* Flow associated L3 header key info. */
+ uint32_t l3_key_data[16];
+ /* Flow associated L3 header mask info. */
+ uint32_t l3_key_mask[16];
+ /* Flow associated L4 header key info. */
+ uint32_t l4_key_data[2];
+ /* Flow associated L4 header mask info. */
+ uint32_t l4_key_mask[2];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_info *
**********************/
@@ -25703,7 +27344,7 @@ struct hwrm_cfa_flow_info_input {
uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_info_output (size:448b/56B) */
+/* hwrm_cfa_flow_info_output (size:5632b/704B) */
struct hwrm_cfa_flow_info_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -25713,8 +27354,11 @@ struct hwrm_cfa_flow_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* flags is 8 b */
uint8_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
/* profile is 8 b */
uint8_t profile;
/* src_fid is 16 b */
@@ -25737,7 +27381,12 @@ struct hwrm_cfa_flow_info_output {
uint32_t tunnel_handle;
/* The flow aging timer for the flow, the unit is 100 milliseconds */
uint16_t flow_timer;
- uint8_t unused_0[5];
+ uint8_t unused_0[6];
+ /* Flow associated L2, L3 and L4 headers info. */
+ uint32_t flow_key_data[130];
+ /* Flow associated action record info. */
+ uint32_t flow_action_info[30];
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25753,7 +27402,7 @@ struct hwrm_cfa_flow_info_output {
***********************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+/* hwrm_cfa_flow_flush_input (size:256b/32B) */
struct hwrm_cfa_flow_flush_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -25782,8 +27431,73 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* flags is 32 b */
uint32_t flags;
- uint8_t unused_0[4];
+ /*
+ * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
+ * fields are valid. The flow flush operation should only flush the flows from the
+ * flow table specified. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
+ UINT32_C(0x1)
+ /*
+ * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
+ * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
+ UINT32_C(0x2)
+ /*
+ * This specifies the size of flow handle entries provided by the driver
+ * in the flow table specified below. Only two flow handle size enums are defined.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
+ UINT32_C(0xc0000000)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
+ 30
+ /* The flow handle is 16bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
+ (UINT32_C(0x0) << 30)
+ /* The flow handle is 64bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
+ /* Specify page size of the flow table memory. */
+ uint8_t page_size;
+ /* The page size is 4K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* The page size is 8K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* The page size is 64K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* The page size is 256K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* The page size is 1M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* The page size is 2M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* The page size is 4M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* The page size is 1G */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
+ /* FLow table memory indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
+ /* number of flows in the flow table */
+ uint16_t num_flows;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
} __attribute__((packed));
/* hwrm_cfa_flow_flush_output (size:128b/16B) */
@@ -25983,7 +27697,12 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint8_t unused_0[2];
+ /*
+ * New flow timer value for the flow specified in the ext_flow_handle.
+ * The flow timer unit is 100ms.
+ */
+ uint32_t flow_timer;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -26244,13 +27963,13 @@ struct hwrm_cfa_flow_aging_qcaps_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_pair_info *
- **********************/
+/**********************************
+ * hwrm_cfa_tcp_flag_process_qcfg *
+ **********************************/
-/* hwrm_cfa_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_pair_info_input {
+/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26278,23 +27997,10 @@ struct hwrm_cfa_pair_info_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* If this flag is set, lookup by name else lookup by index. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
- /* If this flag is set, lookup by PF id and VF id. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
- /* Pair table index. */
- uint16_t pair_index;
- /* Pair pf index. */
- uint8_t pair_pfid;
- /* Pair vf index. */
- uint8_t pair_vfid;
- /* Pair name (32 byte string). */
- char pair_name[32];
} __attribute__((packed));
-/* hwrm_cfa_pair_info_output (size:576b/72B) */
-struct hwrm_cfa_pair_info_output {
+/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26303,22 +28009,100 @@ struct hwrm_cfa_pair_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Pair table index. */
- uint16_t next_pair_index;
- /* Pair member a's fid. */
- uint16_t a_fid;
- /* Logical host number. */
- uint8_t host_a_index;
- /* Logical PF number. */
- uint8_t pf_a_index;
- /* Pair member a's Linux logical VF number. */
- uint16_t vf_a_index;
- /* Rx CFA code. */
- uint16_t rx_cfa_code_a;
- /* Tx CFA action. */
- uint16_t tx_cfa_action_a;
- /* Pair member b's fid. */
- uint16_t b_fid;
+ /* The port 0 RX mirror action record ID. */
+ uint16_t rx_ar_id_port0;
+ /* The port 1 RX mirror action record ID. */
+ uint16_t rx_ar_id_port1;
+ /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port0;
+ /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port1;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_pair_info *
+ **********************/
+
+
+/* hwrm_cfa_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_pair_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If this flag is set, lookup by name else lookup by index. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
+ /* If this flag is set, lookup by PF id and VF id. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
+ /* Pair table index. */
+ uint16_t pair_index;
+ /* Pair pf index. */
+ uint8_t pair_pfid;
+ /* Pair vf index. */
+ uint8_t pair_vfid;
+ /* Pair name (32 byte string). */
+ char pair_name[32];
+} __attribute__((packed));
+
+/* hwrm_cfa_pair_info_output (size:576b/72B) */
+struct hwrm_cfa_pair_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pair table index. */
+ uint16_t next_pair_index;
+ /* Pair member a's fid. */
+ uint16_t a_fid;
+ /* Logical host number. */
+ uint8_t host_a_index;
+ /* Logical PF number. */
+ uint8_t pf_a_index;
+ /* Pair member a's Linux logical VF number. */
+ uint16_t vf_a_index;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code_a;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action_a;
+ /* Pair member b's fid. */
+ uint16_t b_fid;
/* Logical host number. */
uint8_t host_b_index;
/* Logical PF number. */
@@ -26364,13 +28148,645 @@ struct hwrm_cfa_pair_info_output {
uint8_t valid;
} __attribute__((packed));
-/***************************************
- * hwrm_cfa_redirect_query_tunnel_type *
- ***************************************/
+/***************************************
+ * hwrm_cfa_redirect_query_tunnel_type *
+ ***************************************/
+
+
+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
+struct hwrm_cfa_redirect_query_tunnel_type_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The source function id. */
+ uint16_t src_fid;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
+struct hwrm_cfa_redirect_query_tunnel_type_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Tunnel Mask. */
+ uint32_t tunnel_mask;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ UINT32_C(0x1)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ UINT32_C(0x2)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ UINT32_C(0x4)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ UINT32_C(0x8)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ UINT32_C(0x10)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ UINT32_C(0x20)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ UINT32_C(0x40)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
+ UINT32_C(0x80)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
+ UINT32_C(0x100)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
+ UINT32_C(0x200)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
+ UINT32_C(0x400)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
+ UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_rgtr *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_rgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
+ uint32_t unused_0;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_rgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_cfa_ctx_mem_unrgtr *
+ ***************************/
+
+
+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_unrgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_unrgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_qctx *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_qctx_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_qctx_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
+ uint8_t unused_0[4];
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**************************
+ * hwrm_cfa_ctx_mem_qcaps *
+ **************************/
+
+
+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Indicates the maximum number of context memory which can be registered. */
+ uint16_t max_entries;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_eem_qcaps *
+ **********************/
+
+
+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_eem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
+ uint32_t supported;
+ /*
+ * If set to 1, then EEM KEY0 table is supported using crc32 hash.
+ * If set to 0 EEM KEY0 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
+ * If set to 0 EEM KEY1 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, then EEM External Record table is supported.
+ * If set to 0 EEM External Record table is not supported.
+ * (This table includes action record, EFC pointers, encap pointers)
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, then EEM External Flow Counters table is supported.
+ * If set to 0 EEM External Flow Counters table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+ UINT32_C(0x8)
+ /*
+ * The maximum number of entries supported by EEM. When configuring the host memory
+ * the number of numbers of entries that can supported are -
+ * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
+ * Any value that are not these values, the FW will round down to the closest support
+ * number of entries.
+ */
+ uint32_t max_entries_supported;
+ /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
+ uint16_t key_entry_size;
+ /* The entry size in bytes of each entry in the RECORD EEM tables. */
+ uint16_t record_entry_size;
+ /* The entry size in bytes of each entry in the EFC EEM tables. */
+ uint16_t efc_entry_size;
+ uint8_t unused_1;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************
+ * hwrm_cfa_eem_cfg *
+ ********************/
+
+
+/* hwrm_cfa_eem_cfg_input (size:320b/40B) */
+struct hwrm_cfa_eem_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+ /*
+ * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
+ * RECORD, EFC all have the same number of entries and all tables will be configured
+ * using this value. Current minimum value is 32k. Current maximum value is 128M.
+ */
+ uint32_t num_entries;
+ uint32_t unused_1;
+ /* Configured EEM with the given context if for KEY0 table. */
+ uint16_t key0_ctx_id;
+ /* Configured EEM with the given context if for KEY1 table. */
+ uint16_t key1_ctx_id;
+ /* Configured EEM with the given context if for RECORD table. */
+ uint16_t record_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t efc_ctx_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
+struct hwrm_cfa_eem_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_cfa_eem_qcfg *
+ *********************/
-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
-struct hwrm_cfa_redirect_query_tunnel_type_input {
+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26398,13 +28814,16 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The source function id. */
- uint16_t src_fid;
- uint8_t unused_0[6];
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
} __attribute__((packed));
-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
-struct hwrm_cfa_redirect_query_tunnel_type_output {
+/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26413,50 +28832,219 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Tunnel Mask. */
- uint32_t tunnel_mask;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
UINT32_C(0x1)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
UINT32_C(0x2)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ /* The number of entries the FW has configured for EEM. */
+ uint32_t num_entries;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************
+ * hwrm_cfa_eem_op *
+ *******************/
+
+
+/* hwrm_cfa_eem_op_input (size:192b/24B) */
+struct hwrm_cfa_eem_op_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the TX flow offload function specified in fid.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the RX flow offload function specified in fid.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint16_t unused_0;
+ /* The number of EEM key table entries to be configured. */
+ uint16_t op;
+ /* This value is reserved and should not be used. */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
+ /*
+ * To properly stop EEM and ensure there are no DMA's, the caller
+ * must disable EEM for the given PF, using this call. This will
+ * safely disable EEM and ensure that all DMA'ed to the
+ * keys/records/efc have been completed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
+ /*
+ * Once the EEM host memory has been configured, EEM options have
+ * been configured. Then the caller should enable EEM for the given
+ * PF. Note once this call has been made, then the EEM mechanism
+ * will be active and DMA's will occur as packets are processed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
+ /*
+ * Clear EEM settings for the given PF so that the register values
+ * are reset back to there initial state.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
+ #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
+ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_op_output (size:128b/16B) */
+struct hwrm_cfa_eem_op_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_adv_flow_mgnt_qcaps *
+ ********************************/
+
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Value of 1 to indicate firmware support 16-bit flow handle.
+ * Value of 0 to indicate firmware not support 16-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate firmware support 64-bit flow handle.
+ * Value of 0 to indicate firmware not support 64-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * Value of 1 to indicate firmware support flow batch delete operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 to indicate that the firmware does not support flow batch delete
+ * operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * Value of 1 to indicate that the firmware support flow reset all operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 indicates firmware does not support flow reset all operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
UINT32_C(0x8)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ /*
+ * Value of 1 to indicate that firmware supports use of FID as dest_id in
+ * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
+ * Value of 0 indicates firmware does not support use of FID as dest_id.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
UINT32_C(0x10)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ /*
+ * Value of 1 to indicate that firmware supports TX EEM flows.
+ * Value of 0 indicates firmware does not support TX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
UINT32_C(0x20)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ /*
+ * Value of 1 to indicate that firmware supports RX EEM flows.
+ * Value of 0 indicates firmware does not support RX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
- UINT32_C(0x80)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
- UINT32_C(0x100)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
- UINT32_C(0x200)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
- UINT32_C(0x400)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
- UINT32_C(0x800)
- /* Use fixed layer 2 ether type of 0xFFFF */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
- UINT32_C(0x1000)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
- UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -26874,7 +29462,11 @@ struct hwrm_stat_ctx_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This is the address for statistic block. */
+ /*
+ * This is the address for statistic block.
+ * > For new versions of the chip, this address should be 128B
+ * > aligned.
+ */
uint64_t stats_dma_addr;
/*
* The statistic block update period in ms.
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v2 09/10] net/bnxt: HWRM version update
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (7 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 08/10] net/bnxt: update HWRM version Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-28 9:12 ` Ferruh Yigit
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 10/10] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-28 9:19 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Ferruh Yigit
10 siblings, 1 reply; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.74
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
---
drivers/net/bnxt/hsi_struct_def_dpdk.h | 1399 ++++++++++++++++++++----
1 file changed, 1168 insertions(+), 231 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 00a8ff87e..305ee09bc 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2019 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -27,7 +27,8 @@ struct hwrm_cmd_hdr {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -221,8 +222,14 @@ struct hwrm_short_input {
#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
#define HWRM_SHORT_INPUT_SIGNATURE_LAST \
HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
- /* Reserved for future use. */
- uint16_t unused_0;
+ /* The target ID of the command */
+ uint16_t target_id;
+ /* Default target_id (0x0) to maintain compatibility with old driver */
+ #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
+ /* Reserved for user-space HWRM interface */
+ #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
+ #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
+ HWRM_SHORT_INPUT_TARGET_ID_TOOLS
/* This value indicates the length of the request. */
uint16_t size;
/*
@@ -394,6 +401,8 @@ struct cmd_nums {
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
#define HWRM_OEM_CMD UINT32_C(0xd4)
+ /* Tells the fw to run PRBS test on a given port and lane. */
+ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
@@ -486,6 +495,8 @@ struct cmd_nums {
#define HWRM_CFA_EEM_OP UINT32_C(0x123)
/* Experimental */
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
+ /* Experimental */
+ #define HWRM_CFA_TFLIB UINT32_C(0x125)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -506,6 +517,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
/* Engine CKV - Configure a label index with a label value. */
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
+ /* Engine CKV - Query a label */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -587,6 +600,19 @@ struct cmd_nums {
/* Experimental */
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
/* Experimental */
+ #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
+ /* Returns the current value of a free running counter from the device. */
+ #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
+ /* Experimental */
+ #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
+ /* Experimental */
+ #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
+ /*
+ * Tells the fw to run the DMA read from the host and DMA write
+ * to the host test.
+ */
+ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
+ /* Experimental */
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
/* Experimental */
#define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
@@ -643,67 +669,85 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
/*
* This error code is only reported by firmware when the specific
* request is not able to process when the HOT reset in progress.
*/
- #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
/*
* This error code is only reported by firmware when the registered
* driver instances are not capable of hot reset.
*/
- #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ /*
+ * This error code is only reported by the firmware when during
+ * flow allocation when a requeest for a flow counter fails because
+ * the number of flow counters are exhausted.
+ */
+ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the requested key's hash collides with the installed keys.
+ */
+ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the same key has already been installed.
+ */
+ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
@@ -711,11 +755,11 @@ struct ret_codes {
* by itself, just an indicatation that the response should be parsed
* as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
*/
- #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -774,12 +818,25 @@ struct hwrm_err_output {
#define HW_HASH_KEY_SIZE 40
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
+/* Reserved for BONO processor */
+#define HWRM_TARGET_ID_BONO 0xFFF8
+/* Reserved for KONG processor */
+#define HWRM_TARGET_ID_KONG 0xFFF9
+/* Reserved for APE processor */
+#define HWRM_TARGET_ID_APE 0xFFFA
+/*
+ * This value will be used by tools for User-space HWRM Interface.
+ * When tool execute any HWRM command with this target_id, firmware
+ * will copy the response and/or data payload via register space instead
+ * of DMAing it.
+ */
+#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 48
-#define HWRM_VERSION_STR "1.10.0.48"
+#define HWRM_VERSION_RSVD 74
+#define HWRM_VERSION_STR "1.10.0.74"
/****************
* hwrm_ver_get *
@@ -804,7 +861,8 @@ struct hwrm_ver_get_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -1062,6 +1120,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
UINT32_C(0x1000)
+ /*
+ * If set to 1, the firmware is able to support TFLIB features.
+ * If set to 0, then the firmware doesn’t support TFLIB features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
+ UINT32_C(0x2000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -1099,12 +1164,8 @@ struct hwrm_ver_get_output {
* firmware (ASCII chars with NULL at the end).
*/
char netctrl_fw_name[16];
- /*
- * This field is reserved for future use.
- * The responder should set it to 0.
- * The requester should ignore this field.
- */
- uint8_t reserved2[16];
+ /* This field represents the active board package name. */
+ char active_pkg_name[16];
/*
* This field represents the name of RoCE FW (ASCII chars
* with NULL at the end).
@@ -3845,6 +3906,12 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
UINT32_C(0x3c)
+ /* TFLIB unique default VNIC Configuration Change */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
+ UINT32_C(0x3d)
+ /* TFLIB unique link status changed */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
+ UINT32_C(0x3e)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -5859,7 +5926,8 @@ struct hwrm_func_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -5962,7 +6030,8 @@ struct hwrm_func_getfid_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6038,7 +6107,8 @@ struct hwrm_func_vf_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6110,7 +6180,8 @@ struct hwrm_func_vf_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6183,7 +6254,8 @@ struct hwrm_func_vf_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6446,7 +6518,8 @@ struct hwrm_func_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6663,6 +6736,13 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
UINT32_C(0x800000)
+ /*
+ * If the query is for a VF, then this flag shall be ignored.
+ * If this query is for a PF and this flag is set to 1, then
+ * the PF has the capability to support extended stats.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
+ UINT32_C(0x1000000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6807,7 +6887,8 @@ struct hwrm_func_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7247,7 +7328,8 @@ struct hwrm_func_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7889,7 +7971,8 @@ struct hwrm_func_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8014,7 +8097,8 @@ struct hwrm_func_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8078,7 +8162,8 @@ struct hwrm_func_vf_resc_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8141,7 +8226,8 @@ struct hwrm_func_drv_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8382,7 +8468,8 @@ struct hwrm_func_drv_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8447,7 +8534,8 @@ struct hwrm_func_buf_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8581,7 +8669,8 @@ struct hwrm_func_buf_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8650,7 +8739,8 @@ struct hwrm_func_drv_qver_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8757,7 +8847,8 @@ struct hwrm_func_resource_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8886,7 +8977,8 @@ struct hwrm_func_backing_store_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8973,7 +9065,10 @@ struct hwrm_func_backing_store_qcaps_output {
* the backing store.
*/
uint32_t tqm_max_entries_per_ring;
- /* Maximum number of MR/AV context entries supported for this function. */
+ /*
+ * Maximum number of MR plus AV context entries supported for this
+ * function.
+ */
uint32_t mrav_max_entries;
/* Number of bytes that must be allocated for each context entry. */
uint16_t mrav_entry_size;
@@ -8981,7 +9076,22 @@ struct hwrm_func_backing_store_qcaps_output {
uint16_t tim_entry_size;
/* Maximum number of Timer context entries supported for this function. */
uint32_t tim_max_entries;
- uint8_t unused_0[2];
+ /*
+ * When this field is zero, the 32b `mrav_num_entries` field in the
+ * `backing_store_cfg` and `backing_store_qcfg` commands represents
+ * the total number of MR plus AV entries allowed in the MR/AV backing
+ * store PBL.
+ *
+ * When this field is non-zero, the 32b `mrav_num_entries` field in
+ * the `backing_store_cfg` and `backing_store_qcfg` commands is
+ * logically divided into two 16b fields. Bits `[31:16]` represents
+ * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
+ * Both of these values are represented in a unit granularity
+ * specified by this field. For example, if this field is 16 and
+ * `mrav_num_entries` is `0x02000100`, then the number of MR entries
+ * is 8192 and the number of AV entries is 4096.
+ */
+ uint16_t mrav_num_entries_units;
/*
* The number of entries specified for any TQM ring must be a
* multiple of this value to prevent any resource allocation
@@ -9021,7 +9131,8 @@ struct hwrm_func_backing_store_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -9041,6 +9152,12 @@ struct hwrm_func_backing_store_cfg_input {
*/
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint32_t enables;
/*
* This bit must be '1' for the qp fields to be
@@ -9958,7 +10075,20 @@ struct hwrm_func_backing_store_cfg_input {
* the backing store.
*/
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10036,7 +10166,8 @@ struct hwrm_func_backing_store_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -10068,6 +10199,12 @@ struct hwrm_func_backing_store_qcfg_output {
*/
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint8_t unused_0[4];
/*
* This bit must be '1' for the qp fields to be
@@ -10891,7 +11028,20 @@ struct hwrm_func_backing_store_qcfg_output {
uint32_t tqm_ring6_num_entries;
/* Number of TQM ring 7 entries. */
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10930,7 +11080,8 @@ struct hwrm_error_recovery_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11296,7 +11447,8 @@ struct hwrm_func_vlan_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11386,7 +11538,8 @@ struct hwrm_func_vlan_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11507,7 +11660,8 @@ struct hwrm_func_vf_vnic_ids_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11580,7 +11734,8 @@ struct hwrm_func_vf_bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11704,7 +11859,8 @@ struct hwrm_func_vf_bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11841,7 +11997,8 @@ struct hwrm_func_drv_if_change_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11929,7 +12086,8 @@ struct hwrm_port_phy_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -12520,7 +12678,8 @@ struct hwrm_port_phy_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13389,7 +13548,7 @@ struct hwrm_port_phy_qcfg_output {
*********************/
-/* hwrm_port_mac_cfg_input (size:320b/40B) */
+/* hwrm_port_mac_cfg_input (size:384b/48B) */
struct hwrm_port_mac_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13407,7 +13566,8 @@ struct hwrm_port_mac_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13527,6 +13687,13 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
UINT32_C(0x1000)
+ /*
+ * When this bit is set to '1', and the ptp_tx_ts_capture_enable
+ * bit is set, then the device uses one step Tx timestamping.
+ * This bit is temporary and used for experimental purposes.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
+ UINT32_C(0x2000)
uint32_t enables;
/*
* This bit must be '1' for the ipg field to be
@@ -13576,6 +13743,12 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ppb field to be
+ * configured.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
+ UINT32_C(0x200)
/* Port ID of port that is to be configured. */
uint16_t port_id;
/*
@@ -13763,6 +13936,12 @@ struct hwrm_port_mac_cfg_input {
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
5
uint8_t unused_0[3];
+ /*
+ * This signed field specifies by how much to adjust the frequency
+ * of sync timer updates (measured in parts per billion).
+ */
+ int32_t ptp_freq_adj_ppb;
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_port_mac_cfg_output (size:128b/16B) */
@@ -13842,7 +14021,8 @@ struct hwrm_port_mac_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14131,7 +14311,8 @@ struct hwrm_port_mac_ptp_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14174,6 +14355,12 @@ struct hwrm_port_mac_ptp_qcfg_output {
*/
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', the device supports one-step
+ * Tx timestamping.
+ */
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
+ UINT32_C(0x4)
uint8_t unused_0[3];
/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
uint32_t rx_ts_reg_off_lower;
@@ -14595,7 +14782,8 @@ struct hwrm_port_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14716,7 +14904,7 @@ struct tx_port_stats_ext {
} __attribute__((packed));
/* Port Rx Statistics extended Formats */
-/* rx_port_stats_ext (size:2368b/296B) */
+/* rx_port_stats_ext (size:3648b/456B) */
struct rx_port_stats_ext {
/* Number of times link state changed to down */
uint64_t link_down_events;
@@ -14792,6 +14980,49 @@ struct rx_port_stats_ext {
uint64_t pfc_pri7_rx_duration_us;
/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
uint64_t pfc_pri7_rx_transitions;
+ /* Total number of received bits */
+ uint64_t rx_bits;
+ /* The number of events where the port receive buffer was over 85% full */
+ uint64_t rx_buffer_passed_threshold;
+ /*
+ * The number of symbol errors that wasn't corrected by FEC correction
+ * alogirithm
+ */
+ uint64_t rx_pcs_symbol_err;
+ /* The number of corrected bits on the port according to active FEC */
+ uint64_t rx_corrected_bits;
+ /* Total number of rx discard bytes count on cos queue 0 */
+ uint64_t rx_discard_bytes_cos0;
+ /* Total number of rx discard bytes count on cos queue 1 */
+ uint64_t rx_discard_bytes_cos1;
+ /* Total number of rx discard bytes count on cos queue 2 */
+ uint64_t rx_discard_bytes_cos2;
+ /* Total number of rx discard bytes count on cos queue 3 */
+ uint64_t rx_discard_bytes_cos3;
+ /* Total number of rx discard bytes count on cos queue 4 */
+ uint64_t rx_discard_bytes_cos4;
+ /* Total number of rx discard bytes count on cos queue 5 */
+ uint64_t rx_discard_bytes_cos5;
+ /* Total number of rx discard bytes count on cos queue 6 */
+ uint64_t rx_discard_bytes_cos6;
+ /* Total number of rx discard bytes count on cos queue 7 */
+ uint64_t rx_discard_bytes_cos7;
+ /* Total number of rx discard packets count on cos queue 0 */
+ uint64_t rx_discard_packets_cos0;
+ /* Total number of rx discard packets count on cos queue 1 */
+ uint64_t rx_discard_packets_cos1;
+ /* Total number of rx discard packets count on cos queue 2 */
+ uint64_t rx_discard_packets_cos2;
+ /* Total number of rx discard packets count on cos queue 3 */
+ uint64_t rx_discard_packets_cos3;
+ /* Total number of rx discard packets count on cos queue 4 */
+ uint64_t rx_discard_packets_cos4;
+ /* Total number of rx discard packets count on cos queue 5 */
+ uint64_t rx_discard_packets_cos5;
+ /* Total number of rx discard packets count on cos queue 6 */
+ uint64_t rx_discard_packets_cos6;
+ /* Total number of rx discard packets count on cos queue 7 */
+ uint64_t rx_discard_packets_cos7;
} __attribute__((packed));
/************************
@@ -14817,7 +15048,8 @@ struct hwrm_port_qstats_ext_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14909,7 +15141,8 @@ struct hwrm_port_lpbk_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14986,7 +15219,8 @@ struct hwrm_port_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15057,7 +15291,8 @@ struct hwrm_port_phy_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15311,7 +15546,8 @@ struct hwrm_port_phy_mdio_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15387,7 +15623,8 @@ struct hwrm_port_phy_mdio_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15463,7 +15700,8 @@ struct hwrm_port_led_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15886,7 +16124,8 @@ struct hwrm_port_led_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16191,7 +16430,8 @@ struct hwrm_port_led_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16519,6 +16759,137 @@ struct hwrm_port_led_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/***********************
+ * hwrm_port_prbs_test *
+ ***********************/
+
+
+/* hwrm_port_prbs_test_input (size:384b/48B) */
+struct hwrm_port_prbs_test_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Host address data is to DMA'd to. */
+ uint64_t resp_data_addr;
+ /*
+ * Size of the buffer pointed to by resp_data_addr. The firmware may
+ * use this entire buffer or less than the entire buffer, but never more.
+ */
+ uint16_t data_len;
+ uint16_t unused_0;
+ uint32_t unused_1;
+ /* Port ID of port where PRBS test to be run. */
+ uint16_t port_id;
+ /* Polynomial selection for PRBS test. */
+ uint16_t poly;
+ /* PRBS7 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
+ /* PRBS9 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
+ /* PRBS11 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
+ /* PRBS15 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
+ /* PRBS23 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
+ /* PRBS31 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
+ /* PRBS58 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* Invalid */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
+ HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
+ /*
+ * Configuration bits for PRBS test.
+ * Use enable bit to start/stop test.
+ * Use tx/rx lane map bits to run test on specific lanes,
+ * if set to 0 test will be run on all lanes.
+ */
+ uint16_t prbs_config;
+ /*
+ * Set 0 to stop test currently in progress
+ * Set 1 to start test with configuration provided.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, tx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, rx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
+ UINT32_C(0x4)
+ /* Duration in seconds to run the PRBS test. */
+ uint16_t timeout;
+ /*
+ * If tx_lane_map_valid is set to 1, this field is a bitmap
+ * of tx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t tx_lane_map;
+ /*
+ * If rx_lane_map_valid is set to 1, this field is a bitmap
+ * of rx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t rx_lane_map;
+} __attribute__((packed));
+
+/* hwrm_port_prbs_test_output (size:128b/16B) */
+struct hwrm_port_prbs_test_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -16542,7 +16913,8 @@ struct hwrm_queue_qportcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16994,7 +17366,8 @@ struct hwrm_queue_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17091,7 +17464,8 @@ struct hwrm_queue_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17194,7 +17568,8 @@ struct hwrm_queue_pfcenable_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17283,7 +17658,8 @@ struct hwrm_queue_pfcenable_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17372,7 +17748,8 @@ struct hwrm_queue_pri2cos_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17522,7 +17899,8 @@ struct hwrm_queue_pri2cos_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17698,7 +18076,8 @@ struct hwrm_queue_cos2bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -18740,7 +19119,8 @@ struct hwrm_queue_cos2bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19831,7 +20211,8 @@ struct hwrm_vnic_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19897,7 +20278,8 @@ struct hwrm_vnic_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19957,7 +20339,8 @@ struct hwrm_vnic_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20172,7 +20555,8 @@ struct hwrm_vnic_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20327,7 +20711,8 @@ struct hwrm_vnic_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20419,7 +20804,13 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
UINT32_C(0x80)
- uint8_t unused_1[7];
+ /*
+ * This field advertises the maximum concurrent TPA aggregations
+ * supported by the VNIC on new devices that support TPA v2.
+ * '0' means that TPA v2 is not supported.
+ */
+ uint16_t max_aggs_supported;
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -20453,7 +20844,8 @@ struct hwrm_vnic_tpa_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20529,6 +20921,15 @@ struct hwrm_vnic_tpa_cfg_input {
*/
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
UINT32_C(0x80)
+ /*
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall DMA payload data using GRO rules.
+ * When this bit is '0', the VNIC shall DMA payload data
+ * using the more efficient LRO rules of filling all
+ * aggregation buffers.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
+ UINT32_C(0x100)
uint32_t enables;
/*
* This bit must be '1' for the max_agg_segs field to be
@@ -20545,16 +20946,15 @@ struct hwrm_vnic_tpa_cfg_input {
* configured.
*/
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
- /*
- * This bit must be '1' for the min_agg_len field to be
- * configured.
- */
+ /* deprecated bit. Do not use!!! */
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
/* Logical vnic ID */
uint16_t vnic_id;
/*
* This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31.
+ * be aggregated (unit is Log2). Max value is 31. On new
+ * devices supporting TPA v2, the unit is multiples of 4 and
+ * valid values are > 0 and <= 63.
*/
uint16_t max_agg_segs;
/* 1 segment */
@@ -20571,7 +20971,10 @@ struct hwrm_vnic_tpa_cfg_input {
HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
/*
* This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7
+ * allowed (unit is Log2). Max value is 7. On new devices
+ * supporting TPA v2, this is in unit of 1 and must be > 0
+ * and <= max_aggs_supported in the hwrm_vnic_qcaps response
+ * to enable TPA v2.
*/
uint16_t max_aggs;
/* 1 aggregation */
@@ -20596,7 +20999,9 @@ struct hwrm_vnic_tpa_cfg_input {
uint32_t max_agg_timer;
/*
* This is the minimum amount of payload length required to
- * start an aggregation context.
+ * start an aggregation context. This field is deprecated and
+ * should be set to 0. The minimum length is set by firmware
+ * and can be queried using hwrm_vnic_tpa_qcfg.
*/
uint32_t min_agg_len;
} __attribute__((packed));
@@ -20645,7 +21050,8 @@ struct hwrm_vnic_rss_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20795,7 +21201,8 @@ struct hwrm_vnic_rss_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20937,7 +21344,8 @@ struct hwrm_vnic_plcmodes_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21100,7 +21508,8 @@ struct hwrm_vnic_plcmodes_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21228,7 +21637,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21287,7 +21697,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21347,7 +21758,8 @@ struct hwrm_ring_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21687,7 +22099,8 @@ struct hwrm_ring_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21764,7 +22177,8 @@ struct hwrm_ring_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21839,7 +22253,8 @@ struct hwrm_ring_aggint_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21988,7 +22403,8 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22094,7 +22510,8 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22250,7 +22667,8 @@ struct hwrm_ring_grp_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22334,7 +22752,8 @@ struct hwrm_ring_grp_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22414,7 +22833,8 @@ struct hwrm_cfa_l2_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22476,6 +22896,22 @@ struct hwrm_cfa_l2_filter_alloc_input {
(UINT32_C(0x2) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
+ /*
+ * Setting of this flag indicates that no XDP filter is created with
+ * L2 filter.
+ * 0 - legacy behavior, XDP filter is created with L2 filter
+ * 1 - XDP filter won't be created with L2 filter
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
+ UINT32_C(0x40)
+ /*
+ * Setting this flag to 1 indicate the L2 fields in this command
+ * pertain to source fields. Setting this flag to 0 indicate the
+ * L2 fields in this command pertain to the destination fields
+ * and this is the default/legacy behavior.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
+ UINT32_C(0x80)
uint32_t enables;
/*
* This bit must be '1' for the l2_addr field to be
@@ -22579,13 +23015,31 @@ struct hwrm_cfa_l2_filter_alloc_input {
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
+ UINT32_C(0x20000)
+ /*
+ * This bit must be '1' for the t_num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
+ UINT32_C(0x40000)
/*
* This value sets the match value for the L2 MAC address.
* Destination MAC address for RX path.
* Source MAC address for TX path.
*/
uint8_t l2_addr[6];
- uint8_t unused_0[2];
+ /* This value sets the match value for the number of VLANs. */
+ uint8_t num_vlans;
+ /*
+ * This value sets the match value for the number of VLANs
+ * in the tunnel headers.
+ */
+ uint8_t t_num_vlans;
/*
* This value sets the mask value for the L2 address.
* A value of 0 will mask the corresponding bit from
@@ -22784,13 +23238,45 @@ struct hwrm_cfa_l2_filter_alloc_output {
*/
uint64_t l2_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -22825,7 +23311,8 @@ struct hwrm_cfa_l2_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22887,7 +23374,8 @@ struct hwrm_cfa_l2_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23014,7 +23502,8 @@ struct hwrm_cfa_l2_set_rx_mask_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23213,7 +23702,8 @@ struct hwrm_cfa_vlan_antispoof_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23287,7 +23777,8 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23366,7 +23857,8 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23602,13 +24094,45 @@ struct hwrm_cfa_tunnel_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t tunnel_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -23643,7 +24167,8 @@ struct hwrm_cfa_tunnel_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23702,7 +24227,8 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23813,7 +24339,8 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23919,7 +24446,8 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24134,7 +24662,8 @@ struct hwrm_cfa_encap_record_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24247,7 +24776,8 @@ struct hwrm_cfa_encap_record_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24289,7 +24819,7 @@ struct hwrm_cfa_encap_record_free_output {
********************************/
-/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
+/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
struct hwrm_cfa_ntuple_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -24307,7 +24837,8 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24456,6 +24987,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
UINT32_C(0x40000)
+ /*
+ * This bit must be '1' for the rfs_ring_tbl_idx field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
+ UINT32_C(0x80000)
/*
* This value identifies a set of CFA data structures used for an L2
* context.
@@ -24639,6 +25176,13 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
* the pri_hint.
*/
uint64_t ntuple_filter_id_hint;
+ /*
+ * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
+ * This index is used in lieu of the RSS hash when selecting the
+ * index into the RSS table to determine the rx ring.
+ */
+ uint16_t rfs_ring_tbl_idx;
+ uint8_t unused_0[6];
} __attribute__((packed));
/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
@@ -24654,13 +25198,45 @@ struct hwrm_cfa_ntuple_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24713,7 +25289,8 @@ struct hwrm_cfa_ntuple_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24772,7 +25349,8 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24884,7 +25462,8 @@ struct hwrm_cfa_em_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25216,13 +25795,45 @@ struct hwrm_cfa_em_flow_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t em_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -25257,7 +25868,8 @@ struct hwrm_cfa_em_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25316,7 +25928,8 @@ struct hwrm_cfa_meter_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25428,7 +26041,8 @@ struct hwrm_cfa_meter_profile_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25705,7 +26319,8 @@ struct hwrm_cfa_meter_profile_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25789,7 +26404,8 @@ struct hwrm_cfa_meter_profile_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26059,7 +26675,8 @@ struct hwrm_cfa_meter_instance_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26154,7 +26771,8 @@ struct hwrm_cfa_meter_instance_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26246,7 +26864,8 @@ struct hwrm_cfa_meter_instance_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26330,7 +26949,8 @@ struct hwrm_cfa_decap_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26654,7 +27274,8 @@ struct hwrm_cfa_decap_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26714,7 +27335,8 @@ struct hwrm_cfa_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26847,6 +27469,15 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
UINT32_C(0x1000)
+ /*
+ * If set to 1 there will be no attempt to allocate an on-chip try to
+ * offload this flow. If set to 0, which will keep compatibility with the
+ * older drivers, will cause the FW to attempt to allocate an on-chip flow
+ * counter for the newly created flow. This will keep the existing behavior
+ * with EM flows which always had an associated flow counter.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
+ UINT32_C(0x2000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -26977,13 +27608,45 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t flow_handle;
uint8_t unused_0[2];
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
uint32_t flow_counter_id;
@@ -26998,6 +27661,34 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
+struct hwrm_cfa_flow_alloc_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* No more L2 Context TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
+ /* No more action records */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
+ /* No more flow counters */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
+ /* No more wild-card TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
+ /* Hash collsion in exact match tables */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
+ /* Key is already installed */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
+ /* Flow Context DB is out of resource */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
+ HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_free *
**********************/
@@ -27021,7 +27712,8 @@ struct hwrm_cfa_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27034,7 +27726,9 @@ struct hwrm_cfa_flow_free_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint16_t unused_0;
+ /* Flow counter id to be freed. */
+ uint32_t flow_counter_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -27310,7 +28004,8 @@ struct hwrm_cfa_flow_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27420,7 +28115,8 @@ struct hwrm_cfa_flow_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27448,6 +28144,9 @@ struct hwrm_cfa_flow_flush_input {
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
UINT32_C(0x2)
+ /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
+ UINT32_C(0x8000000)
/*
* This specifies the size of flow handle entries provided by the driver
* in the flow table specified below. Only two flow handle size enums are defined.
@@ -27544,7 +28243,8 @@ struct hwrm_cfa_flow_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27684,7 +28384,8 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27733,7 +28434,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output {
***************************/
-/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -27751,7 +28452,8 @@ struct hwrm_cfa_flow_aging_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27773,16 +28475,40 @@ struct hwrm_cfa_flow_aging_cfg_input {
/* This bit must be '1' for the udp flow timer field to be configured */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
UINT32_C(0x4)
- /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ /* This bit must be '1' for the eem dma interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
+ UINT32_C(0x8)
+ /* This bit must be '1' for the eem notice interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
+ UINT32_C(0x10)
+ /* This bit must be '1' for the eem context memory maximum entries field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
+ UINT32_C(0x20)
+ /* This bit must be '1' for the eem context memory ID field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
+ UINT32_C(0x40)
+ /* This bit must be '1' for the eem context memory type field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
+ UINT32_C(0x80)
uint8_t flags;
/* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ /* Enumeration denoting the enable, disable eem flow aging configuration. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
+ (UINT32_C(0x0) << 1)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
uint8_t unused_0;
/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
uint32_t tcp_flow_timer;
@@ -27790,6 +28516,21 @@ struct hwrm_cfa_flow_aging_cfg_input {
uint32_t tcp_fin_timer;
/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
uint32_t udp_flow_timer;
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ uint16_t eem_ctx_mem_type;
+ /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
+ UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
@@ -27836,7 +28577,8 @@ struct hwrm_cfa_flow_aging_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27860,7 +28602,7 @@ struct hwrm_cfa_flow_aging_qcfg_input {
uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -27876,7 +28618,17 @@ struct hwrm_cfa_flow_aging_qcfg_output {
uint32_t tcp_fin_timer;
/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
uint32_t udp_flow_timer;
- uint8_t unused_0[3];
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ /* The context memory type for eem flow aging. */
+ uint16_t eem_ctx_mem_type;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -27910,7 +28662,8 @@ struct hwrm_cfa_flow_aging_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27986,7 +28739,8 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28051,7 +28805,8 @@ struct hwrm_cfa_pair_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28171,7 +28926,8 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28275,7 +29031,8 @@ struct hwrm_cfa_ctx_mem_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28371,7 +29128,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28434,7 +29192,8 @@ struct hwrm_cfa_ctx_mem_qctx_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28531,7 +29290,8 @@ struct hwrm_cfa_ctx_mem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28582,7 +29342,8 @@ struct hwrm_cfa_eem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28630,13 +29391,31 @@ struct hwrm_cfa_eem_qcaps_output {
* which are to be offloaded.
* Note if this bit is set then the path_rx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
/*
* When set to 1, indicates the configuration will apply to RX flows
* which are to be offloaded.
* Note if this bit is set then the path_tx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /*
+ * When set to 1, indicates the the FW supports the Centralized
+ * Memory Model. The concept designates one entity for the
+ * memory allocation while all others ‘subscribe’ to it.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * When set to 1, indicates the the FW supports the Detached
+ * Centralized Memory Model. The memory is allocated and managed
+ * as a separate entity. All PFs and VFs will be granted direct
+ * or semi-direct access to the allocated memory while none of
+ * which can interfere with the management of the memory.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x8)
uint32_t unused_0;
uint32_t supported;
/*
@@ -28712,7 +29491,8 @@ struct hwrm_cfa_eem_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28741,7 +29521,15 @@ struct hwrm_cfa_eem_cfg_input {
/* When set to 1, all offloaded flows will be sent to EEM. */
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- uint32_t unused_0;
+ /* When set to 1, secondary, 0 means primary. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
+ UINT32_C(0x8)
+ /*
+ * Group_id which used by Firmware to identify memory pools belonging
+ * to certain group.
+ */
+ uint16_t group_id;
+ uint16_t unused_0;
/*
* Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
* RECORD, EFC all have the same number of entries and all tables will be configured
@@ -28803,7 +29591,8 @@ struct hwrm_cfa_eem_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28878,7 +29667,8 @@ struct hwrm_cfa_eem_op_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28974,7 +29764,8 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29045,6 +29836,42 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
+ /*
+ * Value of 1 to indicate that firmware supports the dynamic allocation of an
+ * on-chip flow counter which can be used for EEM flows.
+ * Value of 0 indicates firmware does not support the dynamic allocation of an
+ * on-chip flow counter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
+ * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * Value of 1 to indicate that firmware supports untagged matching
+ * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
+ * indicates firmware does not support untagged matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * Value of 1 to indicate that firmware supports XDP filter. Value
+ * of 0 indicates firmware does not support XDP filter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * Value of 1 to indicate that the firmware support L2 header source
+ * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
+ * Value of 0 indicates firmware does not support L2 header source
+ * fields matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
+ UINT32_C(0x800)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -29056,6 +29883,81 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/******************
+ * hwrm_cfa_tflib *
+ ******************/
+
+
+/* hwrm_cfa_tflib_input (size:1024b/128B) */
+struct hwrm_cfa_tflib_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* unused. */
+ uint8_t unused0[4];
+ /* TFLIB request data. */
+ uint32_t tf_req[26];
+} __attribute__((packed));
+
+/* hwrm_cfa_tflib_output (size:5632b/704B) */
+struct hwrm_cfa_tflib_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* TFLIB response code */
+ uint32_t tf_resp_code;
+ /* TFLIB response data. */
+ uint32_t tf_resp[170];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/******************************
* hwrm_tunnel_dst_port_query *
******************************/
@@ -29079,7 +29981,8 @@ struct hwrm_tunnel_dst_port_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29177,7 +30080,8 @@ struct hwrm_tunnel_dst_port_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29274,7 +30178,8 @@ struct hwrm_tunnel_dst_port_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29451,7 +30356,8 @@ struct hwrm_stat_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29540,7 +30446,8 @@ struct hwrm_stat_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29602,7 +30509,8 @@ struct hwrm_stat_ctx_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29702,7 +30610,8 @@ struct hwrm_stat_ctx_eng_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29803,7 +30712,8 @@ struct hwrm_stat_ctx_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29863,7 +30773,8 @@ struct hwrm_pcie_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29970,7 +30881,8 @@ struct hwrm_exec_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30043,7 +30955,8 @@ struct hwrm_reject_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30116,7 +31029,8 @@ struct hwrm_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30204,7 +31118,8 @@ struct hwrm_fwd_async_event_cmpl_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30273,7 +31188,8 @@ struct hwrm_nvm_raw_write_blk_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30342,7 +31258,8 @@ struct hwrm_nvm_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30412,7 +31329,8 @@ struct hwrm_nvm_raw_dump_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30478,7 +31396,8 @@ struct hwrm_nvm_get_dir_entries_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30540,7 +31459,8 @@ struct hwrm_nvm_get_dir_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30601,7 +31521,8 @@ struct hwrm_nvm_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30722,7 +31643,8 @@ struct hwrm_nvm_modify_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30795,7 +31717,8 @@ struct hwrm_nvm_find_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30897,7 +31820,8 @@ struct hwrm_nvm_erase_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30957,7 +31881,8 @@ struct hwrm_nvm_get_dev_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30991,7 +31916,12 @@ struct hwrm_nvm_get_dev_info_output {
uint32_t reserved_size;
/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
uint32_t available_size;
- uint8_t unused_0[3];
+ /* This field represents the major version of NVM cfg */
+ uint8_t nvm_cfg_ver_maj;
+ /* This field represents the minor version of NVM cfg */
+ uint8_t nvm_cfg_ver_min;
+ /* This field represents the update version of NVM cfg */
+ uint8_t nvm_cfg_ver_upd;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -31025,7 +31955,8 @@ struct hwrm_nvm_mod_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31104,7 +32035,8 @@ struct hwrm_nvm_verify_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31177,7 +32109,8 @@ struct hwrm_nvm_install_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31340,7 +32273,8 @@ struct hwrm_nvm_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31413,7 +32347,8 @@ struct hwrm_nvm_get_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31548,7 +32483,8 @@ struct hwrm_nvm_set_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31678,7 +32614,8 @@ struct hwrm_nvm_validate_option_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 09/10] net/bnxt: HWRM version update
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 09/10] net/bnxt: HWRM version update Lance Richardson
@ 2019-05-28 9:12 ` Ferruh Yigit
2019-05-28 15:06 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Ferruh Yigit @ 2019-05-28 9:12 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin
On 5/24/2019 3:49 PM, Lance Richardson wrote:
> From: Ajit Khaparde <ajit.khaparde@broadcom.com>
>
> Update HWRM API to version 1.10.0.74
There are three commits related:
"update HWRM API" (to version 1.10.0.19)
"update HWRM version" (to 1.10.0.48)
"HWRM version update" (to version 1.10.0.74)
Is "HWRM API" & "HWRM version" different things?
I assume they are not different and these commits are updating "HWRM API
version" gradually, if so can you please use a consistent commit title?
Thanks,
ferruh
>
> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
<...>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [dpdk-dev] [PATCH v2 09/10] net/bnxt: HWRM version update
2019-05-28 9:12 ` Ferruh Yigit
@ 2019-05-28 15:06 ` Lance Richardson
0 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 15:06 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: dev, Ajit Khaparde, Maxime Coquelin
WIll do.
Thanks,
Lance
On Tue, May 28, 2019 at 5:12 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
>
> On 5/24/2019 3:49 PM, Lance Richardson wrote:
> > From: Ajit Khaparde <ajit.khaparde@broadcom.com>
> >
> > Update HWRM API to version 1.10.0.74
>
> There are three commits related:
> "update HWRM API" (to version 1.10.0.19)
> "update HWRM version" (to 1.10.0.48)
> "HWRM version update" (to version 1.10.0.74)
>
> Is "HWRM API" & "HWRM version" different things?
> I assume they are not different and these commits are updating "HWRM API
> version" gradually, if so can you please use a consistent commit title?
>
> Thanks,
> ferruh
>
> >
> > Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> > Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
>
> <...>
>
>
>
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v2 10/10] net/bnxt: update release notes for bnxt
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (8 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 09/10] net/bnxt: HWRM version update Lance Richardson
@ 2019-05-24 14:49 ` Lance Richardson
2019-05-28 9:15 ` Ferruh Yigit
2019-05-28 9:19 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Ferruh Yigit
10 siblings, 1 reply; 75+ messages in thread
From: Lance Richardson @ 2019-05-24 14:49 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update release doc briefly describing updates to bnxt PMD.
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
doc/guides/rel_notes/release_19_08.rst | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index b9510f93a..2ff9d4b1c 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -54,6 +54,12 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
+* **Updated the bnxt PMD.**
+
+ Updated the bnxt PMD. The major enhancements include:
+ * Update HWRM version to 1.10.74
+ * Added vector RX/TX
+ * Performance optimizations in non-vector Tx path
Removed Items
-------------
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 10/10] net/bnxt: update release notes for bnxt
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 10/10] net/bnxt: update release notes for bnxt Lance Richardson
@ 2019-05-28 9:15 ` Ferruh Yigit
0 siblings, 0 replies; 75+ messages in thread
From: Ferruh Yigit @ 2019-05-28 9:15 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin
On 5/24/2019 3:49 PM, Lance Richardson wrote:
> From: Ajit Khaparde <ajit.khaparde@broadcom.com>
>
> Update release doc briefly describing updates to bnxt PMD.
It is better to keep the doc update with the feature patch, instead of a
separate doc patch. Can you please distribute content of this patch into
relevant patches?
>
> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> ---
> doc/guides/rel_notes/release_19_08.rst | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
> index b9510f93a..2ff9d4b1c 100644
> --- a/doc/guides/rel_notes/release_19_08.rst
> +++ b/doc/guides/rel_notes/release_19_08.rst
> @@ -54,6 +54,12 @@ New Features
> Also, make sure to start the actual text at the margin.
> =========================================================
>
> +* **Updated the bnxt PMD.**
> +
> + Updated the bnxt PMD. The major enhancements include:
> + * Update HWRM version to 1.10.74
> + * Added vector RX/TX
We have x86(SSE/AVX2/AVX512), Arm (neon) & PPC (altivec) vectorization support
in DPDK, can you please detail what is added.
> + * Performance optimizations in non-vector Tx path
>
> Removed Items
> -------------
>
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [dpdk-dev] [PATCH v2 00/10] bnxt patchset
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
` (9 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 10/10] net/bnxt: update release notes for bnxt Lance Richardson
@ 2019-05-28 9:19 ` Ferruh Yigit
2019-05-28 15:11 ` Lance Richardson
10 siblings, 1 reply; 75+ messages in thread
From: Ferruh Yigit @ 2019-05-28 9:19 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin
On 5/24/2019 3:49 PM, Lance Richardson wrote:
> This patchset bsae on top of the previous submission adds the following:
> 1) Support for vector mode TX and RX.
> 2) HWRM API update (split into multiple patches).
> 3) Fixes for RSS reta update and query.
>
> It also updates the release notes.
>
> v2:
> * Squashed patches 3 and 4 from v1 patchset.
> * Added Meson build support for vector mode PMD.
> * Dropped two unnecessary code style changes from patch 3.
>
> Ajit Khaparde (5):
> net/bnxt: fix RSS reta indirection table update
> net/bnxt: update HWRM API
> net/bnxt: update HWRM version
> net/bnxt: HWRM version update
> net/bnxt: update release notes for bnxt
>
> Lance Richardson (5):
> net/bnxt: move tx bd checking to header file
> net/bnxt: compute and store scattered RX status
> net/bnxt: implement vector mode driver
> net/bnxt: use reta update mask and translate qid to grp id
> net/bnxt: fix reta query op
There are warnings from
"./devtools/checkpatches.sh" & "./devtools/check-git-log.sh"
Can you please address them in next version?
It is acceptable to have some level of "checkpatches.sh" in the base code update
(HWRM update code for your case) but please sure DPDK specific files don't have
any warning.
Thanks,
ferruh
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v2 00/10] bnxt patchset
2019-05-28 9:19 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Ferruh Yigit
@ 2019-05-28 15:11 ` Lance Richardson
0 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 15:11 UTC (permalink / raw)
To: Ferruh Yigit; +Cc: dev, Ajit Khaparde, Maxime Coquelin
On Tue, May 28, 2019 at 5:19 AM Ferruh Yigit <ferruh.yigit@intel.com> wrote:
...
> There are warnings from
> "./devtools/checkpatches.sh" & "./devtools/check-git-log.sh"
> Can you please address them in next version?
>
> It is acceptable to have some level of "checkpatches.sh" in the base code update
> (HWRM update code for your case) but please sure DPDK specific files don't have
> any warning.
>
> Thanks,
> ferruh
Sorry about that. I had run checkpatches.sh (which had warnings only
for HWRM API updates),
but not check-git-log.sh.
Thanks,
Lance
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v3 0/8] bnxt patchset
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (11 preceding siblings ...)
2019-05-24 14:49 ` [dpdk-dev] [PATCH v2 00/10] bnxt patchset Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 1/8] net/bnxt: update release notes for bnxt Lance Richardson
` (7 more replies)
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
14 siblings, 8 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
This patchset bsae on top of the previous submission adds the following:
1) Support for vector mode TX and RX.
2) HWRM API update (split into multiple patches).
3) Fixes for RSS reta update and query.
It also updates the release notes.
v2:
* Squashed patches 3 and 4 from v1 patchset.
* Added Meson build support for vector mode PMD.
* Dropped two unnecessary code style changes from patch 3.
v3:
* Squashed three RSS RETA fix patches into one.
* Eliminated RTE_LIBRTE_BNXT_INC_VECTOR configuration flag.
* Addressed commit log issues from check-git-log.sh.
* Made subject line consistent for HWRM API update patches.
* Separated release notes updates to keep update with associated
patch (except for the first update for which the associated patch
has already been applied).
Ajit Khaparde (5):
net/bnxt: update release notes for bnxt
net/bnxt: fix RSS RETA indirection table ops
net/bnxt: update HWRM API to version 1.10.0.19
net/bnxt: update HWRM API to version 1.10.0.48
net/bnxt: update HWRM API to version 1.10.0.74
Lance Richardson (3):
net/bnxt: move Tx bd checking to header file
net/bnxt: compute and store scattered Rx status
net/bnxt: implement vector mode driver
doc/guides/rel_notes/release_19_08.rst | 6 +
drivers/net/bnxt/Makefile | 3 +
drivers/net/bnxt/bnxt_ethdev.c | 201 +-
drivers/net/bnxt/bnxt_hwrm.c | 1 +
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 ++
drivers/net/bnxt/bnxt_txr.c | 15 -
drivers/net/bnxt/bnxt_txr.h | 20 +
drivers/net/bnxt/hsi_struct_def_dpdk.h | 7573 ++++++++++++++++++++----
drivers/net/bnxt/meson.build | 4 +
13 files changed, 7219 insertions(+), 1106 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v3 1/8] net/bnxt: update release notes for bnxt
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
` (6 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update release doc briefly describing updates to bnxt PMD,
including transmit optimization changes in the following
commits:
commit 5c26b1706862 ("net/bnxt: support bulk free of Tx mbufs")
commit f8dea49ef89b ("net/bnxt: optimize Tx batching code")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
doc/guides/rel_notes/release_19_08.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 5ebb564b1..2b66f41f5 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -54,6 +54,10 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
+* **Updated the bnxt PMD.**
+
+ Updated the bnxt PMD. The major enhancements include:
+ * Performance optimizations in non-vector Tx path
Removed Items
-------------
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v3 2/8] net/bnxt: move Tx bd checking to header file
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 1/8] net/bnxt: update release notes for bnxt Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
` (5 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
vector-mode and non-vector transmit functions, move these functions
into bnxt_txr.h.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/net/bnxt/bnxt_txr.c | 15 ---------------
drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 9de12e0d0..16598ba63 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
return 0;
}
-static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
-{
- return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
- txq->tx_ring->tx_ring_struct->ring_mask);
-}
-
-static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
-{
- /* Tell compiler to fetch tx indices from memory. */
- rte_compiler_barrier();
-
- return ((txq->tx_ring->tx_ring_struct->ring_size -
- bnxt_tx_bds_in_hw(txq)) - 1);
-}
-
static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
struct bnxt_tx_queue *txq,
uint16_t *coal_pkts,
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index f802d5080..13ca04676 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -37,6 +37,21 @@ struct bnxt_sw_tx_bd {
unsigned short nr_bds;
};
+static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
+{
+ return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
+ txq->tx_ring->tx_ring_struct->ring_mask);
+}
+
+static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
+{
+ /* Tell compiler to fetch tx indices from memory. */
+ rte_compiler_barrier();
+
+ return ((txq->tx_ring->tx_ring_struct->ring_size -
+ bnxt_tx_bds_in_hw(txq)) - 1);
+}
+
void bnxt_free_tx_rings(struct bnxt *bp);
int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v3 3/8] net/bnxt: compute and store scattered Rx status
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 1/8] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 4/8] net/bnxt: implement vector mode driver Lance Richardson
` (4 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
In preparation for a bnxt vector-mode driver, compute and store
scattered_rx status for the device when started.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/net/bnxt/bnxt_ethdev.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index b0244d6d1..5b3932b7b 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -624,6 +624,27 @@ static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
return 0;
}
+/*
+ * Determine whether the current configuration requires support for scattered
+ * receive; return 1 if scattered receive is required and 0 if not.
+ */
+static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
+{
+ uint16_t buf_size;
+ int i;
+
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
+
+ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
+ RTE_PKTMBUF_HEADROOM);
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
+ return 1;
+ }
+ return 0;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -642,6 +663,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
+
bnxt_link_update_op(eth_dev, 1);
if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v3 4/8] net/bnxt: implement vector mode driver
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
` (2 preceding siblings ...)
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-29 6:48 ` Maxime Coquelin
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
` (3 subsequent siblings)
7 siblings, 1 reply; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
Introduce SSE vector mode support for the bnxt pmd.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
v2:
* Squashed with v1 patch 4 ("fix double counting VLAN tags").
* Dropped two unnecessary coding style changes from bnxt_txr.h.
v3:
* Eliminated vector mode configration flag.
* Added RTE_ARCH_X86 checks around vector mode code.
* Added release notes item for SSE vector mode.
* Added RTE_ prefix to ETHER_HDR_LEN and ETHER_CRC_LEN.
doc/guides/rel_notes/release_19_08.rst | 1 +
drivers/net/bnxt/Makefile | 3 +
drivers/net/bnxt/bnxt_ethdev.c | 98 ++++-
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 +++++++++++++++++++++++++
drivers/net/bnxt/bnxt_txr.h | 5 +
drivers/net/bnxt/meson.build | 4 +
10 files changed, 603 insertions(+), 10 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 2b66f41f5..7e5ca3c34 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -58,6 +58,7 @@ New Features
Updated the bnxt PMD. The major enhancements include:
* Performance optimizations in non-vector Tx path
+ * Added support for SSE vector mode
Removed Items
-------------
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
index 8be3cb0e4..21a565063 100644
--- a/drivers/net/bnxt/Makefile
+++ b/drivers/net/bnxt/Makefile
@@ -41,6 +41,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_util.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += rte_pmd_bnxt.c
+ifeq ($(CONFIG_RTE_ARCH_X86), y)
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_rxtx_vec_sse.c
+endif
#
# Export include files
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 5b3932b7b..bccba445a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -638,13 +638,73 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
RTE_PKTMBUF_HEADROOM);
- if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
- VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
return 1;
}
return 0;
}
+static eth_rx_burst_t
+bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_ARCH_X86
+ /*
+ * Vector mode receive can be enabled only if scatter rx is not
+ * in use and rx offloads are limited to VLAN stripping and
+ * CRC stripping.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.rxmode.offloads &
+ ~(DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_KEEP_CRC |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM |
+ DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_VLAN_FILTER))) {
+ PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_recv_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d rx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.rxmode.offloads);
+#endif
+ return bnxt_recv_pkts;
+}
+
+static eth_tx_burst_t
+bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_ARCH_X86
+ /*
+ * Vector mode receive can be enabled only if scatter tx is not
+ * in use and tx offloads other than VLAN insertion are not
+ * in use.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.txmode.offloads &
+ ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
+ PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_xmit_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d tx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.txmode.offloads);
+#endif
+ return bnxt_xmit_pkts;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -675,6 +735,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
+ eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
bp->flags |= BNXT_FLAG_INIT_DONE;
return 0;
@@ -1601,9 +1663,13 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_dev_info dev_info;
+ uint32_t new_pkt_size;
uint32_t rc = 0;
uint32_t i;
+ new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS;
+
bnxt_dev_info_get_op(eth_dev, &dev_info);
if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
@@ -1612,6 +1678,23 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
return -EINVAL;
}
+#ifdef RTE_ARCH_X86
+ /*
+ * If vector-mode tx/rx is active, disallow any MTU change that would
+ * require scattered receive support.
+ */
+ if (eth_dev->data->dev_started &&
+ (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
+ eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
+ (new_pkt_size >
+ eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
+ PMD_DRV_LOG(ERR,
+ "MTU change would require scattered rx support. ");
+ PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
+ return -EINVAL;
+ }
+#endif
+
if (new_mtu > RTE_ETHER_MTU) {
bp->flags |= BNXT_FLAG_JUMBO;
bp->eth_dev->data->dev_conf.rxmode.offloads |=
@@ -1622,9 +1705,7 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
bp->flags &= ~BNXT_FLAG_JUMBO;
}
- eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
- new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
- VLAN_TAG_SIZE * 2;
+ eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
eth_dev->data->mtu = new_mtu;
PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
@@ -2659,9 +2740,10 @@ bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
RTE_PTYPE_UNKNOWN
};
- if (dev->rx_pkt_burst == bnxt_recv_pkts)
- return ptypes;
- return NULL;
+ if (!dev->rx_pkt_burst)
+ return NULL;
+
+ return ptypes;
}
static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index 1446d784f..fd3d0bd73 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -10,7 +10,8 @@
#include <rte_memory.h>
-#define RING_NEXT(ring, idx) (((idx) + 1) & (ring)->ring_mask)
+#define RING_ADV(ring, idx, n) (((idx) + (n)) & (ring)->ring_mask)
+#define RING_NEXT(ring, idx) RING_ADV(ring, idx, 1)
#define DB_IDX_MASK 0xffffff
#define DB_IDX_VALID (0x1 << 26)
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index f1ee9eede..2ce2ef427 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -355,6 +355,11 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
RTE_ETH_QUEUE_STATE_STARTED;
eth_dev->data->rx_queue_state[queue_idx] = queue_state;
rte_spinlock_init(&rxq->lock);
+
+#ifdef RTE_ARCH_X86
+ bnxt_rxq_vec_setup(rxq);
+#endif
+
out:
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h
index e5d6001d3..7c6b4dec9 100644
--- a/drivers/net/bnxt/bnxt_rxq.h
+++ b/drivers/net/bnxt/bnxt_rxq.h
@@ -22,6 +22,10 @@ struct bnxt_rx_queue {
uint16_t nb_rx_hold; /* num held free RX desc */
uint16_t rx_free_thresh; /* max free RX desc to hold */
uint16_t queue_id; /* RX queue index */
+#ifdef RTE_ARCH_X86
+ uint16_t rxrearm_nb; /* number of descs to reinit. */
+ uint16_t rxrearm_start; /* next desc index to reinit. */
+#endif
uint16_t reg_idx; /* RX queue register index */
uint16_t port_id; /* Device port identifier */
uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 3815a2199..d10cefb93 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -7,7 +7,7 @@
#define _BNXT_RXR_H_
#define B_RX_DB(db, prod) \
- (*(uint32_t *)db = (DB_KEY_RX | prod))
+ (*(uint32_t *)db = (DB_KEY_RX | (prod)))
#define BNXT_TPA_L4_SIZE(x) \
{ \
@@ -110,4 +110,11 @@ int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+
+#ifdef RTE_ARCH_X86
+uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
+int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
+#endif
+
#endif
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
new file mode 100644
index 000000000..1c32c986c
--- /dev/null
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright(c) 2019 Broadcom All rights reserved. */
+
+#include <inttypes.h>
+#include <stdbool.h>
+
+#include <rte_bitmap.h>
+#include <rte_byteorder.h>
+#include <rte_malloc.h>
+#include <rte_memory.h>
+#if defined(RTE_ARCH_X86)
+#include <tmmintrin.h>
+#else
+#error "bnxt vector pmd: unsupported target."
+#endif
+
+#include "bnxt.h"
+#include "bnxt_cpr.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxr.h"
+#include "bnxt_rxq.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "bnxt_txq.h"
+#include "bnxt_txr.h"
+
+/*
+ * RX Ring handling
+ */
+
+#define RTE_BNXT_MAX_RX_BURST 32
+#define RTE_BNXT_MAX_TX_BURST 32
+#define RTE_BNXT_RXQ_REARM_THRESH 32
+#define RTE_BNXT_DESCS_PER_LOOP 4
+
+static inline void
+bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
+{
+ struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
+ struct bnxt_sw_rx_bd *rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
+ struct rte_mbuf *mb0, *mb1;
+ int i;
+
+ const __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, 0);
+ const __m128i addrmask = _mm_set_epi64x(UINT64_MAX, 0);
+
+ /* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
+ if (rte_mempool_get_bulk(rxq->mb_pool,
+ (void *)rx_bufs,
+ RTE_BNXT_RXQ_REARM_THRESH) < 0) {
+ rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
+ RTE_BNXT_RXQ_REARM_THRESH;
+
+ return;
+ }
+
+ /* Initialize the mbufs in vector, process 2 mbufs in one loop */
+ for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
+ __m128i buf_addr0, buf_addr1;
+ __m128i rxbd0, rxbd1;
+
+ mb0 = rx_bufs[0].mbuf;
+ mb1 = rx_bufs[1].mbuf;
+
+ /* Load address fields from both mbufs */
+ buf_addr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
+ buf_addr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
+
+ /* Load both rx descriptors (preserving some existing fields) */
+ rxbd0 = _mm_loadu_si128((__m128i *)(rxbds + 0));
+ rxbd1 = _mm_loadu_si128((__m128i *)(rxbds + 1));
+
+ /* Add default offset to buffer address. */
+ buf_addr0 = _mm_add_epi64(buf_addr0, hdr_room);
+ buf_addr1 = _mm_add_epi64(buf_addr1, hdr_room);
+
+ /* Clear all fields except address. */
+ buf_addr0 = _mm_and_si128(buf_addr0, addrmask);
+ buf_addr1 = _mm_and_si128(buf_addr1, addrmask);
+
+ /* Clear address field in descriptor. */
+ rxbd0 = _mm_andnot_si128(addrmask, rxbd0);
+ rxbd1 = _mm_andnot_si128(addrmask, rxbd1);
+
+ /* Set address field in descriptor. */
+ rxbd0 = _mm_add_epi64(rxbd0, buf_addr0);
+ rxbd1 = _mm_add_epi64(rxbd1, buf_addr1);
+
+ /* Store descriptors to memory. */
+ _mm_store_si128((__m128i *)(rxbds++), rxbd0);
+ _mm_store_si128((__m128i *)(rxbds++), rxbd1);
+ }
+
+ rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
+ B_RX_DB(rxr->rx_doorbell, rxq->rxrearm_start - 1);
+ if (rxq->rxrearm_start >= rxq->nb_rx_desc)
+ rxq->rxrearm_start = 0;
+
+ rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
+}
+
+static uint32_t
+bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ uint32_t l3, pkt_type = 0;
+ uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
+ uint32_t flags_type;
+
+ vlan = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ t_ipcs = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
+ ip6 = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
+
+ flags_type = rxcmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
+
+ if (!t_ipcs && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_ipcs && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_ipcs && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ return pkt_type;
+}
+
+uint16_t
+bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_rx_queue *rxq = rx_queue;
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ int nb_rx_pkts = 0;
+ struct rx_pkt_cmpl *rxcmp;
+ bool evt = false;
+ const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
+ const __m128i shuf_msk =
+ _mm_set_epi8(15, 14, 13, 12, /* rss */
+ 0xFF, 0xFF, /* vlan_tci (zeroes) */
+ 3, 2, /* data_len */
+ 0xFF, 0xFF, 3, 2, /* pkt_len */
+ 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
+
+ /* If Rx Q was stopped return */
+ if (rxq->rx_deferred_start)
+ return 0;
+
+ if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
+ bnxt_rxq_rearm(rxq, rxr);
+
+ /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
+ nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
+
+ /* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP */
+ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
+
+ /* Handle RX burst request */
+ while (1) {
+ cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
+
+ rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
+
+ if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
+ break;
+
+ cpr->valid = FLIP_VALID(cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ if (likely(CMP_TYPE(rxcmp) == RX_PKT_CMPL_TYPE_RX_L2)) {
+ struct rx_pkt_cmpl_hi *rxcmp1;
+ uint32_t tmp_raw_cons;
+ uint16_t cp_cons;
+ struct rte_mbuf *mbuf;
+ __m128i mm_rxcmp, pkt_mb;
+
+ tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
+ cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
+ rxcmp1 = (struct rx_pkt_cmpl_hi *)
+ &cpr->cp_desc_ring[cp_cons];
+
+ if (!CMP_VALID(rxcmp1, tmp_raw_cons,
+ cpr->cp_ring_struct))
+ break;
+
+ raw_cons = tmp_raw_cons;
+ cons = rxcmp->opaque;
+
+ mbuf = rxr->rx_buf_ring[cons].mbuf;
+ rte_prefetch0(mbuf);
+ rxr->rx_buf_ring[cons].mbuf = NULL;
+
+ cpr->valid = FLIP_VALID(cp_cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ /* Set constant fields from mbuf initializer. */
+ _mm_store_si128((__m128i *)&mbuf->rearm_data,
+ mbuf_init);
+
+ /* Set mbuf pkt_len, data_len, and rss_hash fields. */
+ mm_rxcmp = _mm_load_si128((__m128i *)rxcmp);
+ pkt_mb = _mm_shuffle_epi8(mm_rxcmp, shuf_msk);
+ _mm_storeu_si128((void *)&mbuf->rx_descriptor_fields1,
+ pkt_mb);
+
+ rte_compiler_barrier();
+
+ if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
+ mbuf->ol_flags |= PKT_RX_RSS_HASH;
+
+ if (rxcmp1->flags2 &
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
+ mbuf->vlan_tci = rxcmp1->metadata &
+ (RX_PKT_CMPL_METADATA_VID_MASK |
+ RX_PKT_CMPL_METADATA_DE |
+ RX_PKT_CMPL_METADATA_PRI_MASK);
+ mbuf->ol_flags |= PKT_RX_VLAN;
+ }
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
+ rx_pkts[nb_rx_pkts++] = mbuf;
+ } else {
+ evt =
+ bnxt_event_hwrm_resp_handler(rxq->bp,
+ (struct cmpl_base *)rxcmp);
+ }
+
+ raw_cons = NEXT_RAW_CMP(raw_cons);
+ if (nb_rx_pkts == nb_pkts || evt)
+ break;
+ }
+ rxr->rx_prod = RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
+
+ rxq->rxrearm_nb += nb_rx_pkts;
+ cpr->cp_raw_cons = raw_cons;
+ if (nb_rx_pkts || evt)
+ B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
+
+ return nb_rx_pkts;
+}
+
+static inline void bnxt_next_cmpl(struct bnxt_cp_ring_info *cpr, uint32_t *idx,
+ bool *v, uint32_t inc)
+{
+ *idx += inc;
+ if (unlikely(*idx == cpr->cp_ring_struct->ring_size)) {
+ *v = !*v;
+ *idx = 0;
+ }
+}
+
+static void
+bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
+{
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ struct rte_mbuf **free = txq->free;
+ uint16_t cons = txr->tx_cons;
+ unsigned int blk = 0;
+
+ while (nr_pkts--) {
+ struct bnxt_sw_tx_bd *tx_buf;
+ struct rte_mbuf *mbuf;
+
+ tx_buf = &txr->tx_buf_ring[cons];
+ cons = RING_NEXT(txr->tx_ring_struct, cons);
+ mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
+ tx_buf->mbuf = NULL;
+
+ if (blk && mbuf->pool != free[0]->pool) {
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+ blk = 0;
+ }
+ free[blk++] = mbuf;
+ }
+ if (blk)
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+
+ txr->tx_cons = cons;
+}
+
+static void
+bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
+{
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ uint32_t nb_tx_pkts = 0;
+ struct tx_cmpl *txcmp;
+ struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
+ struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
+ uint32_t ring_mask = cp_ring_struct->ring_mask;
+
+ do {
+ cons = RING_CMPL(ring_mask, raw_cons);
+ txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
+
+ if (!CMPL_VALID(txcmp, cpr->valid))
+ break;
+ bnxt_next_cmpl(cpr, &cons, &cpr->valid, 1);
+ rte_prefetch0(&cp_desc_ring[cons]);
+
+ if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ nb_tx_pkts += txcmp->opaque;
+ else
+ RTE_LOG_DP(ERR, PMD,
+ "Unhandled CMP type %02x\n",
+ CMP_TYPE(txcmp));
+ raw_cons = cons;
+ } while (nb_tx_pkts < ring_mask);
+
+ if (nb_tx_pkts) {
+ bnxt_tx_cmp_vec(txq, nb_tx_pkts);
+ cpr->cp_raw_cons = raw_cons;
+ B_CP_DB(cpr, raw_cons, ring_mask);
+ }
+}
+
+#define TX_BD_FLAGS_CMPL ((1 << TX_BD_LONG_FLAGS_BD_CNT_SFT) | \
+ TX_BD_SHORT_FLAGS_COAL_NOW | \
+ TX_BD_SHORT_TYPE_TX_BD_SHORT | \
+ TX_BD_LONG_FLAGS_PACKET_END)
+
+#define TX_BD_FLAGS_NOCMPL (TX_BD_FLAGS_CMPL | TX_BD_LONG_FLAGS_NO_CMPL)
+
+static inline uint32_t
+bnxt_xmit_flags_len(uint16_t len, uint16_t flags)
+{
+ switch (len >> 9) {
+ case 0:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT512;
+ case 1:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT1K;
+ case 2:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ case 3:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ default:
+ return flags | TX_BD_LONG_FLAGS_LHINT_GTE2K;
+ }
+}
+
+static uint16_t
+bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_tx_queue *txq = tx_queue;
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ uint16_t prod = txr->tx_prod;
+ struct rte_mbuf *tx_mbuf;
+ struct tx_bd_long *txbd = NULL;
+ struct bnxt_sw_tx_bd *tx_buf;
+ uint16_t to_send;
+
+ nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
+
+ if (unlikely(nb_pkts == 0))
+ return 0;
+
+ /* Handle TX burst request */
+ to_send = nb_pkts;
+ while (to_send) {
+ tx_mbuf = *tx_pkts++;
+ rte_prefetch0(tx_mbuf);
+
+ tx_buf = &txr->tx_buf_ring[prod];
+ tx_buf->mbuf = tx_mbuf;
+ tx_buf->nr_bds = 1;
+
+ txbd = &txr->tx_desc_ring[prod];
+ txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
+ txbd->len = tx_mbuf->data_len;
+ txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
+ TX_BD_FLAGS_NOCMPL);
+ prod = RING_NEXT(txr->tx_ring_struct, prod);
+ to_send--;
+ }
+
+ /* Request a completion for last packet in burst */
+ if (txbd) {
+ txbd->opaque = nb_pkts;
+ txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
+ }
+
+ rte_compiler_barrier();
+ B_TX_DB(txr->tx_doorbell, prod);
+
+ txr->tx_prod = prod;
+
+ return nb_pkts;
+}
+
+uint16_t
+bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ int nb_sent = 0;
+ struct bnxt_tx_queue *txq = tx_queue;
+
+ /* Tx queue was stopped; wait for it to be restarted */
+ if (unlikely(txq->tx_deferred_start)) {
+ PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
+ return 0;
+ }
+
+ /* Handle TX completions */
+ if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
+ bnxt_handle_tx_cp_vec(txq);
+
+ while (nb_pkts) {
+ uint16_t ret, num;
+
+ num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
+ ret = bnxt_xmit_fixed_burst_vec(tx_queue,
+ &tx_pkts[nb_sent],
+ num);
+ nb_sent += ret;
+ nb_pkts -= ret;
+ if (ret < num)
+ break;
+ }
+
+ return nb_sent;
+}
+
+int __attribute__((cold))
+bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
+{
+ uintptr_t p;
+ struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
+
+ mb_def.nb_segs = 1;
+ mb_def.data_off = RTE_PKTMBUF_HEADROOM;
+ mb_def.port = rxq->port_id;
+ rte_mbuf_refcnt_set(&mb_def, 1);
+
+ /* prevent compiler reordering: rearm_data covers previous fields */
+ rte_compiler_barrier();
+ p = (uintptr_t)&mb_def.rearm_data;
+ rxq->mbuf_initializer = *(uint64_t *)p;
+ rxq->rxrearm_nb = 0;
+ rxq->rxrearm_start = 0;
+ return 0;
+}
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index 13ca04676..58678a1c8 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -57,6 +57,11 @@ int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+#ifdef RTE_ARCH_X86
+uint16_t bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
+#endif
+
int bnxt_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
int bnxt_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index e130f2712..4dda28f5b 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -18,3 +18,7 @@ sources = files('bnxt_cpr.c',
'bnxt_util.c',
'bnxt_vnic.c',
'rte_pmd_bnxt.c')
+
+if arch_subdir == 'x86'
+ sources += files('bnxt_rxtx_vec_sse.c')
+endif
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v3 4/8] net/bnxt: implement vector mode driver
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 4/8] net/bnxt: implement vector mode driver Lance Richardson
@ 2019-05-29 6:48 ` Maxime Coquelin
2019-05-29 13:19 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Maxime Coquelin @ 2019-05-29 6:48 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, ferruh.yigit
On 5/28/19 9:23 PM, Lance Richardson wrote:
> diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> index 5b3932b7b..bccba445a 100644
> --- a/drivers/net/bnxt/bnxt_ethdev.c
> +++ b/drivers/net/bnxt/bnxt_ethdev.c
> @@ -638,13 +638,73 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
>
> buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
> RTE_PKTMBUF_HEADROOM);
> - if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
> - VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
> + if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
> return 1;
> }
> return 0;
> }
It seems you forgot to squash this in patch 3.
^ permalink raw reply [flat|nested] 75+ messages in thread
* Re: [dpdk-dev] [PATCH v3 4/8] net/bnxt: implement vector mode driver
2019-05-29 6:48 ` Maxime Coquelin
@ 2019-05-29 13:19 ` Lance Richardson
0 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 13:19 UTC (permalink / raw)
To: Maxime Coquelin; +Cc: dev, Ajit Khaparde, Ferruh Yigit
On Wed, May 29, 2019 at 2:48 AM Maxime Coquelin
<maxime.coquelin@redhat.com> wrote:
>
>
>
> On 5/28/19 9:23 PM, Lance Richardson wrote:
> > diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
> > index 5b3932b7b..bccba445a 100644
> > --- a/drivers/net/bnxt/bnxt_ethdev.c
> > +++ b/drivers/net/bnxt/bnxt_ethdev.c
> > @@ -638,13 +638,73 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
> >
> > buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
> > RTE_PKTMBUF_HEADROOM);
> > - if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len +
> > - VLAN_TAG_SIZE * BNXT_NUM_VLANS > buf_size)
> > + if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
> > return 1;
> > }
> > return 0;
> > }
>
> It seems you forgot to squash this in patch 3.
Thanks, good catch...
it appears that I did squash patch 4 from the v1 set, but I mistakenly
squashed it into patch 3 instead of patch 2.
I'll fix in the next spin.
Lance
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v3 5/8] net/bnxt: fix RSS RETA indirection table ops
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
` (3 preceding siblings ...)
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 4/8] net/bnxt: implement vector mode driver Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
` (2 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson, stable
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
We are trying to update the indirection table for all the VNICs.
We should update the table only for the default vnic0.
Fix the reta update function to only update table entries that are
selected by the update mask. Translate queue number to firmware
group ID when updating an entry.
Fix reta query op to only return table entries as identfied by the
provided mask. Translate firmware group IDs to queue numbers.
Removed extraneous code from bnxt_reta_query_op().
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Rahul Gupta <rahul.gupta@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Cc: stable@dpdk.org
---
v3:
* Squashed three RSS RETA fix commits into one.
drivers/net/bnxt/bnxt_ethdev.c | 92 +++++++++++++++++++++++++---------
drivers/net/bnxt/bnxt_hwrm.c | 1 +
2 files changed, 70 insertions(+), 23 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index bccba445a..30dff72a6 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -618,12 +618,6 @@ static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
eth_dev->data->port_id);
}
-static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
-{
- bnxt_print_link_info(eth_dev);
- return 0;
-}
-
/*
* Determine whether the current configuration requires support for scattered
* receive; return 1 if scattered receive is required and 0 if not.
@@ -977,30 +971,72 @@ static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
}
+/* Return bnxt_rx_queue pointer corresponding to a given rxq. */
+static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
+{
+ if (qid >= bp->rx_nr_rings)
+ return NULL;
+
+ return bp->eth_dev->data->rx_queues[qid];
+}
+
+/* Return rxq corresponding to a given rss table ring/group ID. */
+static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
+{
+ unsigned int i;
+
+ for (i = 0; i < bp->rx_nr_rings; i++) {
+ if (bp->grp_info[i].fw_grp_id == fwr)
+ return i;
+ }
+
+ return INVALID_HW_RING_ID;
+}
+
static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
- struct bnxt_vnic_info *vnic;
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft;
int i;
+ if (!vnic->rss_table)
+ return -EINVAL;
+
if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* Update the RSS VNIC(s) */
- for (i = 0; i < bp->max_vnics; i++) {
- vnic = &bp->vnic_info[i];
- memcpy(vnic->rss_table, reta_conf, reta_size);
- bnxt_hwrm_vnic_rss_cfg(bp, vnic);
+
+ for (i = 0; i < reta_size; i++) {
+ struct bnxt_rx_queue *rxq;
+
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (!(reta_conf[idx].mask & (1ULL << sft)))
+ continue;
+
+ rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
+ if (!rxq) {
+ PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
+ return -EINVAL;
+ }
+
+ vnic->rss_table[i] =
+ vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
}
+
+ bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
@@ -1010,8 +1046,8 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
- struct rte_intr_handle *intr_handle
- = &bp->pdev->intr_handle;
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft, i;
/* Retrieve from the default VNIC */
if (!vnic)
@@ -1019,18 +1055,28 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
if (!vnic->rss_table)
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* EW - need to revisit here copying from uint64_t to uint16_t */
- memcpy(reta_conf, vnic->rss_table, reta_size);
- if (rte_intr_allow_others(intr_handle)) {
- if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
- bnxt_dev_lsc_intr_setup(eth_dev);
+ for (idx = 0, i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (reta_conf[idx].mask & (1ULL << sft)) {
+ uint16_t qid;
+
+ qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
+
+ if (qid == INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
+ return -EINVAL;
+ }
+ reta_conf[idx].reta[sft] = qid;
+ }
}
return 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 4f0142cdb..20b45c23a 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1607,6 +1607,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
req.hash_key_tbl_addr =
rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
+ req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v3 6/8] net/bnxt: update HWRM API to version 1.10.0.19
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
` (4 preceding siblings ...)
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.19
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3112 +++++++++++++++++++-----
1 file changed, 2514 insertions(+), 598 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index e80057936..ea9a7d40e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2018 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Limited
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -68,9 +68,9 @@ struct hwrm_resp_hdr {
/* RoCE slow path command */
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
/* RoCE slow path command to query CC Gen1 support. */
-#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
/* RoCE slow path command to modify CC Gen1 support. */
-#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
/* Engine CKV - The device's serial number. */
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
/* Engine CKV - Per-function random nonce data. */
@@ -366,6 +366,7 @@ struct cmd_nums {
#define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
#define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
#define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
+ #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
#define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
#define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
@@ -442,6 +443,14 @@ struct cmd_nums {
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -591,61 +600,79 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ /*
+ * This error code is only reported by firmware when the specific
+ * request is not able to process when the HOT reset in progress.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances are not capable of hot reset.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ /*
+ * This value indicates that the HWRM response is in TLV format and
+ * should be interpreted as one or more TLVs starting with the
+ * hwrm_resp_hdr TLV. This value is not an indicatation of any error
+ * by itself, just an indicatation that the response should be parsed
+ * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
+ */
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -705,11 +732,11 @@ struct hwrm_err_output {
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
#define HWRM_VERSION_MAJOR 1
-#define HWRM_VERSION_MINOR 9
-#define HWRM_VERSION_UPDATE 2
+#define HWRM_VERSION_MINOR 10
+#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 53
-#define HWRM_VERSION_STR "1.9.2.53"
+#define HWRM_VERSION_RSVD 19
+#define HWRM_VERSION_STR "1.10.0.19"
/****************
* hwrm_ver_get *
@@ -959,6 +986,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
UINT32_C(0x100)
+ /*
+ * If set to 1, firmware is capable to support flow aging.
+ * If set to 0, firmware is not capable to support flow aging.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
+ UINT32_C(0x200)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -2031,7 +2065,7 @@ struct cmpl_base {
#define CMPL_BASE_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
/*
@@ -2116,7 +2150,7 @@ struct tx_cmpl {
#define TX_CMPL_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
@@ -2408,30 +2442,31 @@ struct rx_pkt_cmpl_hi {
* inner packet and that the ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the t_ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the t_l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
+ (UINT32_C(0x0) << 4)
/*
* The metadata field contains the VLAN tag and TPID value.
* - metadata[11:0] contains the vlan VID value.
@@ -2439,16 +2474,70 @@ struct rx_pkt_cmpl_hi {
* - metadata[15:13] contains the vlan PRI value.
* - metadata[31:16] contains the vlan TPID value.
*/
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
+ (UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
* This value is only valid if itype indicates a packet
* with an IP header.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2511,8 +2600,14 @@ struct rx_pkt_cmpl_hi {
*/
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
(UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
+ RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This indicates that there was an error in the IP header
* checksum.
@@ -2553,7 +2648,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 9)
@@ -2611,7 +2706,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 12)
@@ -2854,28 +2949,33 @@ struct rx_tpa_start_cmpl_hi {
* inner packet and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
+ UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the sum passed
* for all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
+ UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
+ UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the sum passed for
* all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
+ UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
+ UINT32_C(0xf0)
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
(UINT32_C(0x0) << 4)
@@ -2888,13 +2988,71 @@ struct rx_tpa_start_cmpl_hi {
*/
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
(UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
+ UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
+ UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
+ UINT32_C(0xc00)
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set. For TPA Start completions,
+ * the complete checksum is calculated for the first packet in the
+ * aggregation only.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2911,13 +3069,41 @@ struct rx_tpa_start_cmpl_hi {
/* When meta_format=1, this value is the VLAN TPID. */
#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
- uint16_t v2;
+ uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define RX_TPA_START_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for the packet that was found after part of the
+ * packet was already placed. The packet should be treated as
+ * invalid.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This field identifies the CFA action rule that was used for this
* packet.
@@ -3034,11 +3220,11 @@ struct rx_tpa_end_cmpl {
/*
* This value indicates what the inner packet determined for the
* packet was.
- * - 2 TCP Packet
- * Indicates that the packet was IP and TCP. This indicates
- * that the ip_cs field is valid and that the tcp_udp_cs
- * field is valid and contains the TCP checksum.
- * This also indicates that the payload_offset field is valid.
+ * - 2 TCP Packet
+ * Indicates that the packet was IP and TCP. This indicates
+ * that the ip_cs field is valid and that the tcp_udp_cs
+ * field is valid and contains the TCP checksum.
+ * This also indicates that the payload_offset field is valid.
*/
#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
@@ -3117,13 +3303,28 @@ struct rx_tpa_end_cmpl_hi {
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
- uint32_t tpa_dup_acks;
+ uint16_t tpa_dup_acks;
/*
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+ /*
+ * This value indicated the offset in bytes from the beginning of
+ * the packet where the inner payload starts. This value is valid
+ * for TCP, UDP, FCoE and RoCE packets
+ */
+ uint8_t payload_offset;
+ /*
+ * The value is the total number of aggregation buffers that were
+ * used in the TPA operation. All TPA aggregation buffer completions
+ * preceed the TPA End completion. If the value is zero, then the
+ * aggregation is completely contained in the buffer space provided
+ * in the aggregation start completion.
+ * Note that the field is simply provided as a cross check.
+ */
+ uint8_t tpa_agg_bufs;
/*
* This value is the valid when TPA completion is active. It
* indicates the length of the longest segment of the TPA operation
@@ -3154,6 +3355,9 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
/*
* This error occurs when there is a fatal HW problem in
* the chip only. It indicates that there were not
@@ -3162,6 +3366,12 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
(UINT32_C(0x2) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
/*
* This error occurs when TPA block was not configured to
* reserve adequate BDs for TPA operations on this RX
@@ -3174,8 +3384,14 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
(UINT32_C(0x4) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
+ RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/* unused5 is 16 b */
uint16_t unused_4;
/*
@@ -3239,15 +3455,23 @@ struct eject_cmpl {
* records. Odd values indicate 32B
* records.
*/
- #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
- #define EJECT_CMPL_TYPE_SFT 0
+ #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define EJECT_CMPL_TYPE_SFT 0
/*
* Statistics Ejection Completion:
* Completion of statistics data ejection buffer.
* Length = 16B
*/
- #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
- #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
+ #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
+ #define EJECT_CMPL_FLAGS_SFT 6
+ /*
+ * When this bit is '1', it indicates a packet that has an
+ * error of some type. Type of error is indicated in
+ * error_flags.
+ */
+ #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
/*
* This is the length of the statistics data stored in this
* buffer.
@@ -3258,13 +3482,47 @@ struct eject_cmpl {
* buffer corresponds to.
*/
uint32_t opaque;
- uint32_t v;
+ uint16_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
+ #define EJECT_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for statistics ejection. The statistics ejection should
+ * be treated as invalid
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Did Not Fit:
+ * Statistics did not fit into aggregation buffer provided.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
+ (UINT32_C(0x1) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+ /* reserved16 is 16 b */
+ uint16_t reserved16;
/* unused3 is 32 b */
uint32_t unused_2;
} __attribute__((packed));
@@ -3470,6 +3728,24 @@ struct hwrm_async_event_cmpl {
/* Default VNIC Configuration Change */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
UINT32_C(0x35)
+ /* HW flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ /*
+ * A debug notification being posted to the driver. These
+ * notifications are purely for diagnostic purpose and should not be
+ * used for functional purpose. The driver is not supposed to act
+ * on these messages except to log/record it.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
+ UINT32_C(0x37)
+ /*
+ * A trace log message. This contains firmware trace logs string
+ * embedded in the asynchronous message. This is an experimental
+ * event, not meant for production use at this time.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
/* HWRM Error */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
UINT32_C(0xff)
@@ -4111,9 +4387,19 @@ struct hwrm_async_event_cmpl_reset_notify {
/* opaque is 7 b */
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
- /* 8-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 8-lsb timestamp (100-msec resolution)
+ * The Minimum time required for the Firmware readiness after sending this
+ * notification to the driver instances.
+ */
uint8_t timestamp_lo;
- /* 16-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 16-lsb timestamp (100-msec resolution)
+ * The Maximum Firmware Reset bail out value in the order of 100
+ * milli seconds. The driver instances will use this value to re-initiate the
+ * registration process again if the core firmware didn’t set the ready
+ * state bit.
+ */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
@@ -4829,6 +5115,73 @@ struct hwrm_async_event_cmpl_default_vnic_change {
10
} __attribute__((packed));
+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_flow_aged {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of a hw flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates flow ID this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
+ UINT32_C(0x7fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
+ 0
+ /* Indicates flow direction this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x80000000)
+ /*
+ * If this bit set to 0, then it indicates that the aged
+ * event was rx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 31)
+ /*
+ * If this bit is set to 1, then it indicates that the aged
+ * event was tx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
struct hwrm_async_event_cmpl_hwrm_error {
uint16_t type;
@@ -5682,7 +6035,7 @@ struct hwrm_func_qcaps_output {
/*
* If the query is for a VF, then this flag shall be ignored,
* If this query is for a PF and this flag is set to 1,
- * then the PF has the capability to administer another PF.
+ * then the PF has the administrative privilege to configure another PF
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
UINT32_C(0x40000)
@@ -5700,6 +6053,19 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
UINT32_C(0x100000)
+ /*
+ * If 1, then FW has capability to allocate TX rings dynamically
+ * in ring alloc even if PF reserved pool is zero.
+ * This bit will be used only for PFs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x200000)
+ /*
+ * When this bit is '1', it indicates that core firmware is
+ * capable of Hot Reset.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
+ UINT32_C(0x400000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5864,7 +6230,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_func_qcfg_output (size:640b/80B) */
+/* hwrm_func_qcfg_output (size:704b/88B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -5951,6 +6317,13 @@ struct hwrm_func_qcfg_output {
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
UINT32_C(0x40)
+ /*
+ * If set to 1, then secure mode is enabled for this function or device.
+ * If set to 0, then secure mode is disabled (or normal mode) for this
+ * function or device.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
+ UINT32_C(0x80)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5995,7 +6368,8 @@ struct hwrm_func_qcfg_output {
uint16_t alloc_vnics;
/*
* The maximum transmission unit of the function.
- * For rings allocated on this function, this default
+ * If the reported mtu value is non-zero then it will used for the
+ * rings allocated on this function. otherwise the default
* value is used if ring MTU is not specified.
*/
uint16_t mtu;
@@ -6222,7 +6596,27 @@ struct hwrm_func_qcfg_output {
* reserved for itself (since the NQs must be contiguous in HW).
*/
uint16_t alloc_msix;
- uint8_t unused_2[5];
+ /*
+ * The number of registered VF’s associated with the PF. This field
+ * should be ignored when the request received on the VF interface.
+ * This field will be updated on the PF interface to initiate
+ * the unregister request on PF in the HOT Reset Process.
+ */
+ uint16_t registered_vfs;
+ uint8_t unused_1[3];
+ /*
+ * For backward compatibility this field must be set to 1.
+ * Older drivers might look for this field to be 1 before
+ * processing the message.
+ */
+ uint8_t always_1;
+ /*
+ * This GRC address location is used by the Host driver interfaces to poll
+ * the adapter ready state to re-initiate the registration process again
+ * after receiving the RESET Notify event.
+ */
+ uint32_t reset_addr_poll;
+ uint8_t unused_2[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -6424,6 +6818,13 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
+ /*
+ * When this bit it set, even if PF reserved pool size is zero,
+ * FW will allow driver to create TX rings in ring alloc,
+ * by reserving TX ring, S3 node dynamically.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x400000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7181,6 +7582,17 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
UINT32_C(0x8)
+ /*
+ * When this bit is '1', the function is indicating support of
+ * Hot Reset. The driver interface will destroy the resources,
+ * unregister the function and register again up on receiving
+ * the RESET_NOTIFY Async notification from the core firmware.
+ * The core firmware will this use flag and trigger the Hot Reset
+ * process only if all the registered driver instances are capable
+ * of this support.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
+ UINT32_C(0x10)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10774,6 +11186,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
@@ -10878,6 +11292,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
@@ -10930,6 +11346,9 @@ struct hwrm_port_phy_cfg_input {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* This value controls the wirespeed feature. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11159,6 +11578,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
@@ -11238,6 +11659,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
+ UINT32_C(0x4000)
/*
* Current setting of forced link speed.
* When the link speed is not being forced, this
@@ -11267,6 +11691,9 @@ struct hwrm_port_phy_qcfg_output {
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
+ UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11353,6 +11780,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11408,6 +11837,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* Current setting for wirespeed. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11574,8 +12006,20 @@ struct hwrm_port_phy_qcfg_output {
/* 1G_baseCX */
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
UINT32_C(0x1b)
+ /* 100G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
+ UINT32_C(0x1c)
+ /* 100G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
+ UINT32_C(0x1d)
+ /* 100G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
+ UINT32_C(0x1e)
+ /* 100G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
+ UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
+ HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
/* This value represents a media type. */
uint8_t media_type;
/* Unknown */
@@ -21081,6 +21525,15 @@ struct hwrm_cfa_l2_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -21887,6 +22340,15 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22107,6 +22569,12 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22212,6 +22680,12 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22312,6 +22786,12 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22517,8 +22997,14 @@ struct hwrm_cfa_encap_record_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -22872,6 +23358,15 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23381,6 +23876,15 @@ struct hwrm_cfa_em_flow_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23586,13 +24090,13 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_profile_alloc *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23620,266 +24124,1670 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
- */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
/*
- * This bit must be '1' for the src_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
- UINT32_C(0x4)
+ uint16_t reserved1;
/*
- * This bit must be '1' for the dst_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
- UINT32_C(0x8)
- /*
+ uint32_t reserved2;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_meter_profile_free *
+ *******************************/
+
+
+/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_profile_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_meter_profile_cfg *
+ ******************************/
+
+
+/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
+ UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint32_t reserved;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************************
+ * hwrm_cfa_meter_instance_alloc *
+ *********************************/
+
+
+/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
+ UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
+
+
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the src_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x8)
+ /*
* This bit must be '1' for the ovlan_vid field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
- UINT32_C(0x10)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the t_ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the t_ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the ethertype field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the src_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the dst_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the ipaddr_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the ip_protocol field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the src_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the dst_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x10000)
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
+ */
+ uint32_t tunnel_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0;
+ uint16_t unused_1;
+ /*
+ * This value indicates the source MAC address in
+ * the Ethernet header.
+ */
+ uint8_t src_macaddr[6];
+ uint8_t unused_2[2];
/*
- * This bit must be '1' for the ivlan_vid field to be
- * configured.
+ * This value indicates the destination MAC address in
+ * the Ethernet header.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
- UINT32_C(0x20)
+ uint8_t dst_macaddr[6];
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ivlan_vid;
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ivlan_vid;
+ /* This value indicates the ethertype in the Ethernet header. */
+ uint16_t ethertype;
+ /*
+ * This value indicates the type of IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
+ */
+ uint8_t ip_addr_type;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* IPv4 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ UINT32_C(0x4)
+ /* IPv6 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+ UINT32_C(0x6)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ /*
+ * The value of protocol filed in IP header.
+ * Applies to UDP and TCP traffic.
+ * 6 - TCP
+ * 17 - UDP
+ */
+ uint8_t ip_protocol;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+ UINT32_C(0x0)
+ /* TCP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+ UINT32_C(0x6)
+ /* UDP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+ UINT32_C(0x11)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint16_t unused_3;
+ uint32_t unused_4;
+ /*
+ * The value of source IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t src_ipaddr[4];
+ /*
+ * The value of destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t dst_ipaddr[4];
+ /*
+ * The value of source port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t src_port;
+ /*
+ * The value of destination port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t dst_port;
+ /*
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path.
+ */
+ uint16_t dst_id;
+ /*
+ * If set, this value shall represent the L2 context that matches the L2
+ * information of the decap filter.
+ */
+ uint16_t l2_ctxt_ref_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_decap_filter_free *
+ ******************************/
+
+
+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_decap_filter_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_flow_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
+ UINT32_C(0x1)
+ /* num_vlan is 2 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
+ UINT32_C(0x6)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
+ /* no tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
+ (UINT32_C(0x0) << 1)
+ /* 1 tag */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
+ (UINT32_C(0x1) << 1)
+ /* 2 tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
+ (UINT32_C(0x2) << 1)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
+ /* Enumeration denoting the Flow Type. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
+ UINT32_C(0x38)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
+ /* L2 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
+ (UINT32_C(0x0) << 3)
+ /* IPV4 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
+ (UINT32_C(0x1) << 3)
+ /* IPV6 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
+ (UINT32_C(0x2) << 3)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
/*
- * This bit must be '1' for the t_ovlan_vid field to be
- * configured.
+ * when set to 1, indicates TX flow offload for function specified in src_fid and
+ * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
+ * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
+ * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
+ * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
+ * belong to the children VFs of the same PF to indicate VM to VM flow.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
UINT32_C(0x40)
/*
- * This bit must be '1' for the t_ivlan_vid field to be
- * configured.
+ * when set to 1, indicates RX flow offload for function specified in dst_fid and
+ * the src_fid should be set to invalid value.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x80)
/*
- * This bit must be '1' for the ethertype field to be
- * configured.
+ * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
+ * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
+ * This flag is only valid when the flow direction is RX.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
/*
- * This bit must be '1' for the src_ipaddr field to be
- * configured.
+ * Tx Flow: vf fid.
+ * Rx Flow: pf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ uint16_t src_fid;
+ /* Tunnel handle valid when tunnel flag is set. */
+ uint32_t tunnel_handle;
+ uint16_t action_flags;
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* recycle is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* meter is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /* nat_src is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
+ UINT32_C(0x20)
+ /* nat_dest is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
+ UINT32_C(0x40)
+ /* nat_ipv4_address is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
+ UINT32_C(0x80)
+ /* l2_header_rewrite is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
+ UINT32_C(0x100)
+ /* ttl_decrement is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
UINT32_C(0x200)
/*
- * This bit must be '1' for the dst_ipaddr field to be
- * configured.
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header. The type of tunnel
+ * is specified in the tunnel_type field.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
UINT32_C(0x400)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x800)
/*
- * This bit must be '1' for the ipaddr_type field to be
- * configured.
+ * Tx Flow: pf or vf fid.
+ * Rx Flow: vf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
- UINT32_C(0x800)
+ uint16_t dst_fid;
+ /* VLAN tpid, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tci;
+ /* Meter id, valid when meter flag is set. */
+ uint16_t act_meter_id;
+ /* Flow with the same l2 context tcam key. */
+ uint16_t ref_flow_handle;
+ /* This value sets the match value for the ethertype. */
+ uint16_t ethertype;
+ /* valid when num tags is 1 or 2. */
+ uint16_t outer_vlan_tci;
+ /* This value sets the match value for the Destination MAC address. */
+ uint16_t dmac[3];
+ /* valid when num tags is 2. */
+ uint16_t inner_vlan_tci;
+ /* This value sets the match value for the Source MAC address. */
+ uint16_t smac[3];
+ /* The bit length of destination IP address mask. */
+ uint8_t ip_dst_mask_len;
+ /* The bit length of source IP address mask. */
+ uint8_t ip_src_mask_len;
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
/*
- * This bit must be '1' for the ip_protocol field to be
- * configured.
+ * The value of source port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
- UINT32_C(0x1000)
+ uint16_t l4_src_port;
/*
- * This bit must be '1' for the src_port field to be
- * configured.
+ * The value of source port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
- UINT32_C(0x2000)
+ uint16_t l4_src_port_mask;
/*
- * This bit must be '1' for the dst_port field to be
- * configured.
+ * The value of destination port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
- UINT32_C(0x4000)
+ uint16_t l4_dst_port;
/*
- * This bit must be '1' for the dst_id field to be
- * configured.
+ * The value of destination port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x8000)
+ uint16_t l4_dst_port_mask;
/*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
+ * NAT IPv4/6 address based on address type flag.
+ * 0 values are ignored.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x10000)
+ uint32_t nat_ip_address[4];
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
/*
- * Tunnel identifier.
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
+ * The NAT source/destination port based on direction flag.
+ * Applies to UDP and TCP traffic.
+ * 0 values are ignored.
*/
- uint32_t tunnel_id;
+ uint16_t nat_port;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* The value of ip protocol. */
+ uint8_t ip_proto;
/* Tunnel Type. */
uint8_t tunnel_type;
/* Non-tunnel */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
/* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
UINT32_C(0x3)
/* IP in IP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
/* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
UINT32_C(0x7)
/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
UINT32_C(0x8)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0;
- uint16_t unused_1;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
+struct hwrm_cfa_flow_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[2];
/*
- * This value indicates the source MAC address in
- * the Ethernet header.
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_free *
+ **********************/
+
+
+/* hwrm_cfa_flow_free_input (size:256b/32B) */
+struct hwrm_cfa_flow_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t src_macaddr[6];
- uint8_t unused_2[2];
+ uint16_t cmpl_ring;
/*
- * This value indicates the destination MAC address in
- * the Ethernet header.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t dst_macaddr[6];
+ uint16_t seq_id;
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the Ethernet header.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t ovlan_vid;
+ uint16_t target_id;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the Ethernet header.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t ivlan_vid;
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_free_output (size:256b/32B) */
+struct hwrm_cfa_flow_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* packet is 64 b */
+ uint64_t packet;
+ /* byte is 64 b */
+ uint64_t byte;
+ uint8_t unused_0[7];
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the tunnel Ethernet header.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t t_ovlan_vid;
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_info *
+ **********************/
+
+
+/* hwrm_cfa_flow_info_input (size:256b/32B) */
+struct hwrm_cfa_flow_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the tunnel Ethernet header.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t t_ivlan_vid;
- /* This value indicates the ethertype in the Ethernet header. */
- uint16_t ethertype;
+ uint16_t cmpl_ring;
/*
- * This value indicates the type of IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t ip_addr_type;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* IPv4 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
- UINT32_C(0x4)
- /* IPv6 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
- UINT32_C(0x6)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ uint16_t seq_id;
/*
- * The value of protocol filed in IP header.
- * Applies to UDP and TCP traffic.
- * 6 - TCP
- * 17 - UDP
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint8_t ip_protocol;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
- UINT32_C(0x0)
- /* TCP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
- UINT32_C(0x6)
- /* UDP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
- UINT32_C(0x11)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
- uint16_t unused_3;
- uint32_t unused_4;
+ uint16_t target_id;
/*
- * The value of source IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t src_ipaddr[4];
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ /* Max flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
+ UINT32_C(0xfff)
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
+ /* CNP flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
+ UINT32_C(0x1000)
+ /* RoCEv1 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
+ UINT32_C(0x2000)
+ /* RoCEv2 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
+ UINT32_C(0x4000)
+ /* Direction rx = 1 */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
+ UINT32_C(0x8000)
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_info_output (size:448b/56B) */
+struct hwrm_cfa_flow_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* flags is 8 b */
+ uint8_t flags;
+ /* profile is 8 b */
+ uint8_t profile;
+ /* src_fid is 16 b */
+ uint16_t src_fid;
+ /* dst_fid is 16 b */
+ uint16_t dst_fid;
+ /* l2_ctxt_id is 16 b */
+ uint16_t l2_ctxt_id;
+ /* em_info is 64 b */
+ uint64_t em_info;
+ /* tcam_info is 64 b */
+ uint64_t tcam_info;
+ /* vfp_tcam_info is 64 b */
+ uint64_t vfp_tcam_info;
+ /* ar_id is 16 b */
+ uint16_t ar_id;
+ /* flow_handle is 16 b */
+ uint16_t flow_handle;
+ /* tunnel_handle is 32 b */
+ uint32_t tunnel_handle;
+ /* The flow aging timer for the flow, the unit is 100 milliseconds */
+ uint16_t flow_timer;
+ uint8_t unused_0[5];
/*
- * The value of destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint32_t dst_ipaddr[4];
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_flush *
+ ***********************/
+
+
+/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+struct hwrm_cfa_flow_flush_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * The value of source port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t src_port;
+ uint16_t cmpl_ring;
/*
- * The value of destination port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t dst_port;
+ uint16_t seq_id;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t dst_id;
+ uint16_t target_id;
/*
- * If set, this value shall represent the L2 context that matches the L2
- * information of the decap filter.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t l2_ctxt_ref_id;
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_alloc_output {
+/* hwrm_cfa_flow_flush_output (size:128b/16B) */
+struct hwrm_cfa_flow_flush_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23888,9 +25796,7 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -23901,13 +25807,13 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_decap_filter_free *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_stats *
+ ***********************/
-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_decap_filter_free_input {
+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
+struct hwrm_cfa_flow_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23935,13 +25841,53 @@ struct hwrm_cfa_decap_filter_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[4];
+ /* Flow handle. */
+ uint16_t num_flows;
+ /* Flow handle. */
+ uint16_t flow_handle_0;
+ /* Flow handle. */
+ uint16_t flow_handle_1;
+ /* Flow handle. */
+ uint16_t flow_handle_2;
+ /* Flow handle. */
+ uint16_t flow_handle_3;
+ /* Flow handle. */
+ uint16_t flow_handle_4;
+ /* Flow handle. */
+ uint16_t flow_handle_5;
+ /* Flow handle. */
+ uint16_t flow_handle_6;
+ /* Flow handle. */
+ uint16_t flow_handle_7;
+ /* Flow handle. */
+ uint16_t flow_handle_8;
+ /* Flow handle. */
+ uint16_t flow_handle_9;
+ uint8_t unused_0[2];
+ /* Flow ID of a flow. */
+ uint32_t flow_id_0;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_1;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_2;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_3;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_4;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_5;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_6;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_7;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_8;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_9;
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_free_output {
+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
+struct hwrm_cfa_flow_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23950,6 +25896,46 @@ struct hwrm_cfa_decap_filter_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* packet_0 is 64 b */
+ uint64_t packet_0;
+ /* packet_1 is 64 b */
+ uint64_t packet_1;
+ /* packet_2 is 64 b */
+ uint64_t packet_2;
+ /* packet_3 is 64 b */
+ uint64_t packet_3;
+ /* packet_4 is 64 b */
+ uint64_t packet_4;
+ /* packet_5 is 64 b */
+ uint64_t packet_5;
+ /* packet_6 is 64 b */
+ uint64_t packet_6;
+ /* packet_7 is 64 b */
+ uint64_t packet_7;
+ /* packet_8 is 64 b */
+ uint64_t packet_8;
+ /* packet_9 is 64 b */
+ uint64_t packet_9;
+ /* byte_0 is 64 b */
+ uint64_t byte_0;
+ /* byte_1 is 64 b */
+ uint64_t byte_1;
+ /* byte_2 is 64 b */
+ uint64_t byte_2;
+ /* byte_3 is 64 b */
+ uint64_t byte_3;
+ /* byte_4 is 64 b */
+ uint64_t byte_4;
+ /* byte_5 is 64 b */
+ uint64_t byte_5;
+ /* byte_6 is 64 b */
+ uint64_t byte_6;
+ /* byte_7 is 64 b */
+ uint64_t byte_7;
+ /* byte_8 is 64 b */
+ uint64_t byte_8;
+ /* byte_9 is 64 b */
+ uint64_t byte_9;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -23961,13 +25947,13 @@ struct hwrm_cfa_decap_filter_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_alloc *
- ***********************/
+/***********************************
+ * hwrm_cfa_flow_aging_timer_reset *
+ ***********************************/
-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_flow_alloc_input {
+/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_timer_reset_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23989,219 +25975,21 @@ struct hwrm_cfa_flow_alloc_input {
*/
uint16_t target_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint16_t flags;
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
- UINT32_C(0x1)
- /* num_vlan is 2 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
- UINT32_C(0x6)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
- /* no tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
- (UINT32_C(0x0) << 1)
- /* 1 tag */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
- (UINT32_C(0x1) << 1)
- /* 2 tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
- (UINT32_C(0x2) << 1)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
- /* Enumeration denoting the Flow Type. */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
- UINT32_C(0x38)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
- /* L2 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
- (UINT32_C(0x0) << 3)
- /* IPV4 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
- (UINT32_C(0x1) << 3)
- /* IPV6 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
- (UINT32_C(0x2) << 3)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
- /*
- * when set to 1, indicates TX flow offload for function specified in src_fid and
- * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
- * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
- * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
- * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
- * belong to the children VFs of the same PF to indicate VM to VM flow.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x40)
- /*
- * when set to 1, indicates RX flow offload for function specified in dst_fid and
- * the src_fid should be set to invalid value.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x80)
- /*
- * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
- * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
- * This flag is only valid when the flow direction is RX.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
- UINT32_C(0x100)
- /*
- * Tx Flow: vf fid.
- * Rx Flow: pf fid.
- */
- uint16_t src_fid;
- /* Tunnel handle valid when tunnel flag is set. */
- uint32_t tunnel_handle;
- uint16_t action_flags;
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
- UINT32_C(0x1)
- /* recycle is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
- UINT32_C(0x4)
- /* meter is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
- UINT32_C(0x8)
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
- UINT32_C(0x10)
- /* nat_src is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
- UINT32_C(0x20)
- /* nat_dest is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
- UINT32_C(0x40)
- /* nat_ipv4_address is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
- UINT32_C(0x80)
- /* l2_header_rewrite is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
- UINT32_C(0x100)
- /* ttl_decrement is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
- UINT32_C(0x200)
- /*
- * If set to 1 and flow direction is TX, it indicates decap of L2 header
- * and encap of tunnel header. If set to 1 and flow direction is RX, it
- * indicates decap of tunnel header and encap L2 header. The type of tunnel
- * is specified in the tunnel_type field.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
- UINT32_C(0x400)
- /*
- * Tx Flow: pf or vf fid.
- * Rx Flow: vf fid.
- */
- uint16_t dst_fid;
- /* VLAN tpid, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tpid;
- /* VLAN tci, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tci;
- /* Meter id, valid when meter flag is set. */
- uint16_t act_meter_id;
- /* Flow with the same l2 context tcam key. */
- uint16_t ref_flow_handle;
- /* This value sets the match value for the ethertype. */
- uint16_t ethertype;
- /* valid when num tags is 1 or 2. */
- uint16_t outer_vlan_tci;
- /* This value sets the match value for the Destination MAC address. */
- uint16_t dmac[3];
- /* valid when num tags is 2. */
- uint16_t inner_vlan_tci;
- /* This value sets the match value for the Source MAC address. */
- uint16_t smac[3];
- /* The bit length of destination IP address mask. */
- uint8_t ip_dst_mask_len;
- /* The bit length of source IP address mask. */
- uint8_t ip_src_mask_len;
- /* The value of destination IPv4/IPv6 address. */
- uint32_t ip_dst[4];
- /* The source IPv4/IPv6 address. */
- uint32_t ip_src[4];
- /*
- * The value of source port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port;
- /*
- * The value of source port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port_mask;
- /*
- * The value of destination port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port;
- /*
- * The value of destination port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port_mask;
- /*
- * NAT IPv4/6 address based on address type flag.
- * 0 values are ignored.
- */
- uint32_t nat_ip_address[4];
- /* L2 header re-write Destination MAC address. */
- uint16_t l2_rewrite_dmac[3];
- /*
- * The NAT source/destination port based on direction flag.
- * Applies to UDP and TCP traffic.
- * 0 values are ignored.
- */
- uint16_t nat_port;
- /* L2 header re-write Source MAC address. */
- uint16_t l2_rewrite_smac[3];
- /* The value of ip protocol. */
- uint8_t ip_proto;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
-struct hwrm_cfa_flow_alloc_output {
+/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_timer_reset_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24210,20 +25998,7 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[2];
- /*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
- */
- uint32_t flow_id;
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24234,13 +26009,13 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_flow_free *
- **********************/
+/***************************
+ * hwrm_cfa_flow_aging_cfg *
+ ***************************/
-/* hwrm_cfa_flow_free_input (size:256b/32B) */
-struct hwrm_cfa_flow_free_input {
+/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24268,15 +26043,38 @@ struct hwrm_cfa_flow_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[6];
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
+ /* The bit field to enable per flow aging configuration. */
+ uint16_t enables;
+ /* This bit must be '1' for the tcp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
+ UINT32_C(0x1)
+ /* This bit must be '1' for the tcp finish timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
+ UINT32_C(0x2)
+ /* This bit must be '1' for the udp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
+ UINT32_C(0x4)
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_flow_timer;
+ /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_fin_timer;
+ /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
+ uint32_t udp_flow_timer;
} __attribute__((packed));
-/* hwrm_cfa_flow_free_output (size:256b/32B) */
-struct hwrm_cfa_flow_free_output {
+/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24285,10 +26083,6 @@ struct hwrm_cfa_flow_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet is 64 b */
- uint64_t packet;
- /* byte is 64 b */
- uint64_t byte;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24300,13 +26094,13 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_flush *
- ***********************/
+/****************************
+ * hwrm_cfa_flow_aging_qcfg *
+ ****************************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
-struct hwrm_cfa_flow_flush_input {
+/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24334,12 +26128,21 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- uint8_t unused_0[4];
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_flush_output (size:128b/16B) */
-struct hwrm_cfa_flow_flush_output {
+/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24348,7 +26151,13 @@ struct hwrm_cfa_flow_flush_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_flow_timer;
+ /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_fin_timer;
+ /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t udp_flow_timer;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24359,13 +26168,13 @@ struct hwrm_cfa_flow_flush_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_stats *
- ***********************/
+/*****************************
+ * hwrm_cfa_flow_aging_qcaps *
+ *****************************/
-/* hwrm_cfa_flow_stats_input (size:640b/80B) */
-struct hwrm_cfa_flow_stats_input {
+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24393,53 +26202,21 @@ struct hwrm_cfa_flow_stats_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow handle. */
- uint16_t num_flows;
- /* Flow handle. */
- uint16_t flow_handle_0;
- /* Flow handle. */
- uint16_t flow_handle_1;
- /* Flow handle. */
- uint16_t flow_handle_2;
- /* Flow handle. */
- uint16_t flow_handle_3;
- /* Flow handle. */
- uint16_t flow_handle_4;
- /* Flow handle. */
- uint16_t flow_handle_5;
- /* Flow handle. */
- uint16_t flow_handle_6;
- /* Flow handle. */
- uint16_t flow_handle_7;
- /* Flow handle. */
- uint16_t flow_handle_8;
- /* Flow handle. */
- uint16_t flow_handle_9;
- uint8_t unused_0[2];
- /* Flow ID of a flow. */
- uint32_t flow_id_0;
- /* Flow ID of a flow. */
- uint32_t flow_id_1;
- /* Flow ID of a flow. */
- uint32_t flow_id_2;
- /* Flow ID of a flow. */
- uint32_t flow_id_3;
- /* Flow ID of a flow. */
- uint32_t flow_id_4;
- /* Flow ID of a flow. */
- uint32_t flow_id_5;
- /* Flow ID of a flow. */
- uint32_t flow_id_6;
- /* Flow ID of a flow. */
- uint32_t flow_id_7;
- /* Flow ID of a flow. */
- uint32_t flow_id_8;
- /* Flow ID of a flow. */
- uint32_t flow_id_9;
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
-struct hwrm_cfa_flow_stats_output {
+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_flow_aging_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24448,46 +26225,14 @@ struct hwrm_cfa_flow_stats_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet_0 is 64 b */
- uint64_t packet_0;
- /* packet_1 is 64 b */
- uint64_t packet_1;
- /* packet_2 is 64 b */
- uint64_t packet_2;
- /* packet_3 is 64 b */
- uint64_t packet_3;
- /* packet_4 is 64 b */
- uint64_t packet_4;
- /* packet_5 is 64 b */
- uint64_t packet_5;
- /* packet_6 is 64 b */
- uint64_t packet_6;
- /* packet_7 is 64 b */
- uint64_t packet_7;
- /* packet_8 is 64 b */
- uint64_t packet_8;
- /* packet_9 is 64 b */
- uint64_t packet_9;
- /* byte_0 is 64 b */
- uint64_t byte_0;
- /* byte_1 is 64 b */
- uint64_t byte_1;
- /* byte_2 is 64 b */
- uint64_t byte_2;
- /* byte_3 is 64 b */
- uint64_t byte_3;
- /* byte_4 is 64 b */
- uint64_t byte_4;
- /* byte_5 is 64 b */
- uint64_t byte_5;
- /* byte_6 is 64 b */
- uint64_t byte_6;
- /* byte_7 is 64 b */
- uint64_t byte_7;
- /* byte_8 is 64 b */
- uint64_t byte_8;
- /* byte_9 is 64 b */
- uint64_t byte_9;
+ /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_flow_timer;
+ /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_fin_timer;
+ /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t max_udp_flow_timer;
+ /* The maximum aging flows that HW can support. */
+ uint32_t max_aging_flows;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24706,6 +26451,12 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24765,8 +26516,14 @@ struct hwrm_tunnel_dst_port_query_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0[7];
} __attribute__((packed));
@@ -24857,8 +26614,14 @@ struct hwrm_tunnel_dst_port_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* This field represents the value of L4 destination port used
@@ -24948,8 +26711,14 @@ struct hwrm_tunnel_dst_port_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -25025,6 +26794,52 @@ struct ctx_hw_stats {
uint64_t tpa_aborts;
} __attribute__((packed));
+/* Periodic Engine statistics context DMA to host. */
+/* ctx_eng_stats (size:512b/64B) */
+struct ctx_eng_stats {
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+} __attribute__((packed));
+
/***********************
* hwrm_stat_ctx_alloc *
***********************/
@@ -25081,7 +26896,7 @@ struct hwrm_stat_ctx_alloc_input {
* than offloaded RoCE traffic shall not be included in this
* statistic context.
* When this bit is set to '0', the statistics context shall be
- * used for the network traffic other than offloaded RoCE traffic.
+ * used for network traffic or engine traffic.
*/
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
uint8_t unused_0[3];
@@ -25272,6 +27087,107 @@ struct hwrm_stat_ctx_query_output {
uint8_t valid;
} __attribute__((packed));
+/***************************
+ * hwrm_stat_ctx_eng_query *
+ ***************************/
+
+
+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_eng_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
+struct hwrm_stat_ctx_eng_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***************************
* hwrm_stat_ctx_clr_stats *
***************************/
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v3 7/8] net/bnxt: update HWRM API to version 1.10.0.48
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
` (5 preceding siblings ...)
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM version to 1.10.0.48
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3156 +++++++++++++++++++++---
1 file changed, 2874 insertions(+), 282 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index ea9a7d40e..00a8ff87e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -260,6 +260,7 @@ struct cmd_nums {
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
+ #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
@@ -372,6 +373,8 @@ struct cmd_nums {
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
+ #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
+ #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
@@ -397,6 +400,8 @@ struct cmd_nums {
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
/* Experimental */
+ #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
+ /* Experimental */
#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
@@ -407,6 +412,8 @@ struct cmd_nums {
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
/* Experimental */
+ #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
+ /* Experimental */
#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
/* Experimental */
#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
@@ -451,6 +458,34 @@ struct cmd_nums {
#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
+ /* Experimental */
+ #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
+ /* Experimental */
+ #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
+ /* Experimental */
+ #define HWRM_CFA_EEM_OP UINT32_C(0x123)
+ /* Experimental */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -469,6 +504,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
/* Engine CKV - Generate and encrypt a new AES key. */
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
+ /* Engine CKV - Configure a label index with a label value. */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -523,6 +560,8 @@ struct cmd_nums {
#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
/* Engine - Set the on-die RQE credit update location. */
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
+ /* Engine - Query the engine function configuration. */
+ #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
/* Experimental */
#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
/* Experimental */
@@ -573,6 +612,10 @@ struct cmd_nums {
/* */
#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
/* Experimental */
+ #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
+ /* Experimental */
+ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
+ /* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
#define HWRM_NVM_FLUSH UINT32_C(0xfff0)
@@ -724,8 +767,8 @@ struct hwrm_err_output {
#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
/* hwrm_func_buf_rgtr */
#define HWRM_MAX_REQ_LEN 128
-/* hwrm_selftest_qlist */
-#define HWRM_MAX_RESP_LEN 280
+/* hwrm_cfa_flow_info */
+#define HWRM_MAX_RESP_LEN 704
/* 7 bit indirection table index. */
#define HW_HASH_INDEX_SIZE 0x80
#define HW_HASH_KEY_SIZE 40
@@ -735,8 +778,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 19
-#define HWRM_VERSION_STR "1.10.0.19"
+#define HWRM_VERSION_RSVD 48
+#define HWRM_VERSION_STR "1.10.0.48"
/****************
* hwrm_ver_get *
@@ -993,6 +1036,32 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
UINT32_C(0x200)
+ /*
+ * If set to 1, firmware is capable to support advanced flow counters like,
+ * Meter drop counters and EEM counters.
+ * If set to 0, firmware is not capable to support advanced flow counters.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * If set to 1, the firmware is able to support the use of the CFA
+ * Extended Exact Match(EEM) feature.
+ * If set to 0, firmware is not capable to support the use of the
+ * CFA EEM feature.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
+ UINT32_C(0x800)
+ /*
+ * If set to 1, the firmware is able to support advance CFA flow management
+ * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
+ * If set to 0, then the firmware doesn’t support the advance CFA flow management
+ * features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
+ UINT32_C(0x1000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -3695,6 +3764,9 @@ struct hwrm_async_event_cmpl {
/* Reset notification to clients */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
UINT32_C(0x8)
+ /* Master function selection event */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
/* Function driver unloaded */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
UINT32_C(0x10)
@@ -3739,6 +3811,40 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
UINT32_C(0x37)
+ /*
+ * A EEM flow cached memory flush request event being posted to the PF
+ * driver.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ /*
+ * A EEM flow cache memory flush completion event being posted to the
+ * firmware by the PF driver. This is indication that host EEM flush
+ * has completed by the PF.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ /*
+ * A tcp flag action change event being posted to the PF or trusted VF
+ * driver by the firmware. The PF or trusted VF driver should query
+ * the firmware for the new TCP flag action update after receiving
+ * this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ /*
+ * A eem flow active event being posted to the PF or trusted VF driver
+ * by the firmware. The PF or trusted VF driver should update the
+ * flow's aging timer after receiving this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ /*
+ * A eem cfg change event being posted to the trusted VF driver by the
+ * firmware if the parent PF EEM configuration changed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -4450,6 +4556,75 @@ struct hwrm_async_event_cmpl_reset_notify {
16
} __attribute__((packed));
+/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_recovery {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message can be used for selecting or
+ * deselecting master function for error recovery,
+ * and to communicate to all the functions whether error recovery
+ * was enabled/disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates driver action requested */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
+ 0
+ /*
+ * If set to 1, this function is selected as Master function.
+ * This function has responsibility to do 'chip reset' when it
+ * detects a fatal error. If set to 0, master function functionality
+ * is disabled on this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, error recovery is enabled.
+ * If set to 0, error recovery is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
struct hwrm_async_event_cmpl_func_drvr_unload {
uint16_t type;
@@ -5182,8 +5357,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {
HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
} __attribute__((packed));
-/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
-struct hwrm_async_event_cmpl_hwrm_error {
+/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_req {
uint16_t type;
/*
* This field indicates the exact type of the completion.
@@ -5192,133 +5367,549 @@ struct hwrm_async_event_cmpl_hwrm_error {
* records. Odd values indicate 32B
* records.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
UINT32_C(0x3f)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
+ 0
/* HWRM Asynchronous Event Information */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
UINT32_C(0x2e)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
/* Identifiers of events. */
uint16_t event_id;
- /* HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Notification of a eem_cache_flush request */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
/* Event specific data */
uint32_t event_data2;
- /* Severity of HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
- /* Warning */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
- UINT32_C(0x0)
- /* Non-fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
- UINT32_C(0x1)
- /* Fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
- UINT32_C(0x2)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
+ UINT32_C(0x1)
/* opaque is 7 b */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
/* 8-lsb timestamp from POR (100-msec resolution) */
uint8_t timestamp_lo;
/* 16-lsb timestamp from POR (100-msec resolution) */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
- /* Time stamp for error event */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
- UINT32_C(0x1)
} __attribute__((packed));
-/*******************
- * hwrm_func_reset *
- *******************/
-
-
-/* hwrm_func_reset_input (size:192b/24B) */
-struct hwrm_func_reset_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_done {
+ uint16_t type;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t cmpl_ring;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Notification of a host eem_cache_flush has completed. This event
+ * is generated by the host driver.
*/
- uint16_t seq_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- uint16_t target_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates function ID that this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
+ 0
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_tcp_flag_action_change {
+ uint16_t type;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint64_t resp_addr;
- uint32_t enables;
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of tcp flag action change */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * This bit must be '1' for the vf_id_valid field to be
- * configured.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_flow_active {
+ uint16_t type;
/*
- * The ID of the VF that this PF is trying to reset.
- * Only the parent PF shall be allowed to reset a child VF.
- *
- * A parent PF driver shall use this field only when a specific child VF
- * is requested to be reset.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t vf_id;
- /* This value indicates the level of a function reset. */
- uint8_t func_reset_level;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of an active eem flow */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Indicates the 2nd global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
+ 0
/*
- * Reset the caller function and its children VFs (if any). If no
- * children functions exist, then reset the caller function only.
- */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
- UINT32_C(0x0)
- /* Reset the caller function only */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
- UINT32_C(0x1)
+ * Indicates flow direction of the flow identified by
+ * the global_id_2.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
+ uint8_t opaque_v;
/*
- * Reset all children VFs of the caller function driver if the
- * caller is a PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver with
- * no children VFs.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
- UINT32_C(0x2)
- /*
- * Reset a specific VF of the caller function driver if the caller
- * is the parent PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver that is not
- * the parent of the VF that is being requested to reset.
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the 1st global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
+ 0
+ /*
+ * Indicates flow direction of the flow identified by the
+ * global_id_1.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this is rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this is tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
+ /*
+ * Indicates EEM flow aging mode this event occured on. If
+ * this bit is set to 0, the event_data1 is the EEM global
+ * ID. If this bit is set to 1, the event_data1 is the number
+ * of global ID in the context memory.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
+ UINT32_C(0x80000000)
+ /* EEM flow aging mode 0. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
+ (UINT32_C(0x0) << 31)
+ /* EEM flow aging mode 1. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cfg_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of EEM configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Value of 1 to indicate EEM TX configuration is enabled. Value of
+ * 0 to indicate the EEM TX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
+ * to indicate the EEM RX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
+struct hwrm_async_event_cmpl_fw_trace_msg {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Firmware trace log message */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
+ /* Trace byte 0 to 3 */
+ uint32_t event_data2;
+ /* Trace byte0 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
+ /* Trace byte1 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
+ /* Trace byte2 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
+ /* Trace byte3 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
+ /* Trace flags */
+ uint8_t timestamp_lo;
+ /* Indicates if the string is partial or complete. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
+ UINT32_C(0x1)
+ /* Complete string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
+ UINT32_C(0x0)
+ /* Partial string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
+ UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
+ /* Indicates the firmware that sent the trace message. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
+ UINT32_C(0x2)
+ /* Primary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
+ (UINT32_C(0x0) << 1)
+ /* Secondary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
+ /* Trace byte 4 to 5 */
+ uint16_t timestamp_hi;
+ /* Trace byte4 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
+ /* Trace byte5 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
+ /* Trace byte 6 to 9 */
+ uint32_t event_data1;
+ /* Trace byte6 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
+ /* Trace byte7 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
+ /* Trace byte8 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
+ /* Trace byte9 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
+struct hwrm_async_event_cmpl_hwrm_error {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Severity of HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
+ /* Warning */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
+ UINT32_C(0x0)
+ /* Non-fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
+ UINT32_C(0x1)
+ /* Fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Time stamp for error event */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
+ UINT32_C(0x1)
+} __attribute__((packed));
+
+/*******************
+ * hwrm_func_reset *
+ *******************/
+
+
+/* hwrm_func_reset_input (size:192b/24B) */
+struct hwrm_func_reset_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vf_id_valid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ /*
+ * The ID of the VF that this PF is trying to reset.
+ * Only the parent PF shall be allowed to reset a child VF.
+ *
+ * A parent PF driver shall use this field only when a specific child VF
+ * is requested to be reset.
+ */
+ uint16_t vf_id;
+ /* This value indicates the level of a function reset. */
+ uint8_t func_reset_level;
+ /*
+ * Reset the caller function and its children VFs (if any). If no
+ * children functions exist, then reset the caller function only.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
+ UINT32_C(0x0)
+ /* Reset the caller function only */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
+ UINT32_C(0x1)
+ /*
+ * Reset all children VFs of the caller function driver if the
+ * caller is a PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver with
+ * no children VFs.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
+ UINT32_C(0x2)
+ /*
+ * Reset a specific VF of the caller function driver if the caller
+ * is the parent PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver that is not
+ * the parent of the VF that is being requested to reset.
*/
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
UINT32_C(0x3)
@@ -6066,6 +6657,12 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
UINT32_C(0x400000)
+ /*
+ * This flag will be set to 1 by the FW if FW supports adapter error
+ * recovery.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
+ UINT32_C(0x800000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6813,8 +7410,7 @@ struct hwrm_func_cfg_input {
* resident HWRM clients, only the parent PF driver shall be allowed
* to initiate this change on one of its children VFs. If this bit is
* set to 1, then the VF that is being configured is requested to be
- * trusted. If this bit is set to 0, then the VF that is being configured
- * is requested to be not trusted.
+ * trusted.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
@@ -6825,6 +7421,25 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
UINT32_C(0x400000)
+ /*
+ * This bit requests that the firmware test to see if all the assets
+ * requested in this command (i.e. number of NQ rings) are available.
+ * The firmware will return an error if the requested assets are
+ * not available. The firwmare will NOT reserve the assets if they
+ * are available.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
+ UINT32_C(0x800000)
+ /*
+ * This configuration change can be initiated by a PF driver. This
+ * configuration request shall be targeted to a VF. From local host
+ * resident HWRM clients, only the parent PF driver shall be allowed
+ * to initiate this change on one of its children VFs. If this bit is
+ * set to 1, then the VF that is being configured is requested to be
+ * untrusted.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
+ UINT32_C(0x1000000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7593,6 +8208,19 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
UINT32_C(0x10)
+ /*
+ * When this bit is 1, the function is indicating the support of the
+ * error recovery capability. Error recovery support will be used by
+ * firmware only if all the driver instances support error recovery
+ * process. By setting this bit, driver is indicating support for
+ * corresponding async event completion message. These will be
+ * delivered to the driver even if they did not register for it.
+ * If supported, after receiving reset notify async event with fatal
+ * flag set in event data1, then all the drivers have to tear down
+ * their resources without sending any HWRM commands to FW.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
+ UINT32_C(0x20)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10270,17 +10898,384 @@ struct hwrm_func_backing_store_qcfg_output {
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as 1
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
*/
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/****************************
+ * hwrm_error_recovery_qcfg *
+ ****************************/
+
+
+/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
+struct hwrm_error_recovery_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __attribute__((packed));
+
+/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
+struct hwrm_error_recovery_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When this flag is set to 1, error recovery will be initiated
+ * through master function driver.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
+ /*
+ * When this flag is set to 1, error recovery will be performed
+ * through Co processor.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
+ /*
+ * Driver Polling frequency. This value is in units of 100msec.
+ * Typical value would be 10 to indicate 1sec.
+ * Drivers can poll FW health status, Heartbeat, reset_counter with
+ * this frequency.
+ */
+ uint32_t driver_polling_freq;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 30 to indicate 3sec.
+ * Master function wait period from detecting a fatal error to
+ * initiating reset. In this time period Master PF expects every
+ * active driver will detect fatal error.
+ */
+ uint32_t master_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 50 to indicate 5sec.
+ * Normal function wait period from fatal error detection to
+ * polling FW health status. In this time period, drivers should not
+ * do any PCIe MMIO transaction and should not send any HWRM commands.
+ */
+ uint32_t normal_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 20 to indicate 2sec.
+ * This field indicates that, master function wait period after chip
+ * reset. After this time, master function should reinitialize with
+ * FW.
+ */
+ uint32_t master_func_wait_period_after_reset;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 60 to indicate 6sec.
+ * This field is applicable to both master and normal functions.
+ * Even after chip reset, if FW status not changed to ready,
+ * then all the functions can poll for this much time and bailout.
+ */
+ uint32_t max_bailout_time_after_reset;
+ /*
+ * FW health status register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates upper 30bits of the register address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_health_status_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
+ 2
+ /*
+ * FW HeartBeat register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_heartbeat_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
+ 2
+ /*
+ * FW reset counter.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_reset_cnt_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
+ 2
+ /*
+ * Reset Inprogress Register address for PFs.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_inprogress_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
+ 2
+ /* This field indicates the mask value for reset_inprogress_reg. */
+ uint32_t reset_inprogress_reg_mask;
+ uint8_t unused_0[3];
+ /*
+ * Array of registers and value count to reset the Chip
+ * Each array count has reset_reg, reset_reg_val, delay_after_reset
+ * in TLV format. Depending upon Chip type, number of reset registers
+ * will vary. Drivers have to write reset_reg_val in the reset_reg
+ * location in the same sequence in order to recover from a fatal
+ * error.
+ */
+ uint8_t reg_array_cnt;
+ /*
+ * Reset register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_reg[16];
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
+ /* Value to be written in reset_reg to reset the controller. */
+ uint32_t reset_reg_val[16];
+ /*
+ * This value is in units of 1msec.
+ * Typical value would be 10 to indicate 10msec.
+ * Some of the operations like Core reset require delay before
+ * accessing PCIE MMIO register space.
+ * If this value is non-zero, drivers have to wait for
+ * this much time after writing reset_reg_val in reset_reg.
+ */
+ uint8_t delay_after_reset[16];
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
@@ -10894,6 +11889,12 @@ struct hwrm_func_drv_if_change_output {
*/
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that the firmware got changed / reset.
+ * The driver should do complete re-initialization when that bit is set.
+ */
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
+ UINT32_C(0x2)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -14166,6 +15167,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for autonegotiation on this link.
@@ -14215,6 +15219,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for EEE on this link.
@@ -14281,13 +15288,13 @@ struct hwrm_port_phy_qcaps_output {
#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
} __attribute__((packed));
-/*********************
- * hwrm_port_led_cfg *
- *********************/
+/****************************
+ * hwrm_port_phy_mdio_write *
+ ****************************/
-/* hwrm_port_led_cfg_input (size:512b/64B) */
-struct hwrm_port_led_cfg_input {
+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
+struct hwrm_port_phy_mdio_write_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -14315,46 +15322,198 @@ struct hwrm_port_led_cfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ /*
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
+ */
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1[7];
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_write_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This bit must be '1' for the led0_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
- UINT32_C(0x1)
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_port_phy_mdio_read *
+ ***************************/
+
+
+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
+struct hwrm_port_phy_mdio_read_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This bit must be '1' for the led0_state field to be
- * configured.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
- UINT32_C(0x2)
+ uint16_t cmpl_ring;
/*
- * This bit must be '1' for the led0_color field to be
- * configured.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
- UINT32_C(0x4)
+ uint16_t seq_id;
/*
- * This bit must be '1' for the led0_blink_on field to be
- * configured.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
- UINT32_C(0x8)
+ uint16_t target_id;
/*
- * This bit must be '1' for the led0_blink_off field to be
- * configured.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
- UINT32_C(0x10)
+ uint64_t resp_addr;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
/*
- * This bit must be '1' for the led0_group_id field to be
- * configured.
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
- UINT32_C(0x20)
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1;
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_read_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ uint8_t unused_0[5];
/*
- * This bit must be '1' for the led1_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_led_cfg *
+ *********************/
+
+
+/* hwrm_port_led_cfg_input (size:512b/64B) */
+struct hwrm_port_led_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the led0_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the led0_state field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the led0_color field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the led0_blink_on field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the led0_blink_off field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the led0_group_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the led1_id field to be
+ * configured.
*/
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
UINT32_C(0x40)
@@ -20644,7 +21803,9 @@ struct hwrm_ring_reset_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t unused_0[4];
+ /* Position of consumer index after ring reset completes. */
+ uint8_t consumer_idx[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -21209,6 +22370,26 @@ struct hwrm_ring_grp_free_output {
*/
uint8_t valid;
} __attribute__((packed));
+/*
+ * special reserved flow ID to identify per function default
+ * flows for vSwitch offload
+ */
+#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
+/*
+ * special reserved flow ID to identify per function RoCEv1
+ * flows
+ */
+#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * flows
+ */
+#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * CNP flows
+ */
+#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
/****************************
* hwrm_cfa_l2_filter_alloc *
@@ -22968,6 +24149,13 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Setting of this flag indicates the applicability to the loopback path. */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
+ /*
+ * Setting of this flag indicates this encap record is external encap record.
+ * Resetting of this flag indicates this flag is internal encap record and
+ * this is the default setting.
+ */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
+ UINT32_C(0x2)
/* Encapsulation Type. */
uint8_t encap_type;
/* Virtual eXtensible Local Area Network (VXLAN) */
@@ -23003,8 +24191,11 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -23144,6 +24335,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
UINT32_C(0x4)
+ /*
+ * Setting of this flag indicates that the dest_id field contains function ID.
+ * If this is not set it indicates dest_id is VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x8)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
@@ -23605,7 +24802,13 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
UINT32_C(0x4)
- uint8_t unused_0[4];
+ uint32_t flags;
+ /*
+ * Setting this bit to 1 indicates that dest_id field contains FID.
+ * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x1)
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
@@ -24090,6 +25293,118 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/************************
+ * hwrm_cfa_meter_qcaps *
+ ************************/
+
+
+/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_meter_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
+struct hwrm_cfa_meter_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the clock at which the Meter is running with.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
+ /* 375 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
+ /* 625 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
+ HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
+ uint8_t unused_0[4];
+ /*
+ * The minimum guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_tx_profile;
+ /*
+ * The maximum non-guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_tx_profile;
+ /*
+ * The minimum guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_rx_profile;
+ /*
+ * The maximum non-guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_rx_profile;
+ /*
+ * The minimum guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t min_tx_instance;
+ /*
+ * The maximum non-guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t max_tx_instance;
+ /*
+ * The minimum guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t min_rx_instance;
+ /*
+ * The maximum non-guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t max_rx_instance;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/********************************
* hwrm_cfa_meter_profile_alloc *
********************************/
@@ -24200,11 +25515,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24243,7 +25558,7 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24286,11 +25601,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24564,11 +25879,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24607,7 +25922,7 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24650,11 +25965,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24775,7 +26090,7 @@ struct hwrm_cfa_meter_instance_alloc_input {
/* This value identifies a meter profile in CFA. */
uint16_t meter_profile_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* profile is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
@@ -24798,7 +26113,7 @@ struct hwrm_cfa_meter_instance_alloc_output {
/* This value identifies a meter instance in CFA. */
uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* instance is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
@@ -24816,13 +26131,13 @@ struct hwrm_cfa_meter_instance_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_meter_instance_free *
- ********************************/
+/*******************************
+ * hwrm_cfa_meter_instance_cfg *
+ *******************************/
-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
-struct hwrm_cfa_meter_instance_free_input {
+/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24856,31 +26171,39 @@ struct hwrm_cfa_meter_instance_free_input {
* This enumeration is used for resources that are similar for both
* TX and RX paths of the chip.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
uint8_t unused_0;
- /* This value identifies a meter instance in CFA. */
- uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
+ * This value identifies a new meter profile to be associated with
+ * the meter instance specified in this command.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xffff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[4];
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This value identifies the ID of a meter instance that needs to be updated with
+ * a new meter profile specified in this command.
+ */
+ uint16_t meter_instance_id;
+ uint8_t unused_1[2];
} __attribute__((packed));
-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
-struct hwrm_cfa_meter_instance_free_output {
+/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24900,13 +26223,13 @@ struct hwrm_cfa_meter_instance_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24934,22 +26257,106 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
/*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
UINT32_C(0x2)
/*
* This bit must be '1' for the src_macaddr field to be
@@ -25375,6 +26782,9 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
+ /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
+ UINT32_C(0x200)
/*
* Tx Flow: vf fid.
* Rx Flow: pf fid.
@@ -25430,6 +26840,13 @@ struct hwrm_cfa_flow_alloc_input {
/* If set to 1, flow aging is enabled for this flow. */
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
UINT32_C(0x800)
+ /*
+ * If set to 1 an attempt will be made to try to offload this flow to the
+ * most optimal flow table resource. If set to 0, the flow will be
+ * placed to the default flow table resource.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
+ UINT32_C(0x1000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -25569,7 +26986,8 @@ struct hwrm_cfa_flow_alloc_output {
uint32_t flow_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint32_t flow_counter_id;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25646,6 +27064,229 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_action_data (size:960b/120B) */
+struct hwrm_cfa_flow_action_data {
+ uint16_t action_flags;
+ /* Setting of this flag indicates accept action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* Setting of this flag indicates recycle action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /* Setting of this flag indicates drop action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* Setting of this flag indicates meter action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* Setting of this flag indicates tunnel action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /*
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header.
+ */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
+ UINT32_C(0x20)
+ /* Setting of this flag indicates ttl decrement action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
+ UINT32_C(0x40)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x80)
+ /* Setting of this flag indicates encap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
+ UINT32_C(0x100)
+ /* Setting of this flag indicates decap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
+ UINT32_C(0x200)
+ /* Meter id. */
+ uint16_t act_meter_id;
+ /* VNIC id. */
+ uint16_t vnic_id;
+ /* vport number. */
+ uint16_t vport_id;
+ /* The NAT source/destination. */
+ uint16_t nat_port;
+ uint16_t unused_0[3];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ /* Encapsulation Type. */
+ uint8_t encap_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
+ /* VLAN */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
+ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
+ uint8_t unused[7];
+ /* This value is encap data for the associated encap type. */
+ uint32_t encap_data[20];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
+struct hwrm_cfa_flow_tunnel_hdr_data {
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused[3];
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI).
+ */
+ uint32_t tunnel_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
+struct hwrm_cfa_flow_l4_key_data {
+ /* The value of source port. */
+ uint16_t l4_src_port;
+ /* The value of destination port. */
+ uint16_t l4_dst_port;
+ uint32_t unused;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
+struct hwrm_cfa_flow_l3_key_data {
+ /* The value of ip protocol. */
+ uint8_t ip_protocol;
+ uint8_t unused_0[7];
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ uint32_t unused[2];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
+struct hwrm_cfa_flow_l2_key_data {
+ /* Destination MAC address. */
+ uint16_t dmac[3];
+ uint16_t unused_0;
+ /* Source MAC address. */
+ uint16_t smac[3];
+ uint16_t unused_1;
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
+ uint16_t unused_2;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* Ethertype. */
+ uint16_t ethertype;
+ /* Number of VLAN tags. */
+ uint16_t num_vlan_tags;
+ /* VLAN tpid. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci. */
+ uint16_t l2_rewrite_vlan_tci;
+ uint8_t unused_3[2];
+ /* Outer VLAN TPID. */
+ uint16_t ovlan_tpid;
+ /* Outer VLAN TCI. */
+ uint16_t ovlan_tci;
+ /* Inner VLAN TPID. */
+ uint16_t ivlan_tpid;
+ /* Inner VLAN TCI. */
+ uint16_t ivlan_tci;
+ uint8_t unused[8];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_key_data (size:4160b/520B) */
+struct hwrm_cfa_flow_key_data {
+ /* Flow associated tunnel L2 header key info. */
+ uint32_t t_l2_key_data[14];
+ /* Flow associated tunnel L2 header mask info. */
+ uint32_t t_l2_key_mask[14];
+ /* Flow associated tunnel L3 header key info. */
+ uint32_t t_l3_key_data[16];
+ /* Flow associated tunnel L3 header mask info. */
+ uint32_t t_l3_key_mask[16];
+ /* Flow associated tunnel L4 header key info. */
+ uint32_t t_l4_key_data[2];
+ /* Flow associated tunnel L4 header mask info. */
+ uint32_t t_l4_key_mask[2];
+ /* Flow associated tunnel header info. */
+ uint32_t tunnel_hdr[2];
+ /* Flow associated L2 header key info. */
+ uint32_t l2_key_data[14];
+ /* Flow associated L2 header mask info. */
+ uint32_t l2_key_mask[14];
+ /* Flow associated L3 header key info. */
+ uint32_t l3_key_data[16];
+ /* Flow associated L3 header mask info. */
+ uint32_t l3_key_mask[16];
+ /* Flow associated L4 header key info. */
+ uint32_t l4_key_data[2];
+ /* Flow associated L4 header mask info. */
+ uint32_t l4_key_mask[2];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_info *
**********************/
@@ -25703,7 +27344,7 @@ struct hwrm_cfa_flow_info_input {
uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_info_output (size:448b/56B) */
+/* hwrm_cfa_flow_info_output (size:5632b/704B) */
struct hwrm_cfa_flow_info_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -25713,8 +27354,11 @@ struct hwrm_cfa_flow_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* flags is 8 b */
uint8_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
/* profile is 8 b */
uint8_t profile;
/* src_fid is 16 b */
@@ -25737,7 +27381,12 @@ struct hwrm_cfa_flow_info_output {
uint32_t tunnel_handle;
/* The flow aging timer for the flow, the unit is 100 milliseconds */
uint16_t flow_timer;
- uint8_t unused_0[5];
+ uint8_t unused_0[6];
+ /* Flow associated L2, L3 and L4 headers info. */
+ uint32_t flow_key_data[130];
+ /* Flow associated action record info. */
+ uint32_t flow_action_info[30];
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25753,7 +27402,7 @@ struct hwrm_cfa_flow_info_output {
***********************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+/* hwrm_cfa_flow_flush_input (size:256b/32B) */
struct hwrm_cfa_flow_flush_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -25782,8 +27431,73 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* flags is 32 b */
uint32_t flags;
- uint8_t unused_0[4];
+ /*
+ * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
+ * fields are valid. The flow flush operation should only flush the flows from the
+ * flow table specified. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
+ UINT32_C(0x1)
+ /*
+ * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
+ * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
+ UINT32_C(0x2)
+ /*
+ * This specifies the size of flow handle entries provided by the driver
+ * in the flow table specified below. Only two flow handle size enums are defined.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
+ UINT32_C(0xc0000000)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
+ 30
+ /* The flow handle is 16bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
+ (UINT32_C(0x0) << 30)
+ /* The flow handle is 64bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
+ /* Specify page size of the flow table memory. */
+ uint8_t page_size;
+ /* The page size is 4K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* The page size is 8K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* The page size is 64K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* The page size is 256K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* The page size is 1M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* The page size is 2M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* The page size is 4M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* The page size is 1G */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
+ /* FLow table memory indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
+ /* number of flows in the flow table */
+ uint16_t num_flows;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
} __attribute__((packed));
/* hwrm_cfa_flow_flush_output (size:128b/16B) */
@@ -25983,7 +27697,12 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint8_t unused_0[2];
+ /*
+ * New flow timer value for the flow specified in the ext_flow_handle.
+ * The flow timer unit is 100ms.
+ */
+ uint32_t flow_timer;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -26244,13 +27963,13 @@ struct hwrm_cfa_flow_aging_qcaps_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_pair_info *
- **********************/
+/**********************************
+ * hwrm_cfa_tcp_flag_process_qcfg *
+ **********************************/
-/* hwrm_cfa_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_pair_info_input {
+/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26278,23 +27997,10 @@ struct hwrm_cfa_pair_info_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* If this flag is set, lookup by name else lookup by index. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
- /* If this flag is set, lookup by PF id and VF id. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
- /* Pair table index. */
- uint16_t pair_index;
- /* Pair pf index. */
- uint8_t pair_pfid;
- /* Pair vf index. */
- uint8_t pair_vfid;
- /* Pair name (32 byte string). */
- char pair_name[32];
} __attribute__((packed));
-/* hwrm_cfa_pair_info_output (size:576b/72B) */
-struct hwrm_cfa_pair_info_output {
+/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26303,22 +28009,100 @@ struct hwrm_cfa_pair_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Pair table index. */
- uint16_t next_pair_index;
- /* Pair member a's fid. */
- uint16_t a_fid;
- /* Logical host number. */
- uint8_t host_a_index;
- /* Logical PF number. */
- uint8_t pf_a_index;
- /* Pair member a's Linux logical VF number. */
- uint16_t vf_a_index;
- /* Rx CFA code. */
- uint16_t rx_cfa_code_a;
- /* Tx CFA action. */
- uint16_t tx_cfa_action_a;
- /* Pair member b's fid. */
- uint16_t b_fid;
+ /* The port 0 RX mirror action record ID. */
+ uint16_t rx_ar_id_port0;
+ /* The port 1 RX mirror action record ID. */
+ uint16_t rx_ar_id_port1;
+ /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port0;
+ /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port1;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_pair_info *
+ **********************/
+
+
+/* hwrm_cfa_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_pair_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If this flag is set, lookup by name else lookup by index. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
+ /* If this flag is set, lookup by PF id and VF id. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
+ /* Pair table index. */
+ uint16_t pair_index;
+ /* Pair pf index. */
+ uint8_t pair_pfid;
+ /* Pair vf index. */
+ uint8_t pair_vfid;
+ /* Pair name (32 byte string). */
+ char pair_name[32];
+} __attribute__((packed));
+
+/* hwrm_cfa_pair_info_output (size:576b/72B) */
+struct hwrm_cfa_pair_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pair table index. */
+ uint16_t next_pair_index;
+ /* Pair member a's fid. */
+ uint16_t a_fid;
+ /* Logical host number. */
+ uint8_t host_a_index;
+ /* Logical PF number. */
+ uint8_t pf_a_index;
+ /* Pair member a's Linux logical VF number. */
+ uint16_t vf_a_index;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code_a;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action_a;
+ /* Pair member b's fid. */
+ uint16_t b_fid;
/* Logical host number. */
uint8_t host_b_index;
/* Logical PF number. */
@@ -26364,13 +28148,645 @@ struct hwrm_cfa_pair_info_output {
uint8_t valid;
} __attribute__((packed));
-/***************************************
- * hwrm_cfa_redirect_query_tunnel_type *
- ***************************************/
+/***************************************
+ * hwrm_cfa_redirect_query_tunnel_type *
+ ***************************************/
+
+
+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
+struct hwrm_cfa_redirect_query_tunnel_type_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The source function id. */
+ uint16_t src_fid;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
+struct hwrm_cfa_redirect_query_tunnel_type_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Tunnel Mask. */
+ uint32_t tunnel_mask;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ UINT32_C(0x1)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ UINT32_C(0x2)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ UINT32_C(0x4)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ UINT32_C(0x8)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ UINT32_C(0x10)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ UINT32_C(0x20)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ UINT32_C(0x40)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
+ UINT32_C(0x80)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
+ UINT32_C(0x100)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
+ UINT32_C(0x200)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
+ UINT32_C(0x400)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
+ UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_rgtr *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_rgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
+ uint32_t unused_0;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_rgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_cfa_ctx_mem_unrgtr *
+ ***************************/
+
+
+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_unrgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_unrgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_qctx *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_qctx_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_qctx_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
+ uint8_t unused_0[4];
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**************************
+ * hwrm_cfa_ctx_mem_qcaps *
+ **************************/
+
+
+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Indicates the maximum number of context memory which can be registered. */
+ uint16_t max_entries;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_eem_qcaps *
+ **********************/
+
+
+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_eem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
+ uint32_t supported;
+ /*
+ * If set to 1, then EEM KEY0 table is supported using crc32 hash.
+ * If set to 0 EEM KEY0 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
+ * If set to 0 EEM KEY1 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, then EEM External Record table is supported.
+ * If set to 0 EEM External Record table is not supported.
+ * (This table includes action record, EFC pointers, encap pointers)
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, then EEM External Flow Counters table is supported.
+ * If set to 0 EEM External Flow Counters table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+ UINT32_C(0x8)
+ /*
+ * The maximum number of entries supported by EEM. When configuring the host memory
+ * the number of numbers of entries that can supported are -
+ * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
+ * Any value that are not these values, the FW will round down to the closest support
+ * number of entries.
+ */
+ uint32_t max_entries_supported;
+ /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
+ uint16_t key_entry_size;
+ /* The entry size in bytes of each entry in the RECORD EEM tables. */
+ uint16_t record_entry_size;
+ /* The entry size in bytes of each entry in the EFC EEM tables. */
+ uint16_t efc_entry_size;
+ uint8_t unused_1;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************
+ * hwrm_cfa_eem_cfg *
+ ********************/
+
+
+/* hwrm_cfa_eem_cfg_input (size:320b/40B) */
+struct hwrm_cfa_eem_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+ /*
+ * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
+ * RECORD, EFC all have the same number of entries and all tables will be configured
+ * using this value. Current minimum value is 32k. Current maximum value is 128M.
+ */
+ uint32_t num_entries;
+ uint32_t unused_1;
+ /* Configured EEM with the given context if for KEY0 table. */
+ uint16_t key0_ctx_id;
+ /* Configured EEM with the given context if for KEY1 table. */
+ uint16_t key1_ctx_id;
+ /* Configured EEM with the given context if for RECORD table. */
+ uint16_t record_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t efc_ctx_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
+struct hwrm_cfa_eem_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_cfa_eem_qcfg *
+ *********************/
-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
-struct hwrm_cfa_redirect_query_tunnel_type_input {
+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26398,13 +28814,16 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The source function id. */
- uint16_t src_fid;
- uint8_t unused_0[6];
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
} __attribute__((packed));
-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
-struct hwrm_cfa_redirect_query_tunnel_type_output {
+/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26413,50 +28832,219 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Tunnel Mask. */
- uint32_t tunnel_mask;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
UINT32_C(0x1)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
UINT32_C(0x2)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ /* The number of entries the FW has configured for EEM. */
+ uint32_t num_entries;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************
+ * hwrm_cfa_eem_op *
+ *******************/
+
+
+/* hwrm_cfa_eem_op_input (size:192b/24B) */
+struct hwrm_cfa_eem_op_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the TX flow offload function specified in fid.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the RX flow offload function specified in fid.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint16_t unused_0;
+ /* The number of EEM key table entries to be configured. */
+ uint16_t op;
+ /* This value is reserved and should not be used. */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
+ /*
+ * To properly stop EEM and ensure there are no DMA's, the caller
+ * must disable EEM for the given PF, using this call. This will
+ * safely disable EEM and ensure that all DMA'ed to the
+ * keys/records/efc have been completed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
+ /*
+ * Once the EEM host memory has been configured, EEM options have
+ * been configured. Then the caller should enable EEM for the given
+ * PF. Note once this call has been made, then the EEM mechanism
+ * will be active and DMA's will occur as packets are processed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
+ /*
+ * Clear EEM settings for the given PF so that the register values
+ * are reset back to there initial state.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
+ #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
+ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_op_output (size:128b/16B) */
+struct hwrm_cfa_eem_op_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_adv_flow_mgnt_qcaps *
+ ********************************/
+
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Value of 1 to indicate firmware support 16-bit flow handle.
+ * Value of 0 to indicate firmware not support 16-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate firmware support 64-bit flow handle.
+ * Value of 0 to indicate firmware not support 64-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * Value of 1 to indicate firmware support flow batch delete operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 to indicate that the firmware does not support flow batch delete
+ * operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * Value of 1 to indicate that the firmware support flow reset all operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 indicates firmware does not support flow reset all operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
UINT32_C(0x8)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ /*
+ * Value of 1 to indicate that firmware supports use of FID as dest_id in
+ * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
+ * Value of 0 indicates firmware does not support use of FID as dest_id.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
UINT32_C(0x10)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ /*
+ * Value of 1 to indicate that firmware supports TX EEM flows.
+ * Value of 0 indicates firmware does not support TX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
UINT32_C(0x20)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ /*
+ * Value of 1 to indicate that firmware supports RX EEM flows.
+ * Value of 0 indicates firmware does not support RX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
- UINT32_C(0x80)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
- UINT32_C(0x100)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
- UINT32_C(0x200)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
- UINT32_C(0x400)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
- UINT32_C(0x800)
- /* Use fixed layer 2 ether type of 0xFFFF */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
- UINT32_C(0x1000)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
- UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -26874,7 +29462,11 @@ struct hwrm_stat_ctx_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This is the address for statistic block. */
+ /*
+ * This is the address for statistic block.
+ * > For new versions of the chip, this address should be 128B
+ * > aligned.
+ */
uint64_t stats_dma_addr;
/*
* The statistic block update period in ms.
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v3 8/8] net/bnxt: update HWRM API to version 1.10.0.74
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
` (6 preceding siblings ...)
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
@ 2019-05-28 19:23 ` Lance Richardson
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-28 19:23 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.74
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
doc/guides/rel_notes/release_19_08.rst | 1 +
drivers/net/bnxt/hsi_struct_def_dpdk.h | 1399 ++++++++++++++++++++----
2 files changed, 1169 insertions(+), 231 deletions(-)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 7e5ca3c34..ea8fbcdfd 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -59,6 +59,7 @@ New Features
Updated the bnxt PMD. The major enhancements include:
* Performance optimizations in non-vector Tx path
* Added support for SSE vector mode
+ * Updated HWRM API to version 1.10.0.74
Removed Items
-------------
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 00a8ff87e..305ee09bc 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2019 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -27,7 +27,8 @@ struct hwrm_cmd_hdr {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -221,8 +222,14 @@ struct hwrm_short_input {
#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
#define HWRM_SHORT_INPUT_SIGNATURE_LAST \
HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
- /* Reserved for future use. */
- uint16_t unused_0;
+ /* The target ID of the command */
+ uint16_t target_id;
+ /* Default target_id (0x0) to maintain compatibility with old driver */
+ #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
+ /* Reserved for user-space HWRM interface */
+ #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
+ #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
+ HWRM_SHORT_INPUT_TARGET_ID_TOOLS
/* This value indicates the length of the request. */
uint16_t size;
/*
@@ -394,6 +401,8 @@ struct cmd_nums {
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
#define HWRM_OEM_CMD UINT32_C(0xd4)
+ /* Tells the fw to run PRBS test on a given port and lane. */
+ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
@@ -486,6 +495,8 @@ struct cmd_nums {
#define HWRM_CFA_EEM_OP UINT32_C(0x123)
/* Experimental */
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
+ /* Experimental */
+ #define HWRM_CFA_TFLIB UINT32_C(0x125)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -506,6 +517,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
/* Engine CKV - Configure a label index with a label value. */
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
+ /* Engine CKV - Query a label */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -587,6 +600,19 @@ struct cmd_nums {
/* Experimental */
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
/* Experimental */
+ #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
+ /* Returns the current value of a free running counter from the device. */
+ #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
+ /* Experimental */
+ #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
+ /* Experimental */
+ #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
+ /*
+ * Tells the fw to run the DMA read from the host and DMA write
+ * to the host test.
+ */
+ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
+ /* Experimental */
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
/* Experimental */
#define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
@@ -643,67 +669,85 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
/*
* This error code is only reported by firmware when the specific
* request is not able to process when the HOT reset in progress.
*/
- #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
/*
* This error code is only reported by firmware when the registered
* driver instances are not capable of hot reset.
*/
- #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ /*
+ * This error code is only reported by the firmware when during
+ * flow allocation when a requeest for a flow counter fails because
+ * the number of flow counters are exhausted.
+ */
+ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the requested key's hash collides with the installed keys.
+ */
+ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the same key has already been installed.
+ */
+ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
@@ -711,11 +755,11 @@ struct ret_codes {
* by itself, just an indicatation that the response should be parsed
* as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
*/
- #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -774,12 +818,25 @@ struct hwrm_err_output {
#define HW_HASH_KEY_SIZE 40
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
+/* Reserved for BONO processor */
+#define HWRM_TARGET_ID_BONO 0xFFF8
+/* Reserved for KONG processor */
+#define HWRM_TARGET_ID_KONG 0xFFF9
+/* Reserved for APE processor */
+#define HWRM_TARGET_ID_APE 0xFFFA
+/*
+ * This value will be used by tools for User-space HWRM Interface.
+ * When tool execute any HWRM command with this target_id, firmware
+ * will copy the response and/or data payload via register space instead
+ * of DMAing it.
+ */
+#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 48
-#define HWRM_VERSION_STR "1.10.0.48"
+#define HWRM_VERSION_RSVD 74
+#define HWRM_VERSION_STR "1.10.0.74"
/****************
* hwrm_ver_get *
@@ -804,7 +861,8 @@ struct hwrm_ver_get_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -1062,6 +1120,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
UINT32_C(0x1000)
+ /*
+ * If set to 1, the firmware is able to support TFLIB features.
+ * If set to 0, then the firmware doesn’t support TFLIB features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
+ UINT32_C(0x2000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -1099,12 +1164,8 @@ struct hwrm_ver_get_output {
* firmware (ASCII chars with NULL at the end).
*/
char netctrl_fw_name[16];
- /*
- * This field is reserved for future use.
- * The responder should set it to 0.
- * The requester should ignore this field.
- */
- uint8_t reserved2[16];
+ /* This field represents the active board package name. */
+ char active_pkg_name[16];
/*
* This field represents the name of RoCE FW (ASCII chars
* with NULL at the end).
@@ -3845,6 +3906,12 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
UINT32_C(0x3c)
+ /* TFLIB unique default VNIC Configuration Change */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
+ UINT32_C(0x3d)
+ /* TFLIB unique link status changed */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
+ UINT32_C(0x3e)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -5859,7 +5926,8 @@ struct hwrm_func_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -5962,7 +6030,8 @@ struct hwrm_func_getfid_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6038,7 +6107,8 @@ struct hwrm_func_vf_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6110,7 +6180,8 @@ struct hwrm_func_vf_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6183,7 +6254,8 @@ struct hwrm_func_vf_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6446,7 +6518,8 @@ struct hwrm_func_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6663,6 +6736,13 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
UINT32_C(0x800000)
+ /*
+ * If the query is for a VF, then this flag shall be ignored.
+ * If this query is for a PF and this flag is set to 1, then
+ * the PF has the capability to support extended stats.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
+ UINT32_C(0x1000000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6807,7 +6887,8 @@ struct hwrm_func_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7247,7 +7328,8 @@ struct hwrm_func_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7889,7 +7971,8 @@ struct hwrm_func_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8014,7 +8097,8 @@ struct hwrm_func_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8078,7 +8162,8 @@ struct hwrm_func_vf_resc_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8141,7 +8226,8 @@ struct hwrm_func_drv_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8382,7 +8468,8 @@ struct hwrm_func_drv_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8447,7 +8534,8 @@ struct hwrm_func_buf_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8581,7 +8669,8 @@ struct hwrm_func_buf_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8650,7 +8739,8 @@ struct hwrm_func_drv_qver_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8757,7 +8847,8 @@ struct hwrm_func_resource_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8886,7 +8977,8 @@ struct hwrm_func_backing_store_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8973,7 +9065,10 @@ struct hwrm_func_backing_store_qcaps_output {
* the backing store.
*/
uint32_t tqm_max_entries_per_ring;
- /* Maximum number of MR/AV context entries supported for this function. */
+ /*
+ * Maximum number of MR plus AV context entries supported for this
+ * function.
+ */
uint32_t mrav_max_entries;
/* Number of bytes that must be allocated for each context entry. */
uint16_t mrav_entry_size;
@@ -8981,7 +9076,22 @@ struct hwrm_func_backing_store_qcaps_output {
uint16_t tim_entry_size;
/* Maximum number of Timer context entries supported for this function. */
uint32_t tim_max_entries;
- uint8_t unused_0[2];
+ /*
+ * When this field is zero, the 32b `mrav_num_entries` field in the
+ * `backing_store_cfg` and `backing_store_qcfg` commands represents
+ * the total number of MR plus AV entries allowed in the MR/AV backing
+ * store PBL.
+ *
+ * When this field is non-zero, the 32b `mrav_num_entries` field in
+ * the `backing_store_cfg` and `backing_store_qcfg` commands is
+ * logically divided into two 16b fields. Bits `[31:16]` represents
+ * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
+ * Both of these values are represented in a unit granularity
+ * specified by this field. For example, if this field is 16 and
+ * `mrav_num_entries` is `0x02000100`, then the number of MR entries
+ * is 8192 and the number of AV entries is 4096.
+ */
+ uint16_t mrav_num_entries_units;
/*
* The number of entries specified for any TQM ring must be a
* multiple of this value to prevent any resource allocation
@@ -9021,7 +9131,8 @@ struct hwrm_func_backing_store_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -9041,6 +9152,12 @@ struct hwrm_func_backing_store_cfg_input {
*/
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint32_t enables;
/*
* This bit must be '1' for the qp fields to be
@@ -9958,7 +10075,20 @@ struct hwrm_func_backing_store_cfg_input {
* the backing store.
*/
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10036,7 +10166,8 @@ struct hwrm_func_backing_store_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -10068,6 +10199,12 @@ struct hwrm_func_backing_store_qcfg_output {
*/
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint8_t unused_0[4];
/*
* This bit must be '1' for the qp fields to be
@@ -10891,7 +11028,20 @@ struct hwrm_func_backing_store_qcfg_output {
uint32_t tqm_ring6_num_entries;
/* Number of TQM ring 7 entries. */
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10930,7 +11080,8 @@ struct hwrm_error_recovery_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11296,7 +11447,8 @@ struct hwrm_func_vlan_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11386,7 +11538,8 @@ struct hwrm_func_vlan_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11507,7 +11660,8 @@ struct hwrm_func_vf_vnic_ids_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11580,7 +11734,8 @@ struct hwrm_func_vf_bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11704,7 +11859,8 @@ struct hwrm_func_vf_bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11841,7 +11997,8 @@ struct hwrm_func_drv_if_change_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11929,7 +12086,8 @@ struct hwrm_port_phy_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -12520,7 +12678,8 @@ struct hwrm_port_phy_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13389,7 +13548,7 @@ struct hwrm_port_phy_qcfg_output {
*********************/
-/* hwrm_port_mac_cfg_input (size:320b/40B) */
+/* hwrm_port_mac_cfg_input (size:384b/48B) */
struct hwrm_port_mac_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13407,7 +13566,8 @@ struct hwrm_port_mac_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13527,6 +13687,13 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
UINT32_C(0x1000)
+ /*
+ * When this bit is set to '1', and the ptp_tx_ts_capture_enable
+ * bit is set, then the device uses one step Tx timestamping.
+ * This bit is temporary and used for experimental purposes.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
+ UINT32_C(0x2000)
uint32_t enables;
/*
* This bit must be '1' for the ipg field to be
@@ -13576,6 +13743,12 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ppb field to be
+ * configured.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
+ UINT32_C(0x200)
/* Port ID of port that is to be configured. */
uint16_t port_id;
/*
@@ -13763,6 +13936,12 @@ struct hwrm_port_mac_cfg_input {
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
5
uint8_t unused_0[3];
+ /*
+ * This signed field specifies by how much to adjust the frequency
+ * of sync timer updates (measured in parts per billion).
+ */
+ int32_t ptp_freq_adj_ppb;
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_port_mac_cfg_output (size:128b/16B) */
@@ -13842,7 +14021,8 @@ struct hwrm_port_mac_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14131,7 +14311,8 @@ struct hwrm_port_mac_ptp_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14174,6 +14355,12 @@ struct hwrm_port_mac_ptp_qcfg_output {
*/
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', the device supports one-step
+ * Tx timestamping.
+ */
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
+ UINT32_C(0x4)
uint8_t unused_0[3];
/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
uint32_t rx_ts_reg_off_lower;
@@ -14595,7 +14782,8 @@ struct hwrm_port_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14716,7 +14904,7 @@ struct tx_port_stats_ext {
} __attribute__((packed));
/* Port Rx Statistics extended Formats */
-/* rx_port_stats_ext (size:2368b/296B) */
+/* rx_port_stats_ext (size:3648b/456B) */
struct rx_port_stats_ext {
/* Number of times link state changed to down */
uint64_t link_down_events;
@@ -14792,6 +14980,49 @@ struct rx_port_stats_ext {
uint64_t pfc_pri7_rx_duration_us;
/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
uint64_t pfc_pri7_rx_transitions;
+ /* Total number of received bits */
+ uint64_t rx_bits;
+ /* The number of events where the port receive buffer was over 85% full */
+ uint64_t rx_buffer_passed_threshold;
+ /*
+ * The number of symbol errors that wasn't corrected by FEC correction
+ * alogirithm
+ */
+ uint64_t rx_pcs_symbol_err;
+ /* The number of corrected bits on the port according to active FEC */
+ uint64_t rx_corrected_bits;
+ /* Total number of rx discard bytes count on cos queue 0 */
+ uint64_t rx_discard_bytes_cos0;
+ /* Total number of rx discard bytes count on cos queue 1 */
+ uint64_t rx_discard_bytes_cos1;
+ /* Total number of rx discard bytes count on cos queue 2 */
+ uint64_t rx_discard_bytes_cos2;
+ /* Total number of rx discard bytes count on cos queue 3 */
+ uint64_t rx_discard_bytes_cos3;
+ /* Total number of rx discard bytes count on cos queue 4 */
+ uint64_t rx_discard_bytes_cos4;
+ /* Total number of rx discard bytes count on cos queue 5 */
+ uint64_t rx_discard_bytes_cos5;
+ /* Total number of rx discard bytes count on cos queue 6 */
+ uint64_t rx_discard_bytes_cos6;
+ /* Total number of rx discard bytes count on cos queue 7 */
+ uint64_t rx_discard_bytes_cos7;
+ /* Total number of rx discard packets count on cos queue 0 */
+ uint64_t rx_discard_packets_cos0;
+ /* Total number of rx discard packets count on cos queue 1 */
+ uint64_t rx_discard_packets_cos1;
+ /* Total number of rx discard packets count on cos queue 2 */
+ uint64_t rx_discard_packets_cos2;
+ /* Total number of rx discard packets count on cos queue 3 */
+ uint64_t rx_discard_packets_cos3;
+ /* Total number of rx discard packets count on cos queue 4 */
+ uint64_t rx_discard_packets_cos4;
+ /* Total number of rx discard packets count on cos queue 5 */
+ uint64_t rx_discard_packets_cos5;
+ /* Total number of rx discard packets count on cos queue 6 */
+ uint64_t rx_discard_packets_cos6;
+ /* Total number of rx discard packets count on cos queue 7 */
+ uint64_t rx_discard_packets_cos7;
} __attribute__((packed));
/************************
@@ -14817,7 +15048,8 @@ struct hwrm_port_qstats_ext_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14909,7 +15141,8 @@ struct hwrm_port_lpbk_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14986,7 +15219,8 @@ struct hwrm_port_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15057,7 +15291,8 @@ struct hwrm_port_phy_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15311,7 +15546,8 @@ struct hwrm_port_phy_mdio_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15387,7 +15623,8 @@ struct hwrm_port_phy_mdio_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15463,7 +15700,8 @@ struct hwrm_port_led_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15886,7 +16124,8 @@ struct hwrm_port_led_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16191,7 +16430,8 @@ struct hwrm_port_led_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16519,6 +16759,137 @@ struct hwrm_port_led_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/***********************
+ * hwrm_port_prbs_test *
+ ***********************/
+
+
+/* hwrm_port_prbs_test_input (size:384b/48B) */
+struct hwrm_port_prbs_test_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Host address data is to DMA'd to. */
+ uint64_t resp_data_addr;
+ /*
+ * Size of the buffer pointed to by resp_data_addr. The firmware may
+ * use this entire buffer or less than the entire buffer, but never more.
+ */
+ uint16_t data_len;
+ uint16_t unused_0;
+ uint32_t unused_1;
+ /* Port ID of port where PRBS test to be run. */
+ uint16_t port_id;
+ /* Polynomial selection for PRBS test. */
+ uint16_t poly;
+ /* PRBS7 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
+ /* PRBS9 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
+ /* PRBS11 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
+ /* PRBS15 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
+ /* PRBS23 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
+ /* PRBS31 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
+ /* PRBS58 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* Invalid */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
+ HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
+ /*
+ * Configuration bits for PRBS test.
+ * Use enable bit to start/stop test.
+ * Use tx/rx lane map bits to run test on specific lanes,
+ * if set to 0 test will be run on all lanes.
+ */
+ uint16_t prbs_config;
+ /*
+ * Set 0 to stop test currently in progress
+ * Set 1 to start test with configuration provided.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, tx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, rx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
+ UINT32_C(0x4)
+ /* Duration in seconds to run the PRBS test. */
+ uint16_t timeout;
+ /*
+ * If tx_lane_map_valid is set to 1, this field is a bitmap
+ * of tx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t tx_lane_map;
+ /*
+ * If rx_lane_map_valid is set to 1, this field is a bitmap
+ * of rx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t rx_lane_map;
+} __attribute__((packed));
+
+/* hwrm_port_prbs_test_output (size:128b/16B) */
+struct hwrm_port_prbs_test_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -16542,7 +16913,8 @@ struct hwrm_queue_qportcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16994,7 +17366,8 @@ struct hwrm_queue_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17091,7 +17464,8 @@ struct hwrm_queue_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17194,7 +17568,8 @@ struct hwrm_queue_pfcenable_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17283,7 +17658,8 @@ struct hwrm_queue_pfcenable_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17372,7 +17748,8 @@ struct hwrm_queue_pri2cos_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17522,7 +17899,8 @@ struct hwrm_queue_pri2cos_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17698,7 +18076,8 @@ struct hwrm_queue_cos2bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -18740,7 +19119,8 @@ struct hwrm_queue_cos2bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19831,7 +20211,8 @@ struct hwrm_vnic_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19897,7 +20278,8 @@ struct hwrm_vnic_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19957,7 +20339,8 @@ struct hwrm_vnic_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20172,7 +20555,8 @@ struct hwrm_vnic_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20327,7 +20711,8 @@ struct hwrm_vnic_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20419,7 +20804,13 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
UINT32_C(0x80)
- uint8_t unused_1[7];
+ /*
+ * This field advertises the maximum concurrent TPA aggregations
+ * supported by the VNIC on new devices that support TPA v2.
+ * '0' means that TPA v2 is not supported.
+ */
+ uint16_t max_aggs_supported;
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -20453,7 +20844,8 @@ struct hwrm_vnic_tpa_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20529,6 +20921,15 @@ struct hwrm_vnic_tpa_cfg_input {
*/
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
UINT32_C(0x80)
+ /*
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall DMA payload data using GRO rules.
+ * When this bit is '0', the VNIC shall DMA payload data
+ * using the more efficient LRO rules of filling all
+ * aggregation buffers.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
+ UINT32_C(0x100)
uint32_t enables;
/*
* This bit must be '1' for the max_agg_segs field to be
@@ -20545,16 +20946,15 @@ struct hwrm_vnic_tpa_cfg_input {
* configured.
*/
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
- /*
- * This bit must be '1' for the min_agg_len field to be
- * configured.
- */
+ /* deprecated bit. Do not use!!! */
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
/* Logical vnic ID */
uint16_t vnic_id;
/*
* This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31.
+ * be aggregated (unit is Log2). Max value is 31. On new
+ * devices supporting TPA v2, the unit is multiples of 4 and
+ * valid values are > 0 and <= 63.
*/
uint16_t max_agg_segs;
/* 1 segment */
@@ -20571,7 +20971,10 @@ struct hwrm_vnic_tpa_cfg_input {
HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
/*
* This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7
+ * allowed (unit is Log2). Max value is 7. On new devices
+ * supporting TPA v2, this is in unit of 1 and must be > 0
+ * and <= max_aggs_supported in the hwrm_vnic_qcaps response
+ * to enable TPA v2.
*/
uint16_t max_aggs;
/* 1 aggregation */
@@ -20596,7 +20999,9 @@ struct hwrm_vnic_tpa_cfg_input {
uint32_t max_agg_timer;
/*
* This is the minimum amount of payload length required to
- * start an aggregation context.
+ * start an aggregation context. This field is deprecated and
+ * should be set to 0. The minimum length is set by firmware
+ * and can be queried using hwrm_vnic_tpa_qcfg.
*/
uint32_t min_agg_len;
} __attribute__((packed));
@@ -20645,7 +21050,8 @@ struct hwrm_vnic_rss_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20795,7 +21201,8 @@ struct hwrm_vnic_rss_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20937,7 +21344,8 @@ struct hwrm_vnic_plcmodes_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21100,7 +21508,8 @@ struct hwrm_vnic_plcmodes_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21228,7 +21637,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21287,7 +21697,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21347,7 +21758,8 @@ struct hwrm_ring_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21687,7 +22099,8 @@ struct hwrm_ring_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21764,7 +22177,8 @@ struct hwrm_ring_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21839,7 +22253,8 @@ struct hwrm_ring_aggint_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21988,7 +22403,8 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22094,7 +22510,8 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22250,7 +22667,8 @@ struct hwrm_ring_grp_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22334,7 +22752,8 @@ struct hwrm_ring_grp_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22414,7 +22833,8 @@ struct hwrm_cfa_l2_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22476,6 +22896,22 @@ struct hwrm_cfa_l2_filter_alloc_input {
(UINT32_C(0x2) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
+ /*
+ * Setting of this flag indicates that no XDP filter is created with
+ * L2 filter.
+ * 0 - legacy behavior, XDP filter is created with L2 filter
+ * 1 - XDP filter won't be created with L2 filter
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
+ UINT32_C(0x40)
+ /*
+ * Setting this flag to 1 indicate the L2 fields in this command
+ * pertain to source fields. Setting this flag to 0 indicate the
+ * L2 fields in this command pertain to the destination fields
+ * and this is the default/legacy behavior.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
+ UINT32_C(0x80)
uint32_t enables;
/*
* This bit must be '1' for the l2_addr field to be
@@ -22579,13 +23015,31 @@ struct hwrm_cfa_l2_filter_alloc_input {
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
+ UINT32_C(0x20000)
+ /*
+ * This bit must be '1' for the t_num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
+ UINT32_C(0x40000)
/*
* This value sets the match value for the L2 MAC address.
* Destination MAC address for RX path.
* Source MAC address for TX path.
*/
uint8_t l2_addr[6];
- uint8_t unused_0[2];
+ /* This value sets the match value for the number of VLANs. */
+ uint8_t num_vlans;
+ /*
+ * This value sets the match value for the number of VLANs
+ * in the tunnel headers.
+ */
+ uint8_t t_num_vlans;
/*
* This value sets the mask value for the L2 address.
* A value of 0 will mask the corresponding bit from
@@ -22784,13 +23238,45 @@ struct hwrm_cfa_l2_filter_alloc_output {
*/
uint64_t l2_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -22825,7 +23311,8 @@ struct hwrm_cfa_l2_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22887,7 +23374,8 @@ struct hwrm_cfa_l2_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23014,7 +23502,8 @@ struct hwrm_cfa_l2_set_rx_mask_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23213,7 +23702,8 @@ struct hwrm_cfa_vlan_antispoof_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23287,7 +23777,8 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23366,7 +23857,8 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23602,13 +24094,45 @@ struct hwrm_cfa_tunnel_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t tunnel_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -23643,7 +24167,8 @@ struct hwrm_cfa_tunnel_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23702,7 +24227,8 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23813,7 +24339,8 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23919,7 +24446,8 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24134,7 +24662,8 @@ struct hwrm_cfa_encap_record_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24247,7 +24776,8 @@ struct hwrm_cfa_encap_record_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24289,7 +24819,7 @@ struct hwrm_cfa_encap_record_free_output {
********************************/
-/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
+/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
struct hwrm_cfa_ntuple_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -24307,7 +24837,8 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24456,6 +24987,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
UINT32_C(0x40000)
+ /*
+ * This bit must be '1' for the rfs_ring_tbl_idx field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
+ UINT32_C(0x80000)
/*
* This value identifies a set of CFA data structures used for an L2
* context.
@@ -24639,6 +25176,13 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
* the pri_hint.
*/
uint64_t ntuple_filter_id_hint;
+ /*
+ * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
+ * This index is used in lieu of the RSS hash when selecting the
+ * index into the RSS table to determine the rx ring.
+ */
+ uint16_t rfs_ring_tbl_idx;
+ uint8_t unused_0[6];
} __attribute__((packed));
/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
@@ -24654,13 +25198,45 @@ struct hwrm_cfa_ntuple_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24713,7 +25289,8 @@ struct hwrm_cfa_ntuple_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24772,7 +25349,8 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24884,7 +25462,8 @@ struct hwrm_cfa_em_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25216,13 +25795,45 @@ struct hwrm_cfa_em_flow_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t em_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -25257,7 +25868,8 @@ struct hwrm_cfa_em_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25316,7 +25928,8 @@ struct hwrm_cfa_meter_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25428,7 +26041,8 @@ struct hwrm_cfa_meter_profile_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25705,7 +26319,8 @@ struct hwrm_cfa_meter_profile_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25789,7 +26404,8 @@ struct hwrm_cfa_meter_profile_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26059,7 +26675,8 @@ struct hwrm_cfa_meter_instance_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26154,7 +26771,8 @@ struct hwrm_cfa_meter_instance_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26246,7 +26864,8 @@ struct hwrm_cfa_meter_instance_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26330,7 +26949,8 @@ struct hwrm_cfa_decap_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26654,7 +27274,8 @@ struct hwrm_cfa_decap_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26714,7 +27335,8 @@ struct hwrm_cfa_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26847,6 +27469,15 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
UINT32_C(0x1000)
+ /*
+ * If set to 1 there will be no attempt to allocate an on-chip try to
+ * offload this flow. If set to 0, which will keep compatibility with the
+ * older drivers, will cause the FW to attempt to allocate an on-chip flow
+ * counter for the newly created flow. This will keep the existing behavior
+ * with EM flows which always had an associated flow counter.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
+ UINT32_C(0x2000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -26977,13 +27608,45 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t flow_handle;
uint8_t unused_0[2];
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
uint32_t flow_counter_id;
@@ -26998,6 +27661,34 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
+struct hwrm_cfa_flow_alloc_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* No more L2 Context TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
+ /* No more action records */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
+ /* No more flow counters */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
+ /* No more wild-card TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
+ /* Hash collsion in exact match tables */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
+ /* Key is already installed */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
+ /* Flow Context DB is out of resource */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
+ HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_free *
**********************/
@@ -27021,7 +27712,8 @@ struct hwrm_cfa_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27034,7 +27726,9 @@ struct hwrm_cfa_flow_free_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint16_t unused_0;
+ /* Flow counter id to be freed. */
+ uint32_t flow_counter_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -27310,7 +28004,8 @@ struct hwrm_cfa_flow_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27420,7 +28115,8 @@ struct hwrm_cfa_flow_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27448,6 +28144,9 @@ struct hwrm_cfa_flow_flush_input {
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
UINT32_C(0x2)
+ /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
+ UINT32_C(0x8000000)
/*
* This specifies the size of flow handle entries provided by the driver
* in the flow table specified below. Only two flow handle size enums are defined.
@@ -27544,7 +28243,8 @@ struct hwrm_cfa_flow_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27684,7 +28384,8 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27733,7 +28434,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output {
***************************/
-/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -27751,7 +28452,8 @@ struct hwrm_cfa_flow_aging_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27773,16 +28475,40 @@ struct hwrm_cfa_flow_aging_cfg_input {
/* This bit must be '1' for the udp flow timer field to be configured */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
UINT32_C(0x4)
- /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ /* This bit must be '1' for the eem dma interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
+ UINT32_C(0x8)
+ /* This bit must be '1' for the eem notice interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
+ UINT32_C(0x10)
+ /* This bit must be '1' for the eem context memory maximum entries field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
+ UINT32_C(0x20)
+ /* This bit must be '1' for the eem context memory ID field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
+ UINT32_C(0x40)
+ /* This bit must be '1' for the eem context memory type field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
+ UINT32_C(0x80)
uint8_t flags;
/* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ /* Enumeration denoting the enable, disable eem flow aging configuration. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
+ (UINT32_C(0x0) << 1)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
uint8_t unused_0;
/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
uint32_t tcp_flow_timer;
@@ -27790,6 +28516,21 @@ struct hwrm_cfa_flow_aging_cfg_input {
uint32_t tcp_fin_timer;
/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
uint32_t udp_flow_timer;
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ uint16_t eem_ctx_mem_type;
+ /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
+ UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
@@ -27836,7 +28577,8 @@ struct hwrm_cfa_flow_aging_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27860,7 +28602,7 @@ struct hwrm_cfa_flow_aging_qcfg_input {
uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -27876,7 +28618,17 @@ struct hwrm_cfa_flow_aging_qcfg_output {
uint32_t tcp_fin_timer;
/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
uint32_t udp_flow_timer;
- uint8_t unused_0[3];
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ /* The context memory type for eem flow aging. */
+ uint16_t eem_ctx_mem_type;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -27910,7 +28662,8 @@ struct hwrm_cfa_flow_aging_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27986,7 +28739,8 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28051,7 +28805,8 @@ struct hwrm_cfa_pair_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28171,7 +28926,8 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28275,7 +29031,8 @@ struct hwrm_cfa_ctx_mem_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28371,7 +29128,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28434,7 +29192,8 @@ struct hwrm_cfa_ctx_mem_qctx_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28531,7 +29290,8 @@ struct hwrm_cfa_ctx_mem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28582,7 +29342,8 @@ struct hwrm_cfa_eem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28630,13 +29391,31 @@ struct hwrm_cfa_eem_qcaps_output {
* which are to be offloaded.
* Note if this bit is set then the path_rx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
/*
* When set to 1, indicates the configuration will apply to RX flows
* which are to be offloaded.
* Note if this bit is set then the path_tx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /*
+ * When set to 1, indicates the the FW supports the Centralized
+ * Memory Model. The concept designates one entity for the
+ * memory allocation while all others ‘subscribe’ to it.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * When set to 1, indicates the the FW supports the Detached
+ * Centralized Memory Model. The memory is allocated and managed
+ * as a separate entity. All PFs and VFs will be granted direct
+ * or semi-direct access to the allocated memory while none of
+ * which can interfere with the management of the memory.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x8)
uint32_t unused_0;
uint32_t supported;
/*
@@ -28712,7 +29491,8 @@ struct hwrm_cfa_eem_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28741,7 +29521,15 @@ struct hwrm_cfa_eem_cfg_input {
/* When set to 1, all offloaded flows will be sent to EEM. */
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- uint32_t unused_0;
+ /* When set to 1, secondary, 0 means primary. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
+ UINT32_C(0x8)
+ /*
+ * Group_id which used by Firmware to identify memory pools belonging
+ * to certain group.
+ */
+ uint16_t group_id;
+ uint16_t unused_0;
/*
* Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
* RECORD, EFC all have the same number of entries and all tables will be configured
@@ -28803,7 +29591,8 @@ struct hwrm_cfa_eem_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28878,7 +29667,8 @@ struct hwrm_cfa_eem_op_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28974,7 +29764,8 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29045,6 +29836,42 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
+ /*
+ * Value of 1 to indicate that firmware supports the dynamic allocation of an
+ * on-chip flow counter which can be used for EEM flows.
+ * Value of 0 indicates firmware does not support the dynamic allocation of an
+ * on-chip flow counter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
+ * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * Value of 1 to indicate that firmware supports untagged matching
+ * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
+ * indicates firmware does not support untagged matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * Value of 1 to indicate that firmware supports XDP filter. Value
+ * of 0 indicates firmware does not support XDP filter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * Value of 1 to indicate that the firmware support L2 header source
+ * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
+ * Value of 0 indicates firmware does not support L2 header source
+ * fields matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
+ UINT32_C(0x800)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -29056,6 +29883,81 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/******************
+ * hwrm_cfa_tflib *
+ ******************/
+
+
+/* hwrm_cfa_tflib_input (size:1024b/128B) */
+struct hwrm_cfa_tflib_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* unused. */
+ uint8_t unused0[4];
+ /* TFLIB request data. */
+ uint32_t tf_req[26];
+} __attribute__((packed));
+
+/* hwrm_cfa_tflib_output (size:5632b/704B) */
+struct hwrm_cfa_tflib_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* TFLIB response code */
+ uint32_t tf_resp_code;
+ /* TFLIB response data. */
+ uint32_t tf_resp[170];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/******************************
* hwrm_tunnel_dst_port_query *
******************************/
@@ -29079,7 +29981,8 @@ struct hwrm_tunnel_dst_port_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29177,7 +30080,8 @@ struct hwrm_tunnel_dst_port_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29274,7 +30178,8 @@ struct hwrm_tunnel_dst_port_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29451,7 +30356,8 @@ struct hwrm_stat_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29540,7 +30446,8 @@ struct hwrm_stat_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29602,7 +30509,8 @@ struct hwrm_stat_ctx_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29702,7 +30610,8 @@ struct hwrm_stat_ctx_eng_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29803,7 +30712,8 @@ struct hwrm_stat_ctx_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29863,7 +30773,8 @@ struct hwrm_pcie_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29970,7 +30881,8 @@ struct hwrm_exec_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30043,7 +30955,8 @@ struct hwrm_reject_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30116,7 +31029,8 @@ struct hwrm_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30204,7 +31118,8 @@ struct hwrm_fwd_async_event_cmpl_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30273,7 +31188,8 @@ struct hwrm_nvm_raw_write_blk_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30342,7 +31258,8 @@ struct hwrm_nvm_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30412,7 +31329,8 @@ struct hwrm_nvm_raw_dump_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30478,7 +31396,8 @@ struct hwrm_nvm_get_dir_entries_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30540,7 +31459,8 @@ struct hwrm_nvm_get_dir_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30601,7 +31521,8 @@ struct hwrm_nvm_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30722,7 +31643,8 @@ struct hwrm_nvm_modify_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30795,7 +31717,8 @@ struct hwrm_nvm_find_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30897,7 +31820,8 @@ struct hwrm_nvm_erase_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30957,7 +31881,8 @@ struct hwrm_nvm_get_dev_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30991,7 +31916,12 @@ struct hwrm_nvm_get_dev_info_output {
uint32_t reserved_size;
/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
uint32_t available_size;
- uint8_t unused_0[3];
+ /* This field represents the major version of NVM cfg */
+ uint8_t nvm_cfg_ver_maj;
+ /* This field represents the minor version of NVM cfg */
+ uint8_t nvm_cfg_ver_min;
+ /* This field represents the update version of NVM cfg */
+ uint8_t nvm_cfg_ver_upd;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -31025,7 +31955,8 @@ struct hwrm_nvm_mod_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31104,7 +32035,8 @@ struct hwrm_nvm_verify_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31177,7 +32109,8 @@ struct hwrm_nvm_install_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31340,7 +32273,8 @@ struct hwrm_nvm_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31413,7 +32347,8 @@ struct hwrm_nvm_get_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31548,7 +32483,8 @@ struct hwrm_nvm_set_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31678,7 +32614,8 @@ struct hwrm_nvm_validate_option_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v4 0/8] bnxt patchset
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (12 preceding siblings ...)
2019-05-28 19:23 ` [dpdk-dev] [PATCH v3 0/8] " Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt Lance Richardson
` (7 more replies)
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
14 siblings, 8 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
This patchset adds the following:
1) Support for vector mode TX and RX.
2) HWRM API update (split into multiple patches).
3) Fixes for RSS reta update and query.
It also updates the release notes.
v2:
* Squashed patches 3 and 4 from v1 patchset.
* Added Meson build support for vector mode PMD.
* Dropped two unnecessary code style changes from patch 3.
v3:
* Squashed three RSS RETA fix patches into one.
* Eliminated RTE_LIBRTE_BNXT_INC_VECTOR configuration flag.
* Addressed commit log issues from check-git-log.sh.
* Made subject line consistent for HWRM API update patches.
* Separated release notes updates to keep update with associated
patch (except for the first update for which the associated patch
has already been applied).
v4:
* The change squashed from patch 4 into patch 3 from the v1
patchset should have been squashed into patch 2; fixed in v4.
Ajit Khaparde (5):
net/bnxt: update release notes for bnxt
net/bnxt: fix RSS RETA indirection table ops
net/bnxt: update HWRM API to version 1.10.0.19
net/bnxt: update HWRM API to version 1.10.0.48
net/bnxt: update HWRM API to version 1.10.0.74
Lance Richardson (3):
net/bnxt: move Tx bd checking to header file
net/bnxt: compute and store scattered Rx status
net/bnxt: implement vector mode driver
doc/guides/rel_notes/release_19_08.rst | 6 +
drivers/net/bnxt/Makefile | 3 +
drivers/net/bnxt/bnxt_ethdev.c | 201 +-
drivers/net/bnxt/bnxt_hwrm.c | 1 +
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 ++
drivers/net/bnxt/bnxt_txr.c | 15 -
drivers/net/bnxt/bnxt_txr.h | 20 +
drivers/net/bnxt/hsi_struct_def_dpdk.h | 7573 ++++++++++++++++++++----
drivers/net/bnxt/meson.build | 4 +
13 files changed, 7219 insertions(+), 1106 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 18:16 ` Kevin Traynor
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
` (6 subsequent siblings)
7 siblings, 1 reply; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update release doc briefly describing updates to bnxt PMD,
including transmit optimization changes in the following
commits:
commit 5c26b1706862 ("net/bnxt: support bulk free of Tx mbufs")
commit f8dea49ef89b ("net/bnxt: optimize Tx batching code")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
doc/guides/rel_notes/release_19_08.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 5ebb564b1..2b66f41f5 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -54,6 +54,10 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
+* **Updated the bnxt PMD.**
+
+ Updated the bnxt PMD. The major enhancements include:
+ * Performance optimizations in non-vector Tx path
Removed Items
-------------
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt Lance Richardson
@ 2019-05-29 18:16 ` Kevin Traynor
2019-05-29 20:28 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Kevin Traynor @ 2019-05-29 18:16 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin
On 29/05/2019 16:02, Lance Richardson wrote:
> From: Ajit Khaparde <ajit.khaparde@broadcom.com>
>
> Update release doc briefly describing updates to bnxt PMD,
> including transmit optimization changes in the following
> commits:
>
> commit 5c26b1706862 ("net/bnxt: support bulk free of Tx mbufs")
> commit f8dea49ef89b ("net/bnxt: optimize Tx batching code")
>
The commit-id's are not correct, and it should be with Fixes tag
Fixes: 5ef3592c97b9 ("net/bnxt: support bulk free of Tx mbufs")
Fixes: 220de9869bc3 ("net/bnxt: optimize Tx batching")
> Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
> Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
> ---
> doc/guides/rel_notes/release_19_08.rst | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
> index 5ebb564b1..2b66f41f5 100644
> --- a/doc/guides/rel_notes/release_19_08.rst
> +++ b/doc/guides/rel_notes/release_19_08.rst
> @@ -54,6 +54,10 @@ New Features
> Also, make sure to start the actual text at the margin.
> =========================================================
>
> +* **Updated the bnxt PMD.**
> +
> + Updated the bnxt PMD. The major enhancements include:
> + * Performance optimizations in non-vector Tx path
>
> Removed Items
> -------------
>
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt
2019-05-29 18:16 ` Kevin Traynor
@ 2019-05-29 20:28 ` Lance Richardson
2019-05-29 20:35 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 20:28 UTC (permalink / raw)
To: Kevin Traynor; +Cc: dev, Ajit Khaparde, Ferruh Yigit, Maxime Coquelin
On Wed, May 29, 2019 at 2:16 PM Kevin Traynor <ktraynor@redhat.com> wrote:
>
> On 29/05/2019 16:02, Lance Richardson wrote:
> > From: Ajit Khaparde <ajit.khaparde@broadcom.com>
> >
> > Update release doc briefly describing updates to bnxt PMD,
> > including transmit optimization changes in the following
> > commits:
> >
> > commit 5c26b1706862 ("net/bnxt: support bulk free of Tx mbufs")
> > commit f8dea49ef89b ("net/bnxt: optimize Tx batching code")
> >
>
> The commit-id's are not correct, and it should be with Fixes tag
>
> Fixes: 5ef3592c97b9 ("net/bnxt: support bulk free of Tx mbufs")
> Fixes: 220de9869bc3 ("net/bnxt: optimize Tx batching")
>
Hi Kevin,
Oops, those IDs were from the dpdk-next-net repo. Will fix, and add
"Fixes" tag...
Thanks,
Lance
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt
2019-05-29 20:28 ` Lance Richardson
@ 2019-05-29 20:35 ` Lance Richardson
2019-05-29 20:38 ` Lance Richardson
0 siblings, 1 reply; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 20:35 UTC (permalink / raw)
To: Kevin Traynor; +Cc: dev, Ajit Khaparde, Ferruh Yigit, Maxime Coquelin
On Wed, May 29, 2019 at 4:28 PM Lance Richardson
<lance.richardson@broadcom.com> wrote:
>
> On Wed, May 29, 2019 at 2:16 PM Kevin Traynor <ktraynor@redhat.com> wrote:
> >
> > On 29/05/2019 16:02, Lance Richardson wrote:
> > > From: Ajit Khaparde <ajit.khaparde@broadcom.com>
> > >
> > > Update release doc briefly describing updates to bnxt PMD,
> > > including transmit optimization changes in the following
> > > commits:
> > >
> > > commit 5c26b1706862 ("net/bnxt: support bulk free of Tx mbufs")
> > > commit f8dea49ef89b ("net/bnxt: optimize Tx batching code")
> > >
> >
> > The commit-id's are not correct, and it should be with Fixes tag
> >
> > Fixes: 5ef3592c97b9 ("net/bnxt: support bulk free of Tx mbufs")
> > Fixes: 220de9869bc3 ("net/bnxt: optimize Tx batching")
> >
>
> Hi Kevin,
>
> Oops, those IDs were from the dpdk-next-net repo. Will fix, and add
> "Fixes" tag...
>
> Thanks,
>
> Lance
I jumped the gun... what is wrong with the commit IDs?
dpdk_upstream lance$ git remote show origin | grep URL
Fetch URL: https://github.com/DPDK/dpdk.git
Push URL: https://github.com/DPDK/dpdk.git
dpdk_upstream lance$ git log --oneline -s --abbrev=12 | grep bnxt | head
5ef3592c97b9 net/bnxt: support bulk free of Tx mbufs
220de9869bc3 net/bnxt: optimize Tx batching
Thanks,
Lance
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt
2019-05-29 20:35 ` Lance Richardson
@ 2019-05-29 20:38 ` Lance Richardson
0 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 20:38 UTC (permalink / raw)
To: Kevin Traynor; +Cc: dev, Ajit Khaparde, Ferruh Yigit, Maxime Coquelin
I see now that you had fixed them up... sorry for the noise.
On Wed, May 29, 2019 at 4:35 PM Lance Richardson
<lance.richardson@broadcom.com> wrote:
>
> On Wed, May 29, 2019 at 4:28 PM Lance Richardson
> <lance.richardson@broadcom.com> wrote:
> >
> > On Wed, May 29, 2019 at 2:16 PM Kevin Traynor <ktraynor@redhat.com> wrote:
> > >
> > > On 29/05/2019 16:02, Lance Richardson wrote:
> > > > From: Ajit Khaparde <ajit.khaparde@broadcom.com>
> > > >
> > > > Update release doc briefly describing updates to bnxt PMD,
> > > > including transmit optimization changes in the following
> > > > commits:
> > > >
> > > > commit 5c26b1706862 ("net/bnxt: support bulk free of Tx mbufs")
> > > > commit f8dea49ef89b ("net/bnxt: optimize Tx batching code")
> > > >
> > >
> > > The commit-id's are not correct, and it should be with Fixes tag
> > >
> > > Fixes: 5ef3592c97b9 ("net/bnxt: support bulk free of Tx mbufs")
> > > Fixes: 220de9869bc3 ("net/bnxt: optimize Tx batching")
> > >
> >
> > Hi Kevin,
> >
> > Oops, those IDs were from the dpdk-next-net repo. Will fix, and add
> > "Fixes" tag...
> >
> > Thanks,
> >
> > Lance
>
> I jumped the gun... what is wrong with the commit IDs?
>
> dpdk_upstream lance$ git remote show origin | grep URL
> Fetch URL: https://github.com/DPDK/dpdk.git
> Push URL: https://github.com/DPDK/dpdk.git
> dpdk_upstream lance$ git log --oneline -s --abbrev=12 | grep bnxt | head
> 5ef3592c97b9 net/bnxt: support bulk free of Tx mbufs
> 220de9869bc3 net/bnxt: optimize Tx batching
>
> Thanks,
>
> Lance
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v4 2/8] net/bnxt: move Tx bd checking to header file
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
` (5 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
vector-mode and non-vector transmit functions, move these functions
into bnxt_txr.h.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/net/bnxt/bnxt_txr.c | 15 ---------------
drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 9de12e0d0..16598ba63 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
return 0;
}
-static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
-{
- return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
- txq->tx_ring->tx_ring_struct->ring_mask);
-}
-
-static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
-{
- /* Tell compiler to fetch tx indices from memory. */
- rte_compiler_barrier();
-
- return ((txq->tx_ring->tx_ring_struct->ring_size -
- bnxt_tx_bds_in_hw(txq)) - 1);
-}
-
static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
struct bnxt_tx_queue *txq,
uint16_t *coal_pkts,
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index f802d5080..13ca04676 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -37,6 +37,21 @@ struct bnxt_sw_tx_bd {
unsigned short nr_bds;
};
+static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
+{
+ return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
+ txq->tx_ring->tx_ring_struct->ring_mask);
+}
+
+static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
+{
+ /* Tell compiler to fetch tx indices from memory. */
+ rte_compiler_barrier();
+
+ return ((txq->tx_ring->tx_ring_struct->ring_size -
+ bnxt_tx_bds_in_hw(txq)) - 1);
+}
+
void bnxt_free_tx_rings(struct bnxt *bp);
int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v4 3/8] net/bnxt: compute and store scattered Rx status
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 1/8] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 4/8] net/bnxt: implement vector mode driver Lance Richardson
` (4 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
In preparation for a bnxt vector-mode driver, compute and store
scattered_rx status for the device when started.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
v4:
* Moved a fix to bnxt_scattered_rx(), which is introduced in this patch,
from patch 4 into this patch. (The original version incorrectly
accounted for a possible QinQ header which was in fact already
accounted for).
drivers/net/bnxt/bnxt_ethdev.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index b0244d6d1..6295fec2a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -624,6 +624,26 @@ static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
return 0;
}
+/*
+ * Determine whether the current configuration requires support for scattered
+ * receive; return 1 if scattered receive is required and 0 if not.
+ */
+static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
+{
+ uint16_t buf_size;
+ int i;
+
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
+
+ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
+ RTE_PKTMBUF_HEADROOM);
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
+ return 1;
+ }
+ return 0;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -642,6 +662,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
+
bnxt_link_update_op(eth_dev, 1);
if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v4 4/8] net/bnxt: implement vector mode driver
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
` (2 preceding siblings ...)
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
` (3 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
Introduce SSE vector mode support for the bnxt pmd.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
v2:
* Squashed with v1 patch 4 ("fix double counting VLAN tags").
* Dropped two unnecessary coding style changes from bnxt_txr.h.
v3:
* Eliminated vector mode configration flag.
* Added RTE_ARCH_X86 checks around vector mode code.
* Added release notes item for SSE vector mode.
* Added RTE_ prefix to ETHER_HDR_LEN and ETHER_CRC_LEN.
v4:
* Corrected squash that was done for v2 of this patch, the
squashed change is now in patch 3 of this patch set.
doc/guides/rel_notes/release_19_08.rst | 1 +
drivers/net/bnxt/Makefile | 3 +
drivers/net/bnxt/bnxt_ethdev.c | 95 ++++-
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 +++++++++++++++++++++++++
drivers/net/bnxt/bnxt_txr.h | 5 +
drivers/net/bnxt/meson.build | 4 +
10 files changed, 602 insertions(+), 8 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 2b66f41f5..7e5ca3c34 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -58,6 +58,7 @@ New Features
Updated the bnxt PMD. The major enhancements include:
* Performance optimizations in non-vector Tx path
+ * Added support for SSE vector mode
Removed Items
-------------
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
index 8be3cb0e4..21a565063 100644
--- a/drivers/net/bnxt/Makefile
+++ b/drivers/net/bnxt/Makefile
@@ -41,6 +41,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_util.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += rte_pmd_bnxt.c
+ifeq ($(CONFIG_RTE_ARCH_X86), y)
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_rxtx_vec_sse.c
+endif
#
# Export include files
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 6295fec2a..bccba445a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -644,6 +644,67 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
return 0;
}
+static eth_rx_burst_t
+bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_ARCH_X86
+ /*
+ * Vector mode receive can be enabled only if scatter rx is not
+ * in use and rx offloads are limited to VLAN stripping and
+ * CRC stripping.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.rxmode.offloads &
+ ~(DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_KEEP_CRC |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM |
+ DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_VLAN_FILTER))) {
+ PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_recv_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d rx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.rxmode.offloads);
+#endif
+ return bnxt_recv_pkts;
+}
+
+static eth_tx_burst_t
+bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_ARCH_X86
+ /*
+ * Vector mode receive can be enabled only if scatter tx is not
+ * in use and tx offloads other than VLAN insertion are not
+ * in use.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.txmode.offloads &
+ ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
+ PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_xmit_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d tx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.txmode.offloads);
+#endif
+ return bnxt_xmit_pkts;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -674,6 +735,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
+ eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
bp->flags |= BNXT_FLAG_INIT_DONE;
return 0;
@@ -1600,9 +1663,13 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_dev_info dev_info;
+ uint32_t new_pkt_size;
uint32_t rc = 0;
uint32_t i;
+ new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS;
+
bnxt_dev_info_get_op(eth_dev, &dev_info);
if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
@@ -1611,6 +1678,23 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
return -EINVAL;
}
+#ifdef RTE_ARCH_X86
+ /*
+ * If vector-mode tx/rx is active, disallow any MTU change that would
+ * require scattered receive support.
+ */
+ if (eth_dev->data->dev_started &&
+ (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
+ eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
+ (new_pkt_size >
+ eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
+ PMD_DRV_LOG(ERR,
+ "MTU change would require scattered rx support. ");
+ PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
+ return -EINVAL;
+ }
+#endif
+
if (new_mtu > RTE_ETHER_MTU) {
bp->flags |= BNXT_FLAG_JUMBO;
bp->eth_dev->data->dev_conf.rxmode.offloads |=
@@ -1621,9 +1705,7 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
bp->flags &= ~BNXT_FLAG_JUMBO;
}
- eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
- new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
- VLAN_TAG_SIZE * 2;
+ eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
eth_dev->data->mtu = new_mtu;
PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
@@ -2658,9 +2740,10 @@ bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
RTE_PTYPE_UNKNOWN
};
- if (dev->rx_pkt_burst == bnxt_recv_pkts)
- return ptypes;
- return NULL;
+ if (!dev->rx_pkt_burst)
+ return NULL;
+
+ return ptypes;
}
static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index 1446d784f..fd3d0bd73 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -10,7 +10,8 @@
#include <rte_memory.h>
-#define RING_NEXT(ring, idx) (((idx) + 1) & (ring)->ring_mask)
+#define RING_ADV(ring, idx, n) (((idx) + (n)) & (ring)->ring_mask)
+#define RING_NEXT(ring, idx) RING_ADV(ring, idx, 1)
#define DB_IDX_MASK 0xffffff
#define DB_IDX_VALID (0x1 << 26)
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index f1ee9eede..2ce2ef427 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -355,6 +355,11 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
RTE_ETH_QUEUE_STATE_STARTED;
eth_dev->data->rx_queue_state[queue_idx] = queue_state;
rte_spinlock_init(&rxq->lock);
+
+#ifdef RTE_ARCH_X86
+ bnxt_rxq_vec_setup(rxq);
+#endif
+
out:
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h
index e5d6001d3..7c6b4dec9 100644
--- a/drivers/net/bnxt/bnxt_rxq.h
+++ b/drivers/net/bnxt/bnxt_rxq.h
@@ -22,6 +22,10 @@ struct bnxt_rx_queue {
uint16_t nb_rx_hold; /* num held free RX desc */
uint16_t rx_free_thresh; /* max free RX desc to hold */
uint16_t queue_id; /* RX queue index */
+#ifdef RTE_ARCH_X86
+ uint16_t rxrearm_nb; /* number of descs to reinit. */
+ uint16_t rxrearm_start; /* next desc index to reinit. */
+#endif
uint16_t reg_idx; /* RX queue register index */
uint16_t port_id; /* Device port identifier */
uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 3815a2199..d10cefb93 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -7,7 +7,7 @@
#define _BNXT_RXR_H_
#define B_RX_DB(db, prod) \
- (*(uint32_t *)db = (DB_KEY_RX | prod))
+ (*(uint32_t *)db = (DB_KEY_RX | (prod)))
#define BNXT_TPA_L4_SIZE(x) \
{ \
@@ -110,4 +110,11 @@ int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+
+#ifdef RTE_ARCH_X86
+uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
+int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
+#endif
+
#endif
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
new file mode 100644
index 000000000..1c32c986c
--- /dev/null
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright(c) 2019 Broadcom All rights reserved. */
+
+#include <inttypes.h>
+#include <stdbool.h>
+
+#include <rte_bitmap.h>
+#include <rte_byteorder.h>
+#include <rte_malloc.h>
+#include <rte_memory.h>
+#if defined(RTE_ARCH_X86)
+#include <tmmintrin.h>
+#else
+#error "bnxt vector pmd: unsupported target."
+#endif
+
+#include "bnxt.h"
+#include "bnxt_cpr.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxr.h"
+#include "bnxt_rxq.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "bnxt_txq.h"
+#include "bnxt_txr.h"
+
+/*
+ * RX Ring handling
+ */
+
+#define RTE_BNXT_MAX_RX_BURST 32
+#define RTE_BNXT_MAX_TX_BURST 32
+#define RTE_BNXT_RXQ_REARM_THRESH 32
+#define RTE_BNXT_DESCS_PER_LOOP 4
+
+static inline void
+bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
+{
+ struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
+ struct bnxt_sw_rx_bd *rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
+ struct rte_mbuf *mb0, *mb1;
+ int i;
+
+ const __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, 0);
+ const __m128i addrmask = _mm_set_epi64x(UINT64_MAX, 0);
+
+ /* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
+ if (rte_mempool_get_bulk(rxq->mb_pool,
+ (void *)rx_bufs,
+ RTE_BNXT_RXQ_REARM_THRESH) < 0) {
+ rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
+ RTE_BNXT_RXQ_REARM_THRESH;
+
+ return;
+ }
+
+ /* Initialize the mbufs in vector, process 2 mbufs in one loop */
+ for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
+ __m128i buf_addr0, buf_addr1;
+ __m128i rxbd0, rxbd1;
+
+ mb0 = rx_bufs[0].mbuf;
+ mb1 = rx_bufs[1].mbuf;
+
+ /* Load address fields from both mbufs */
+ buf_addr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
+ buf_addr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
+
+ /* Load both rx descriptors (preserving some existing fields) */
+ rxbd0 = _mm_loadu_si128((__m128i *)(rxbds + 0));
+ rxbd1 = _mm_loadu_si128((__m128i *)(rxbds + 1));
+
+ /* Add default offset to buffer address. */
+ buf_addr0 = _mm_add_epi64(buf_addr0, hdr_room);
+ buf_addr1 = _mm_add_epi64(buf_addr1, hdr_room);
+
+ /* Clear all fields except address. */
+ buf_addr0 = _mm_and_si128(buf_addr0, addrmask);
+ buf_addr1 = _mm_and_si128(buf_addr1, addrmask);
+
+ /* Clear address field in descriptor. */
+ rxbd0 = _mm_andnot_si128(addrmask, rxbd0);
+ rxbd1 = _mm_andnot_si128(addrmask, rxbd1);
+
+ /* Set address field in descriptor. */
+ rxbd0 = _mm_add_epi64(rxbd0, buf_addr0);
+ rxbd1 = _mm_add_epi64(rxbd1, buf_addr1);
+
+ /* Store descriptors to memory. */
+ _mm_store_si128((__m128i *)(rxbds++), rxbd0);
+ _mm_store_si128((__m128i *)(rxbds++), rxbd1);
+ }
+
+ rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
+ B_RX_DB(rxr->rx_doorbell, rxq->rxrearm_start - 1);
+ if (rxq->rxrearm_start >= rxq->nb_rx_desc)
+ rxq->rxrearm_start = 0;
+
+ rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
+}
+
+static uint32_t
+bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ uint32_t l3, pkt_type = 0;
+ uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
+ uint32_t flags_type;
+
+ vlan = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ t_ipcs = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
+ ip6 = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
+
+ flags_type = rxcmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
+
+ if (!t_ipcs && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_ipcs && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_ipcs && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ return pkt_type;
+}
+
+uint16_t
+bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_rx_queue *rxq = rx_queue;
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ int nb_rx_pkts = 0;
+ struct rx_pkt_cmpl *rxcmp;
+ bool evt = false;
+ const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
+ const __m128i shuf_msk =
+ _mm_set_epi8(15, 14, 13, 12, /* rss */
+ 0xFF, 0xFF, /* vlan_tci (zeroes) */
+ 3, 2, /* data_len */
+ 0xFF, 0xFF, 3, 2, /* pkt_len */
+ 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
+
+ /* If Rx Q was stopped return */
+ if (rxq->rx_deferred_start)
+ return 0;
+
+ if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
+ bnxt_rxq_rearm(rxq, rxr);
+
+ /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
+ nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
+
+ /* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP */
+ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
+
+ /* Handle RX burst request */
+ while (1) {
+ cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
+
+ rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
+
+ if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
+ break;
+
+ cpr->valid = FLIP_VALID(cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ if (likely(CMP_TYPE(rxcmp) == RX_PKT_CMPL_TYPE_RX_L2)) {
+ struct rx_pkt_cmpl_hi *rxcmp1;
+ uint32_t tmp_raw_cons;
+ uint16_t cp_cons;
+ struct rte_mbuf *mbuf;
+ __m128i mm_rxcmp, pkt_mb;
+
+ tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
+ cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
+ rxcmp1 = (struct rx_pkt_cmpl_hi *)
+ &cpr->cp_desc_ring[cp_cons];
+
+ if (!CMP_VALID(rxcmp1, tmp_raw_cons,
+ cpr->cp_ring_struct))
+ break;
+
+ raw_cons = tmp_raw_cons;
+ cons = rxcmp->opaque;
+
+ mbuf = rxr->rx_buf_ring[cons].mbuf;
+ rte_prefetch0(mbuf);
+ rxr->rx_buf_ring[cons].mbuf = NULL;
+
+ cpr->valid = FLIP_VALID(cp_cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ /* Set constant fields from mbuf initializer. */
+ _mm_store_si128((__m128i *)&mbuf->rearm_data,
+ mbuf_init);
+
+ /* Set mbuf pkt_len, data_len, and rss_hash fields. */
+ mm_rxcmp = _mm_load_si128((__m128i *)rxcmp);
+ pkt_mb = _mm_shuffle_epi8(mm_rxcmp, shuf_msk);
+ _mm_storeu_si128((void *)&mbuf->rx_descriptor_fields1,
+ pkt_mb);
+
+ rte_compiler_barrier();
+
+ if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
+ mbuf->ol_flags |= PKT_RX_RSS_HASH;
+
+ if (rxcmp1->flags2 &
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
+ mbuf->vlan_tci = rxcmp1->metadata &
+ (RX_PKT_CMPL_METADATA_VID_MASK |
+ RX_PKT_CMPL_METADATA_DE |
+ RX_PKT_CMPL_METADATA_PRI_MASK);
+ mbuf->ol_flags |= PKT_RX_VLAN;
+ }
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
+ rx_pkts[nb_rx_pkts++] = mbuf;
+ } else {
+ evt =
+ bnxt_event_hwrm_resp_handler(rxq->bp,
+ (struct cmpl_base *)rxcmp);
+ }
+
+ raw_cons = NEXT_RAW_CMP(raw_cons);
+ if (nb_rx_pkts == nb_pkts || evt)
+ break;
+ }
+ rxr->rx_prod = RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
+
+ rxq->rxrearm_nb += nb_rx_pkts;
+ cpr->cp_raw_cons = raw_cons;
+ if (nb_rx_pkts || evt)
+ B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
+
+ return nb_rx_pkts;
+}
+
+static inline void bnxt_next_cmpl(struct bnxt_cp_ring_info *cpr, uint32_t *idx,
+ bool *v, uint32_t inc)
+{
+ *idx += inc;
+ if (unlikely(*idx == cpr->cp_ring_struct->ring_size)) {
+ *v = !*v;
+ *idx = 0;
+ }
+}
+
+static void
+bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
+{
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ struct rte_mbuf **free = txq->free;
+ uint16_t cons = txr->tx_cons;
+ unsigned int blk = 0;
+
+ while (nr_pkts--) {
+ struct bnxt_sw_tx_bd *tx_buf;
+ struct rte_mbuf *mbuf;
+
+ tx_buf = &txr->tx_buf_ring[cons];
+ cons = RING_NEXT(txr->tx_ring_struct, cons);
+ mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
+ tx_buf->mbuf = NULL;
+
+ if (blk && mbuf->pool != free[0]->pool) {
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+ blk = 0;
+ }
+ free[blk++] = mbuf;
+ }
+ if (blk)
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+
+ txr->tx_cons = cons;
+}
+
+static void
+bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
+{
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ uint32_t nb_tx_pkts = 0;
+ struct tx_cmpl *txcmp;
+ struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
+ struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
+ uint32_t ring_mask = cp_ring_struct->ring_mask;
+
+ do {
+ cons = RING_CMPL(ring_mask, raw_cons);
+ txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
+
+ if (!CMPL_VALID(txcmp, cpr->valid))
+ break;
+ bnxt_next_cmpl(cpr, &cons, &cpr->valid, 1);
+ rte_prefetch0(&cp_desc_ring[cons]);
+
+ if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ nb_tx_pkts += txcmp->opaque;
+ else
+ RTE_LOG_DP(ERR, PMD,
+ "Unhandled CMP type %02x\n",
+ CMP_TYPE(txcmp));
+ raw_cons = cons;
+ } while (nb_tx_pkts < ring_mask);
+
+ if (nb_tx_pkts) {
+ bnxt_tx_cmp_vec(txq, nb_tx_pkts);
+ cpr->cp_raw_cons = raw_cons;
+ B_CP_DB(cpr, raw_cons, ring_mask);
+ }
+}
+
+#define TX_BD_FLAGS_CMPL ((1 << TX_BD_LONG_FLAGS_BD_CNT_SFT) | \
+ TX_BD_SHORT_FLAGS_COAL_NOW | \
+ TX_BD_SHORT_TYPE_TX_BD_SHORT | \
+ TX_BD_LONG_FLAGS_PACKET_END)
+
+#define TX_BD_FLAGS_NOCMPL (TX_BD_FLAGS_CMPL | TX_BD_LONG_FLAGS_NO_CMPL)
+
+static inline uint32_t
+bnxt_xmit_flags_len(uint16_t len, uint16_t flags)
+{
+ switch (len >> 9) {
+ case 0:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT512;
+ case 1:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT1K;
+ case 2:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ case 3:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ default:
+ return flags | TX_BD_LONG_FLAGS_LHINT_GTE2K;
+ }
+}
+
+static uint16_t
+bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_tx_queue *txq = tx_queue;
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ uint16_t prod = txr->tx_prod;
+ struct rte_mbuf *tx_mbuf;
+ struct tx_bd_long *txbd = NULL;
+ struct bnxt_sw_tx_bd *tx_buf;
+ uint16_t to_send;
+
+ nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
+
+ if (unlikely(nb_pkts == 0))
+ return 0;
+
+ /* Handle TX burst request */
+ to_send = nb_pkts;
+ while (to_send) {
+ tx_mbuf = *tx_pkts++;
+ rte_prefetch0(tx_mbuf);
+
+ tx_buf = &txr->tx_buf_ring[prod];
+ tx_buf->mbuf = tx_mbuf;
+ tx_buf->nr_bds = 1;
+
+ txbd = &txr->tx_desc_ring[prod];
+ txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
+ txbd->len = tx_mbuf->data_len;
+ txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
+ TX_BD_FLAGS_NOCMPL);
+ prod = RING_NEXT(txr->tx_ring_struct, prod);
+ to_send--;
+ }
+
+ /* Request a completion for last packet in burst */
+ if (txbd) {
+ txbd->opaque = nb_pkts;
+ txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
+ }
+
+ rte_compiler_barrier();
+ B_TX_DB(txr->tx_doorbell, prod);
+
+ txr->tx_prod = prod;
+
+ return nb_pkts;
+}
+
+uint16_t
+bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ int nb_sent = 0;
+ struct bnxt_tx_queue *txq = tx_queue;
+
+ /* Tx queue was stopped; wait for it to be restarted */
+ if (unlikely(txq->tx_deferred_start)) {
+ PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
+ return 0;
+ }
+
+ /* Handle TX completions */
+ if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
+ bnxt_handle_tx_cp_vec(txq);
+
+ while (nb_pkts) {
+ uint16_t ret, num;
+
+ num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
+ ret = bnxt_xmit_fixed_burst_vec(tx_queue,
+ &tx_pkts[nb_sent],
+ num);
+ nb_sent += ret;
+ nb_pkts -= ret;
+ if (ret < num)
+ break;
+ }
+
+ return nb_sent;
+}
+
+int __attribute__((cold))
+bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
+{
+ uintptr_t p;
+ struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
+
+ mb_def.nb_segs = 1;
+ mb_def.data_off = RTE_PKTMBUF_HEADROOM;
+ mb_def.port = rxq->port_id;
+ rte_mbuf_refcnt_set(&mb_def, 1);
+
+ /* prevent compiler reordering: rearm_data covers previous fields */
+ rte_compiler_barrier();
+ p = (uintptr_t)&mb_def.rearm_data;
+ rxq->mbuf_initializer = *(uint64_t *)p;
+ rxq->rxrearm_nb = 0;
+ rxq->rxrearm_start = 0;
+ return 0;
+}
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index 13ca04676..58678a1c8 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -57,6 +57,11 @@ int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+#ifdef RTE_ARCH_X86
+uint16_t bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
+#endif
+
int bnxt_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
int bnxt_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index e130f2712..4dda28f5b 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -18,3 +18,7 @@ sources = files('bnxt_cpr.c',
'bnxt_util.c',
'bnxt_vnic.c',
'rte_pmd_bnxt.c')
+
+if arch_subdir == 'x86'
+ sources += files('bnxt_rxtx_vec_sse.c')
+endif
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v4 5/8] net/bnxt: fix RSS RETA indirection table ops
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
` (3 preceding siblings ...)
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 4/8] net/bnxt: implement vector mode driver Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
` (2 subsequent siblings)
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson, stable
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
We are trying to update the indirection table for all the VNICs.
We should update the table only for the default vnic0.
Fix the reta update function to only update table entries that are
selected by the update mask. Translate queue number to firmware
group ID when updating an entry.
Fix reta query op to only return table entries as identfied by the
provided mask. Translate firmware group IDs to queue numbers.
Removed extraneous code from bnxt_reta_query_op().
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Rahul Gupta <rahul.gupta@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Cc: stable@dpdk.org
---
v3:
* Squashed three RSS RETA fix commits into one.
drivers/net/bnxt/bnxt_ethdev.c | 92 +++++++++++++++++++++++++---------
drivers/net/bnxt/bnxt_hwrm.c | 1 +
2 files changed, 70 insertions(+), 23 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index bccba445a..30dff72a6 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -618,12 +618,6 @@ static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
eth_dev->data->port_id);
}
-static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
-{
- bnxt_print_link_info(eth_dev);
- return 0;
-}
-
/*
* Determine whether the current configuration requires support for scattered
* receive; return 1 if scattered receive is required and 0 if not.
@@ -977,30 +971,72 @@ static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
}
+/* Return bnxt_rx_queue pointer corresponding to a given rxq. */
+static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
+{
+ if (qid >= bp->rx_nr_rings)
+ return NULL;
+
+ return bp->eth_dev->data->rx_queues[qid];
+}
+
+/* Return rxq corresponding to a given rss table ring/group ID. */
+static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
+{
+ unsigned int i;
+
+ for (i = 0; i < bp->rx_nr_rings; i++) {
+ if (bp->grp_info[i].fw_grp_id == fwr)
+ return i;
+ }
+
+ return INVALID_HW_RING_ID;
+}
+
static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
- struct bnxt_vnic_info *vnic;
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft;
int i;
+ if (!vnic->rss_table)
+ return -EINVAL;
+
if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* Update the RSS VNIC(s) */
- for (i = 0; i < bp->max_vnics; i++) {
- vnic = &bp->vnic_info[i];
- memcpy(vnic->rss_table, reta_conf, reta_size);
- bnxt_hwrm_vnic_rss_cfg(bp, vnic);
+
+ for (i = 0; i < reta_size; i++) {
+ struct bnxt_rx_queue *rxq;
+
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (!(reta_conf[idx].mask & (1ULL << sft)))
+ continue;
+
+ rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
+ if (!rxq) {
+ PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
+ return -EINVAL;
+ }
+
+ vnic->rss_table[i] =
+ vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
}
+
+ bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
@@ -1010,8 +1046,8 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
- struct rte_intr_handle *intr_handle
- = &bp->pdev->intr_handle;
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft, i;
/* Retrieve from the default VNIC */
if (!vnic)
@@ -1019,18 +1055,28 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
if (!vnic->rss_table)
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* EW - need to revisit here copying from uint64_t to uint16_t */
- memcpy(reta_conf, vnic->rss_table, reta_size);
- if (rte_intr_allow_others(intr_handle)) {
- if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
- bnxt_dev_lsc_intr_setup(eth_dev);
+ for (idx = 0, i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (reta_conf[idx].mask & (1ULL << sft)) {
+ uint16_t qid;
+
+ qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
+
+ if (qid == INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
+ return -EINVAL;
+ }
+ reta_conf[idx].reta[sft] = qid;
+ }
}
return 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index 4f0142cdb..20b45c23a 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1607,6 +1607,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
req.hash_key_tbl_addr =
rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
+ req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v4 6/8] net/bnxt: update HWRM API to version 1.10.0.19
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
` (4 preceding siblings ...)
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.19
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3112 +++++++++++++++++++-----
1 file changed, 2514 insertions(+), 598 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index e80057936..ea9a7d40e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2018 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Limited
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -68,9 +68,9 @@ struct hwrm_resp_hdr {
/* RoCE slow path command */
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
/* RoCE slow path command to query CC Gen1 support. */
-#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
/* RoCE slow path command to modify CC Gen1 support. */
-#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
/* Engine CKV - The device's serial number. */
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
/* Engine CKV - Per-function random nonce data. */
@@ -366,6 +366,7 @@ struct cmd_nums {
#define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
#define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
#define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
+ #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
#define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
#define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
@@ -442,6 +443,14 @@ struct cmd_nums {
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -591,61 +600,79 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ /*
+ * This error code is only reported by firmware when the specific
+ * request is not able to process when the HOT reset in progress.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances are not capable of hot reset.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ /*
+ * This value indicates that the HWRM response is in TLV format and
+ * should be interpreted as one or more TLVs starting with the
+ * hwrm_resp_hdr TLV. This value is not an indicatation of any error
+ * by itself, just an indicatation that the response should be parsed
+ * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
+ */
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -705,11 +732,11 @@ struct hwrm_err_output {
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
#define HWRM_VERSION_MAJOR 1
-#define HWRM_VERSION_MINOR 9
-#define HWRM_VERSION_UPDATE 2
+#define HWRM_VERSION_MINOR 10
+#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 53
-#define HWRM_VERSION_STR "1.9.2.53"
+#define HWRM_VERSION_RSVD 19
+#define HWRM_VERSION_STR "1.10.0.19"
/****************
* hwrm_ver_get *
@@ -959,6 +986,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
UINT32_C(0x100)
+ /*
+ * If set to 1, firmware is capable to support flow aging.
+ * If set to 0, firmware is not capable to support flow aging.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
+ UINT32_C(0x200)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -2031,7 +2065,7 @@ struct cmpl_base {
#define CMPL_BASE_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
/*
@@ -2116,7 +2150,7 @@ struct tx_cmpl {
#define TX_CMPL_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
@@ -2408,30 +2442,31 @@ struct rx_pkt_cmpl_hi {
* inner packet and that the ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the t_ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the t_l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
+ (UINT32_C(0x0) << 4)
/*
* The metadata field contains the VLAN tag and TPID value.
* - metadata[11:0] contains the vlan VID value.
@@ -2439,16 +2474,70 @@ struct rx_pkt_cmpl_hi {
* - metadata[15:13] contains the vlan PRI value.
* - metadata[31:16] contains the vlan TPID value.
*/
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
+ (UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
* This value is only valid if itype indicates a packet
* with an IP header.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2511,8 +2600,14 @@ struct rx_pkt_cmpl_hi {
*/
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
(UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
+ RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This indicates that there was an error in the IP header
* checksum.
@@ -2553,7 +2648,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 9)
@@ -2611,7 +2706,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 12)
@@ -2854,28 +2949,33 @@ struct rx_tpa_start_cmpl_hi {
* inner packet and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
+ UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the sum passed
* for all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
+ UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
+ UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the sum passed for
* all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
+ UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
+ UINT32_C(0xf0)
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
(UINT32_C(0x0) << 4)
@@ -2888,13 +2988,71 @@ struct rx_tpa_start_cmpl_hi {
*/
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
(UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
+ UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
+ UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
+ UINT32_C(0xc00)
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set. For TPA Start completions,
+ * the complete checksum is calculated for the first packet in the
+ * aggregation only.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2911,13 +3069,41 @@ struct rx_tpa_start_cmpl_hi {
/* When meta_format=1, this value is the VLAN TPID. */
#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
- uint16_t v2;
+ uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define RX_TPA_START_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for the packet that was found after part of the
+ * packet was already placed. The packet should be treated as
+ * invalid.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This field identifies the CFA action rule that was used for this
* packet.
@@ -3034,11 +3220,11 @@ struct rx_tpa_end_cmpl {
/*
* This value indicates what the inner packet determined for the
* packet was.
- * - 2 TCP Packet
- * Indicates that the packet was IP and TCP. This indicates
- * that the ip_cs field is valid and that the tcp_udp_cs
- * field is valid and contains the TCP checksum.
- * This also indicates that the payload_offset field is valid.
+ * - 2 TCP Packet
+ * Indicates that the packet was IP and TCP. This indicates
+ * that the ip_cs field is valid and that the tcp_udp_cs
+ * field is valid and contains the TCP checksum.
+ * This also indicates that the payload_offset field is valid.
*/
#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
@@ -3117,13 +3303,28 @@ struct rx_tpa_end_cmpl_hi {
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
- uint32_t tpa_dup_acks;
+ uint16_t tpa_dup_acks;
/*
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+ /*
+ * This value indicated the offset in bytes from the beginning of
+ * the packet where the inner payload starts. This value is valid
+ * for TCP, UDP, FCoE and RoCE packets
+ */
+ uint8_t payload_offset;
+ /*
+ * The value is the total number of aggregation buffers that were
+ * used in the TPA operation. All TPA aggregation buffer completions
+ * preceed the TPA End completion. If the value is zero, then the
+ * aggregation is completely contained in the buffer space provided
+ * in the aggregation start completion.
+ * Note that the field is simply provided as a cross check.
+ */
+ uint8_t tpa_agg_bufs;
/*
* This value is the valid when TPA completion is active. It
* indicates the length of the longest segment of the TPA operation
@@ -3154,6 +3355,9 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
/*
* This error occurs when there is a fatal HW problem in
* the chip only. It indicates that there were not
@@ -3162,6 +3366,12 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
(UINT32_C(0x2) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
/*
* This error occurs when TPA block was not configured to
* reserve adequate BDs for TPA operations on this RX
@@ -3174,8 +3384,14 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
(UINT32_C(0x4) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
+ RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/* unused5 is 16 b */
uint16_t unused_4;
/*
@@ -3239,15 +3455,23 @@ struct eject_cmpl {
* records. Odd values indicate 32B
* records.
*/
- #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
- #define EJECT_CMPL_TYPE_SFT 0
+ #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define EJECT_CMPL_TYPE_SFT 0
/*
* Statistics Ejection Completion:
* Completion of statistics data ejection buffer.
* Length = 16B
*/
- #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
- #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
+ #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
+ #define EJECT_CMPL_FLAGS_SFT 6
+ /*
+ * When this bit is '1', it indicates a packet that has an
+ * error of some type. Type of error is indicated in
+ * error_flags.
+ */
+ #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
/*
* This is the length of the statistics data stored in this
* buffer.
@@ -3258,13 +3482,47 @@ struct eject_cmpl {
* buffer corresponds to.
*/
uint32_t opaque;
- uint32_t v;
+ uint16_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
+ #define EJECT_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for statistics ejection. The statistics ejection should
+ * be treated as invalid
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Did Not Fit:
+ * Statistics did not fit into aggregation buffer provided.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
+ (UINT32_C(0x1) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+ /* reserved16 is 16 b */
+ uint16_t reserved16;
/* unused3 is 32 b */
uint32_t unused_2;
} __attribute__((packed));
@@ -3470,6 +3728,24 @@ struct hwrm_async_event_cmpl {
/* Default VNIC Configuration Change */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
UINT32_C(0x35)
+ /* HW flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ /*
+ * A debug notification being posted to the driver. These
+ * notifications are purely for diagnostic purpose and should not be
+ * used for functional purpose. The driver is not supposed to act
+ * on these messages except to log/record it.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
+ UINT32_C(0x37)
+ /*
+ * A trace log message. This contains firmware trace logs string
+ * embedded in the asynchronous message. This is an experimental
+ * event, not meant for production use at this time.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
/* HWRM Error */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
UINT32_C(0xff)
@@ -4111,9 +4387,19 @@ struct hwrm_async_event_cmpl_reset_notify {
/* opaque is 7 b */
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
- /* 8-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 8-lsb timestamp (100-msec resolution)
+ * The Minimum time required for the Firmware readiness after sending this
+ * notification to the driver instances.
+ */
uint8_t timestamp_lo;
- /* 16-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 16-lsb timestamp (100-msec resolution)
+ * The Maximum Firmware Reset bail out value in the order of 100
+ * milli seconds. The driver instances will use this value to re-initiate the
+ * registration process again if the core firmware didn’t set the ready
+ * state bit.
+ */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
@@ -4829,6 +5115,73 @@ struct hwrm_async_event_cmpl_default_vnic_change {
10
} __attribute__((packed));
+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_flow_aged {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of a hw flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates flow ID this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
+ UINT32_C(0x7fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
+ 0
+ /* Indicates flow direction this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x80000000)
+ /*
+ * If this bit set to 0, then it indicates that the aged
+ * event was rx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 31)
+ /*
+ * If this bit is set to 1, then it indicates that the aged
+ * event was tx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
struct hwrm_async_event_cmpl_hwrm_error {
uint16_t type;
@@ -5682,7 +6035,7 @@ struct hwrm_func_qcaps_output {
/*
* If the query is for a VF, then this flag shall be ignored,
* If this query is for a PF and this flag is set to 1,
- * then the PF has the capability to administer another PF.
+ * then the PF has the administrative privilege to configure another PF
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
UINT32_C(0x40000)
@@ -5700,6 +6053,19 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
UINT32_C(0x100000)
+ /*
+ * If 1, then FW has capability to allocate TX rings dynamically
+ * in ring alloc even if PF reserved pool is zero.
+ * This bit will be used only for PFs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x200000)
+ /*
+ * When this bit is '1', it indicates that core firmware is
+ * capable of Hot Reset.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
+ UINT32_C(0x400000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5864,7 +6230,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_func_qcfg_output (size:640b/80B) */
+/* hwrm_func_qcfg_output (size:704b/88B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -5951,6 +6317,13 @@ struct hwrm_func_qcfg_output {
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
UINT32_C(0x40)
+ /*
+ * If set to 1, then secure mode is enabled for this function or device.
+ * If set to 0, then secure mode is disabled (or normal mode) for this
+ * function or device.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
+ UINT32_C(0x80)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5995,7 +6368,8 @@ struct hwrm_func_qcfg_output {
uint16_t alloc_vnics;
/*
* The maximum transmission unit of the function.
- * For rings allocated on this function, this default
+ * If the reported mtu value is non-zero then it will used for the
+ * rings allocated on this function. otherwise the default
* value is used if ring MTU is not specified.
*/
uint16_t mtu;
@@ -6222,7 +6596,27 @@ struct hwrm_func_qcfg_output {
* reserved for itself (since the NQs must be contiguous in HW).
*/
uint16_t alloc_msix;
- uint8_t unused_2[5];
+ /*
+ * The number of registered VF’s associated with the PF. This field
+ * should be ignored when the request received on the VF interface.
+ * This field will be updated on the PF interface to initiate
+ * the unregister request on PF in the HOT Reset Process.
+ */
+ uint16_t registered_vfs;
+ uint8_t unused_1[3];
+ /*
+ * For backward compatibility this field must be set to 1.
+ * Older drivers might look for this field to be 1 before
+ * processing the message.
+ */
+ uint8_t always_1;
+ /*
+ * This GRC address location is used by the Host driver interfaces to poll
+ * the adapter ready state to re-initiate the registration process again
+ * after receiving the RESET Notify event.
+ */
+ uint32_t reset_addr_poll;
+ uint8_t unused_2[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -6424,6 +6818,13 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
+ /*
+ * When this bit it set, even if PF reserved pool size is zero,
+ * FW will allow driver to create TX rings in ring alloc,
+ * by reserving TX ring, S3 node dynamically.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x400000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7181,6 +7582,17 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
UINT32_C(0x8)
+ /*
+ * When this bit is '1', the function is indicating support of
+ * Hot Reset. The driver interface will destroy the resources,
+ * unregister the function and register again up on receiving
+ * the RESET_NOTIFY Async notification from the core firmware.
+ * The core firmware will this use flag and trigger the Hot Reset
+ * process only if all the registered driver instances are capable
+ * of this support.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
+ UINT32_C(0x10)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10774,6 +11186,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
@@ -10878,6 +11292,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
@@ -10930,6 +11346,9 @@ struct hwrm_port_phy_cfg_input {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* This value controls the wirespeed feature. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11159,6 +11578,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
@@ -11238,6 +11659,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
+ UINT32_C(0x4000)
/*
* Current setting of forced link speed.
* When the link speed is not being forced, this
@@ -11267,6 +11691,9 @@ struct hwrm_port_phy_qcfg_output {
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
+ UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11353,6 +11780,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11408,6 +11837,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* Current setting for wirespeed. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11574,8 +12006,20 @@ struct hwrm_port_phy_qcfg_output {
/* 1G_baseCX */
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
UINT32_C(0x1b)
+ /* 100G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
+ UINT32_C(0x1c)
+ /* 100G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
+ UINT32_C(0x1d)
+ /* 100G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
+ UINT32_C(0x1e)
+ /* 100G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
+ UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
+ HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
/* This value represents a media type. */
uint8_t media_type;
/* Unknown */
@@ -21081,6 +21525,15 @@ struct hwrm_cfa_l2_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -21887,6 +22340,15 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22107,6 +22569,12 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22212,6 +22680,12 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22312,6 +22786,12 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22517,8 +22997,14 @@ struct hwrm_cfa_encap_record_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -22872,6 +23358,15 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23381,6 +23876,15 @@ struct hwrm_cfa_em_flow_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23586,13 +24090,13 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_profile_alloc *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23620,266 +24124,1670 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
- */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
/*
- * This bit must be '1' for the src_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
- UINT32_C(0x4)
+ uint16_t reserved1;
/*
- * This bit must be '1' for the dst_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
- UINT32_C(0x8)
- /*
+ uint32_t reserved2;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_meter_profile_free *
+ *******************************/
+
+
+/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_profile_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_meter_profile_cfg *
+ ******************************/
+
+
+/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
+ UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint32_t reserved;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************************
+ * hwrm_cfa_meter_instance_alloc *
+ *********************************/
+
+
+/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
+ UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
+
+
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the src_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x8)
+ /*
* This bit must be '1' for the ovlan_vid field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
- UINT32_C(0x10)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the t_ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the t_ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the ethertype field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the src_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the dst_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the ipaddr_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the ip_protocol field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the src_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the dst_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x10000)
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
+ */
+ uint32_t tunnel_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0;
+ uint16_t unused_1;
+ /*
+ * This value indicates the source MAC address in
+ * the Ethernet header.
+ */
+ uint8_t src_macaddr[6];
+ uint8_t unused_2[2];
/*
- * This bit must be '1' for the ivlan_vid field to be
- * configured.
+ * This value indicates the destination MAC address in
+ * the Ethernet header.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
- UINT32_C(0x20)
+ uint8_t dst_macaddr[6];
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ivlan_vid;
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ivlan_vid;
+ /* This value indicates the ethertype in the Ethernet header. */
+ uint16_t ethertype;
+ /*
+ * This value indicates the type of IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
+ */
+ uint8_t ip_addr_type;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* IPv4 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ UINT32_C(0x4)
+ /* IPv6 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+ UINT32_C(0x6)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ /*
+ * The value of protocol filed in IP header.
+ * Applies to UDP and TCP traffic.
+ * 6 - TCP
+ * 17 - UDP
+ */
+ uint8_t ip_protocol;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+ UINT32_C(0x0)
+ /* TCP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+ UINT32_C(0x6)
+ /* UDP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+ UINT32_C(0x11)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint16_t unused_3;
+ uint32_t unused_4;
+ /*
+ * The value of source IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t src_ipaddr[4];
+ /*
+ * The value of destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t dst_ipaddr[4];
+ /*
+ * The value of source port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t src_port;
+ /*
+ * The value of destination port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t dst_port;
+ /*
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path.
+ */
+ uint16_t dst_id;
+ /*
+ * If set, this value shall represent the L2 context that matches the L2
+ * information of the decap filter.
+ */
+ uint16_t l2_ctxt_ref_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_decap_filter_free *
+ ******************************/
+
+
+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_decap_filter_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_flow_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
+ UINT32_C(0x1)
+ /* num_vlan is 2 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
+ UINT32_C(0x6)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
+ /* no tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
+ (UINT32_C(0x0) << 1)
+ /* 1 tag */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
+ (UINT32_C(0x1) << 1)
+ /* 2 tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
+ (UINT32_C(0x2) << 1)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
+ /* Enumeration denoting the Flow Type. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
+ UINT32_C(0x38)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
+ /* L2 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
+ (UINT32_C(0x0) << 3)
+ /* IPV4 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
+ (UINT32_C(0x1) << 3)
+ /* IPV6 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
+ (UINT32_C(0x2) << 3)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
/*
- * This bit must be '1' for the t_ovlan_vid field to be
- * configured.
+ * when set to 1, indicates TX flow offload for function specified in src_fid and
+ * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
+ * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
+ * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
+ * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
+ * belong to the children VFs of the same PF to indicate VM to VM flow.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
UINT32_C(0x40)
/*
- * This bit must be '1' for the t_ivlan_vid field to be
- * configured.
+ * when set to 1, indicates RX flow offload for function specified in dst_fid and
+ * the src_fid should be set to invalid value.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x80)
/*
- * This bit must be '1' for the ethertype field to be
- * configured.
+ * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
+ * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
+ * This flag is only valid when the flow direction is RX.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
/*
- * This bit must be '1' for the src_ipaddr field to be
- * configured.
+ * Tx Flow: vf fid.
+ * Rx Flow: pf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ uint16_t src_fid;
+ /* Tunnel handle valid when tunnel flag is set. */
+ uint32_t tunnel_handle;
+ uint16_t action_flags;
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* recycle is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* meter is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /* nat_src is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
+ UINT32_C(0x20)
+ /* nat_dest is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
+ UINT32_C(0x40)
+ /* nat_ipv4_address is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
+ UINT32_C(0x80)
+ /* l2_header_rewrite is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
+ UINT32_C(0x100)
+ /* ttl_decrement is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
UINT32_C(0x200)
/*
- * This bit must be '1' for the dst_ipaddr field to be
- * configured.
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header. The type of tunnel
+ * is specified in the tunnel_type field.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
UINT32_C(0x400)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x800)
/*
- * This bit must be '1' for the ipaddr_type field to be
- * configured.
+ * Tx Flow: pf or vf fid.
+ * Rx Flow: vf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
- UINT32_C(0x800)
+ uint16_t dst_fid;
+ /* VLAN tpid, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tci;
+ /* Meter id, valid when meter flag is set. */
+ uint16_t act_meter_id;
+ /* Flow with the same l2 context tcam key. */
+ uint16_t ref_flow_handle;
+ /* This value sets the match value for the ethertype. */
+ uint16_t ethertype;
+ /* valid when num tags is 1 or 2. */
+ uint16_t outer_vlan_tci;
+ /* This value sets the match value for the Destination MAC address. */
+ uint16_t dmac[3];
+ /* valid when num tags is 2. */
+ uint16_t inner_vlan_tci;
+ /* This value sets the match value for the Source MAC address. */
+ uint16_t smac[3];
+ /* The bit length of destination IP address mask. */
+ uint8_t ip_dst_mask_len;
+ /* The bit length of source IP address mask. */
+ uint8_t ip_src_mask_len;
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
/*
- * This bit must be '1' for the ip_protocol field to be
- * configured.
+ * The value of source port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
- UINT32_C(0x1000)
+ uint16_t l4_src_port;
/*
- * This bit must be '1' for the src_port field to be
- * configured.
+ * The value of source port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
- UINT32_C(0x2000)
+ uint16_t l4_src_port_mask;
/*
- * This bit must be '1' for the dst_port field to be
- * configured.
+ * The value of destination port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
- UINT32_C(0x4000)
+ uint16_t l4_dst_port;
/*
- * This bit must be '1' for the dst_id field to be
- * configured.
+ * The value of destination port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x8000)
+ uint16_t l4_dst_port_mask;
/*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
+ * NAT IPv4/6 address based on address type flag.
+ * 0 values are ignored.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x10000)
+ uint32_t nat_ip_address[4];
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
/*
- * Tunnel identifier.
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
+ * The NAT source/destination port based on direction flag.
+ * Applies to UDP and TCP traffic.
+ * 0 values are ignored.
*/
- uint32_t tunnel_id;
+ uint16_t nat_port;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* The value of ip protocol. */
+ uint8_t ip_proto;
/* Tunnel Type. */
uint8_t tunnel_type;
/* Non-tunnel */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
/* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
UINT32_C(0x3)
/* IP in IP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
/* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
UINT32_C(0x7)
/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
UINT32_C(0x8)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0;
- uint16_t unused_1;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
+struct hwrm_cfa_flow_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[2];
/*
- * This value indicates the source MAC address in
- * the Ethernet header.
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_free *
+ **********************/
+
+
+/* hwrm_cfa_flow_free_input (size:256b/32B) */
+struct hwrm_cfa_flow_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t src_macaddr[6];
- uint8_t unused_2[2];
+ uint16_t cmpl_ring;
/*
- * This value indicates the destination MAC address in
- * the Ethernet header.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t dst_macaddr[6];
+ uint16_t seq_id;
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the Ethernet header.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t ovlan_vid;
+ uint16_t target_id;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the Ethernet header.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t ivlan_vid;
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_free_output (size:256b/32B) */
+struct hwrm_cfa_flow_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* packet is 64 b */
+ uint64_t packet;
+ /* byte is 64 b */
+ uint64_t byte;
+ uint8_t unused_0[7];
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the tunnel Ethernet header.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t t_ovlan_vid;
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_info *
+ **********************/
+
+
+/* hwrm_cfa_flow_info_input (size:256b/32B) */
+struct hwrm_cfa_flow_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the tunnel Ethernet header.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t t_ivlan_vid;
- /* This value indicates the ethertype in the Ethernet header. */
- uint16_t ethertype;
+ uint16_t cmpl_ring;
/*
- * This value indicates the type of IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t ip_addr_type;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* IPv4 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
- UINT32_C(0x4)
- /* IPv6 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
- UINT32_C(0x6)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ uint16_t seq_id;
/*
- * The value of protocol filed in IP header.
- * Applies to UDP and TCP traffic.
- * 6 - TCP
- * 17 - UDP
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint8_t ip_protocol;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
- UINT32_C(0x0)
- /* TCP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
- UINT32_C(0x6)
- /* UDP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
- UINT32_C(0x11)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
- uint16_t unused_3;
- uint32_t unused_4;
+ uint16_t target_id;
/*
- * The value of source IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t src_ipaddr[4];
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ /* Max flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
+ UINT32_C(0xfff)
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
+ /* CNP flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
+ UINT32_C(0x1000)
+ /* RoCEv1 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
+ UINT32_C(0x2000)
+ /* RoCEv2 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
+ UINT32_C(0x4000)
+ /* Direction rx = 1 */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
+ UINT32_C(0x8000)
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_info_output (size:448b/56B) */
+struct hwrm_cfa_flow_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* flags is 8 b */
+ uint8_t flags;
+ /* profile is 8 b */
+ uint8_t profile;
+ /* src_fid is 16 b */
+ uint16_t src_fid;
+ /* dst_fid is 16 b */
+ uint16_t dst_fid;
+ /* l2_ctxt_id is 16 b */
+ uint16_t l2_ctxt_id;
+ /* em_info is 64 b */
+ uint64_t em_info;
+ /* tcam_info is 64 b */
+ uint64_t tcam_info;
+ /* vfp_tcam_info is 64 b */
+ uint64_t vfp_tcam_info;
+ /* ar_id is 16 b */
+ uint16_t ar_id;
+ /* flow_handle is 16 b */
+ uint16_t flow_handle;
+ /* tunnel_handle is 32 b */
+ uint32_t tunnel_handle;
+ /* The flow aging timer for the flow, the unit is 100 milliseconds */
+ uint16_t flow_timer;
+ uint8_t unused_0[5];
/*
- * The value of destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint32_t dst_ipaddr[4];
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_flush *
+ ***********************/
+
+
+/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+struct hwrm_cfa_flow_flush_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * The value of source port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t src_port;
+ uint16_t cmpl_ring;
/*
- * The value of destination port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t dst_port;
+ uint16_t seq_id;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t dst_id;
+ uint16_t target_id;
/*
- * If set, this value shall represent the L2 context that matches the L2
- * information of the decap filter.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t l2_ctxt_ref_id;
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_alloc_output {
+/* hwrm_cfa_flow_flush_output (size:128b/16B) */
+struct hwrm_cfa_flow_flush_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23888,9 +25796,7 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -23901,13 +25807,13 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_decap_filter_free *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_stats *
+ ***********************/
-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_decap_filter_free_input {
+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
+struct hwrm_cfa_flow_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23935,13 +25841,53 @@ struct hwrm_cfa_decap_filter_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[4];
+ /* Flow handle. */
+ uint16_t num_flows;
+ /* Flow handle. */
+ uint16_t flow_handle_0;
+ /* Flow handle. */
+ uint16_t flow_handle_1;
+ /* Flow handle. */
+ uint16_t flow_handle_2;
+ /* Flow handle. */
+ uint16_t flow_handle_3;
+ /* Flow handle. */
+ uint16_t flow_handle_4;
+ /* Flow handle. */
+ uint16_t flow_handle_5;
+ /* Flow handle. */
+ uint16_t flow_handle_6;
+ /* Flow handle. */
+ uint16_t flow_handle_7;
+ /* Flow handle. */
+ uint16_t flow_handle_8;
+ /* Flow handle. */
+ uint16_t flow_handle_9;
+ uint8_t unused_0[2];
+ /* Flow ID of a flow. */
+ uint32_t flow_id_0;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_1;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_2;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_3;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_4;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_5;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_6;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_7;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_8;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_9;
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_free_output {
+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
+struct hwrm_cfa_flow_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23950,6 +25896,46 @@ struct hwrm_cfa_decap_filter_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* packet_0 is 64 b */
+ uint64_t packet_0;
+ /* packet_1 is 64 b */
+ uint64_t packet_1;
+ /* packet_2 is 64 b */
+ uint64_t packet_2;
+ /* packet_3 is 64 b */
+ uint64_t packet_3;
+ /* packet_4 is 64 b */
+ uint64_t packet_4;
+ /* packet_5 is 64 b */
+ uint64_t packet_5;
+ /* packet_6 is 64 b */
+ uint64_t packet_6;
+ /* packet_7 is 64 b */
+ uint64_t packet_7;
+ /* packet_8 is 64 b */
+ uint64_t packet_8;
+ /* packet_9 is 64 b */
+ uint64_t packet_9;
+ /* byte_0 is 64 b */
+ uint64_t byte_0;
+ /* byte_1 is 64 b */
+ uint64_t byte_1;
+ /* byte_2 is 64 b */
+ uint64_t byte_2;
+ /* byte_3 is 64 b */
+ uint64_t byte_3;
+ /* byte_4 is 64 b */
+ uint64_t byte_4;
+ /* byte_5 is 64 b */
+ uint64_t byte_5;
+ /* byte_6 is 64 b */
+ uint64_t byte_6;
+ /* byte_7 is 64 b */
+ uint64_t byte_7;
+ /* byte_8 is 64 b */
+ uint64_t byte_8;
+ /* byte_9 is 64 b */
+ uint64_t byte_9;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -23961,13 +25947,13 @@ struct hwrm_cfa_decap_filter_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_alloc *
- ***********************/
+/***********************************
+ * hwrm_cfa_flow_aging_timer_reset *
+ ***********************************/
-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_flow_alloc_input {
+/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_timer_reset_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23989,219 +25975,21 @@ struct hwrm_cfa_flow_alloc_input {
*/
uint16_t target_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint16_t flags;
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
- UINT32_C(0x1)
- /* num_vlan is 2 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
- UINT32_C(0x6)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
- /* no tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
- (UINT32_C(0x0) << 1)
- /* 1 tag */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
- (UINT32_C(0x1) << 1)
- /* 2 tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
- (UINT32_C(0x2) << 1)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
- /* Enumeration denoting the Flow Type. */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
- UINT32_C(0x38)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
- /* L2 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
- (UINT32_C(0x0) << 3)
- /* IPV4 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
- (UINT32_C(0x1) << 3)
- /* IPV6 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
- (UINT32_C(0x2) << 3)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
- /*
- * when set to 1, indicates TX flow offload for function specified in src_fid and
- * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
- * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
- * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
- * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
- * belong to the children VFs of the same PF to indicate VM to VM flow.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x40)
- /*
- * when set to 1, indicates RX flow offload for function specified in dst_fid and
- * the src_fid should be set to invalid value.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x80)
- /*
- * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
- * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
- * This flag is only valid when the flow direction is RX.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
- UINT32_C(0x100)
- /*
- * Tx Flow: vf fid.
- * Rx Flow: pf fid.
- */
- uint16_t src_fid;
- /* Tunnel handle valid when tunnel flag is set. */
- uint32_t tunnel_handle;
- uint16_t action_flags;
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
- UINT32_C(0x1)
- /* recycle is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
- UINT32_C(0x4)
- /* meter is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
- UINT32_C(0x8)
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
- UINT32_C(0x10)
- /* nat_src is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
- UINT32_C(0x20)
- /* nat_dest is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
- UINT32_C(0x40)
- /* nat_ipv4_address is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
- UINT32_C(0x80)
- /* l2_header_rewrite is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
- UINT32_C(0x100)
- /* ttl_decrement is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
- UINT32_C(0x200)
- /*
- * If set to 1 and flow direction is TX, it indicates decap of L2 header
- * and encap of tunnel header. If set to 1 and flow direction is RX, it
- * indicates decap of tunnel header and encap L2 header. The type of tunnel
- * is specified in the tunnel_type field.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
- UINT32_C(0x400)
- /*
- * Tx Flow: pf or vf fid.
- * Rx Flow: vf fid.
- */
- uint16_t dst_fid;
- /* VLAN tpid, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tpid;
- /* VLAN tci, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tci;
- /* Meter id, valid when meter flag is set. */
- uint16_t act_meter_id;
- /* Flow with the same l2 context tcam key. */
- uint16_t ref_flow_handle;
- /* This value sets the match value for the ethertype. */
- uint16_t ethertype;
- /* valid when num tags is 1 or 2. */
- uint16_t outer_vlan_tci;
- /* This value sets the match value for the Destination MAC address. */
- uint16_t dmac[3];
- /* valid when num tags is 2. */
- uint16_t inner_vlan_tci;
- /* This value sets the match value for the Source MAC address. */
- uint16_t smac[3];
- /* The bit length of destination IP address mask. */
- uint8_t ip_dst_mask_len;
- /* The bit length of source IP address mask. */
- uint8_t ip_src_mask_len;
- /* The value of destination IPv4/IPv6 address. */
- uint32_t ip_dst[4];
- /* The source IPv4/IPv6 address. */
- uint32_t ip_src[4];
- /*
- * The value of source port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port;
- /*
- * The value of source port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port_mask;
- /*
- * The value of destination port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port;
- /*
- * The value of destination port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port_mask;
- /*
- * NAT IPv4/6 address based on address type flag.
- * 0 values are ignored.
- */
- uint32_t nat_ip_address[4];
- /* L2 header re-write Destination MAC address. */
- uint16_t l2_rewrite_dmac[3];
- /*
- * The NAT source/destination port based on direction flag.
- * Applies to UDP and TCP traffic.
- * 0 values are ignored.
- */
- uint16_t nat_port;
- /* L2 header re-write Source MAC address. */
- uint16_t l2_rewrite_smac[3];
- /* The value of ip protocol. */
- uint8_t ip_proto;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
-struct hwrm_cfa_flow_alloc_output {
+/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_timer_reset_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24210,20 +25998,7 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[2];
- /*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
- */
- uint32_t flow_id;
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24234,13 +26009,13 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_flow_free *
- **********************/
+/***************************
+ * hwrm_cfa_flow_aging_cfg *
+ ***************************/
-/* hwrm_cfa_flow_free_input (size:256b/32B) */
-struct hwrm_cfa_flow_free_input {
+/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24268,15 +26043,38 @@ struct hwrm_cfa_flow_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[6];
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
+ /* The bit field to enable per flow aging configuration. */
+ uint16_t enables;
+ /* This bit must be '1' for the tcp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
+ UINT32_C(0x1)
+ /* This bit must be '1' for the tcp finish timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
+ UINT32_C(0x2)
+ /* This bit must be '1' for the udp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
+ UINT32_C(0x4)
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_flow_timer;
+ /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_fin_timer;
+ /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
+ uint32_t udp_flow_timer;
} __attribute__((packed));
-/* hwrm_cfa_flow_free_output (size:256b/32B) */
-struct hwrm_cfa_flow_free_output {
+/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24285,10 +26083,6 @@ struct hwrm_cfa_flow_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet is 64 b */
- uint64_t packet;
- /* byte is 64 b */
- uint64_t byte;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24300,13 +26094,13 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_flush *
- ***********************/
+/****************************
+ * hwrm_cfa_flow_aging_qcfg *
+ ****************************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
-struct hwrm_cfa_flow_flush_input {
+/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24334,12 +26128,21 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- uint8_t unused_0[4];
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_flush_output (size:128b/16B) */
-struct hwrm_cfa_flow_flush_output {
+/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24348,7 +26151,13 @@ struct hwrm_cfa_flow_flush_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_flow_timer;
+ /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_fin_timer;
+ /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t udp_flow_timer;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24359,13 +26168,13 @@ struct hwrm_cfa_flow_flush_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_stats *
- ***********************/
+/*****************************
+ * hwrm_cfa_flow_aging_qcaps *
+ *****************************/
-/* hwrm_cfa_flow_stats_input (size:640b/80B) */
-struct hwrm_cfa_flow_stats_input {
+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24393,53 +26202,21 @@ struct hwrm_cfa_flow_stats_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow handle. */
- uint16_t num_flows;
- /* Flow handle. */
- uint16_t flow_handle_0;
- /* Flow handle. */
- uint16_t flow_handle_1;
- /* Flow handle. */
- uint16_t flow_handle_2;
- /* Flow handle. */
- uint16_t flow_handle_3;
- /* Flow handle. */
- uint16_t flow_handle_4;
- /* Flow handle. */
- uint16_t flow_handle_5;
- /* Flow handle. */
- uint16_t flow_handle_6;
- /* Flow handle. */
- uint16_t flow_handle_7;
- /* Flow handle. */
- uint16_t flow_handle_8;
- /* Flow handle. */
- uint16_t flow_handle_9;
- uint8_t unused_0[2];
- /* Flow ID of a flow. */
- uint32_t flow_id_0;
- /* Flow ID of a flow. */
- uint32_t flow_id_1;
- /* Flow ID of a flow. */
- uint32_t flow_id_2;
- /* Flow ID of a flow. */
- uint32_t flow_id_3;
- /* Flow ID of a flow. */
- uint32_t flow_id_4;
- /* Flow ID of a flow. */
- uint32_t flow_id_5;
- /* Flow ID of a flow. */
- uint32_t flow_id_6;
- /* Flow ID of a flow. */
- uint32_t flow_id_7;
- /* Flow ID of a flow. */
- uint32_t flow_id_8;
- /* Flow ID of a flow. */
- uint32_t flow_id_9;
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
-struct hwrm_cfa_flow_stats_output {
+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_flow_aging_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24448,46 +26225,14 @@ struct hwrm_cfa_flow_stats_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet_0 is 64 b */
- uint64_t packet_0;
- /* packet_1 is 64 b */
- uint64_t packet_1;
- /* packet_2 is 64 b */
- uint64_t packet_2;
- /* packet_3 is 64 b */
- uint64_t packet_3;
- /* packet_4 is 64 b */
- uint64_t packet_4;
- /* packet_5 is 64 b */
- uint64_t packet_5;
- /* packet_6 is 64 b */
- uint64_t packet_6;
- /* packet_7 is 64 b */
- uint64_t packet_7;
- /* packet_8 is 64 b */
- uint64_t packet_8;
- /* packet_9 is 64 b */
- uint64_t packet_9;
- /* byte_0 is 64 b */
- uint64_t byte_0;
- /* byte_1 is 64 b */
- uint64_t byte_1;
- /* byte_2 is 64 b */
- uint64_t byte_2;
- /* byte_3 is 64 b */
- uint64_t byte_3;
- /* byte_4 is 64 b */
- uint64_t byte_4;
- /* byte_5 is 64 b */
- uint64_t byte_5;
- /* byte_6 is 64 b */
- uint64_t byte_6;
- /* byte_7 is 64 b */
- uint64_t byte_7;
- /* byte_8 is 64 b */
- uint64_t byte_8;
- /* byte_9 is 64 b */
- uint64_t byte_9;
+ /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_flow_timer;
+ /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_fin_timer;
+ /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t max_udp_flow_timer;
+ /* The maximum aging flows that HW can support. */
+ uint32_t max_aging_flows;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24706,6 +26451,12 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24765,8 +26516,14 @@ struct hwrm_tunnel_dst_port_query_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0[7];
} __attribute__((packed));
@@ -24857,8 +26614,14 @@ struct hwrm_tunnel_dst_port_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* This field represents the value of L4 destination port used
@@ -24948,8 +26711,14 @@ struct hwrm_tunnel_dst_port_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -25025,6 +26794,52 @@ struct ctx_hw_stats {
uint64_t tpa_aborts;
} __attribute__((packed));
+/* Periodic Engine statistics context DMA to host. */
+/* ctx_eng_stats (size:512b/64B) */
+struct ctx_eng_stats {
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+} __attribute__((packed));
+
/***********************
* hwrm_stat_ctx_alloc *
***********************/
@@ -25081,7 +26896,7 @@ struct hwrm_stat_ctx_alloc_input {
* than offloaded RoCE traffic shall not be included in this
* statistic context.
* When this bit is set to '0', the statistics context shall be
- * used for the network traffic other than offloaded RoCE traffic.
+ * used for network traffic or engine traffic.
*/
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
uint8_t unused_0[3];
@@ -25272,6 +27087,107 @@ struct hwrm_stat_ctx_query_output {
uint8_t valid;
} __attribute__((packed));
+/***************************
+ * hwrm_stat_ctx_eng_query *
+ ***************************/
+
+
+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_eng_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
+struct hwrm_stat_ctx_eng_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***************************
* hwrm_stat_ctx_clr_stats *
***************************/
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v4 7/8] net/bnxt: update HWRM API to version 1.10.0.48
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
` (5 preceding siblings ...)
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM version to 1.10.0.48
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3156 +++++++++++++++++++++---
1 file changed, 2874 insertions(+), 282 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index ea9a7d40e..00a8ff87e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -260,6 +260,7 @@ struct cmd_nums {
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
+ #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
@@ -372,6 +373,8 @@ struct cmd_nums {
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
+ #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
+ #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
@@ -397,6 +400,8 @@ struct cmd_nums {
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
/* Experimental */
+ #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
+ /* Experimental */
#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
@@ -407,6 +412,8 @@ struct cmd_nums {
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
/* Experimental */
+ #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
+ /* Experimental */
#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
/* Experimental */
#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
@@ -451,6 +458,34 @@ struct cmd_nums {
#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
+ /* Experimental */
+ #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
+ /* Experimental */
+ #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
+ /* Experimental */
+ #define HWRM_CFA_EEM_OP UINT32_C(0x123)
+ /* Experimental */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -469,6 +504,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
/* Engine CKV - Generate and encrypt a new AES key. */
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
+ /* Engine CKV - Configure a label index with a label value. */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -523,6 +560,8 @@ struct cmd_nums {
#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
/* Engine - Set the on-die RQE credit update location. */
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
+ /* Engine - Query the engine function configuration. */
+ #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
/* Experimental */
#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
/* Experimental */
@@ -573,6 +612,10 @@ struct cmd_nums {
/* */
#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
/* Experimental */
+ #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
+ /* Experimental */
+ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
+ /* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
#define HWRM_NVM_FLUSH UINT32_C(0xfff0)
@@ -724,8 +767,8 @@ struct hwrm_err_output {
#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
/* hwrm_func_buf_rgtr */
#define HWRM_MAX_REQ_LEN 128
-/* hwrm_selftest_qlist */
-#define HWRM_MAX_RESP_LEN 280
+/* hwrm_cfa_flow_info */
+#define HWRM_MAX_RESP_LEN 704
/* 7 bit indirection table index. */
#define HW_HASH_INDEX_SIZE 0x80
#define HW_HASH_KEY_SIZE 40
@@ -735,8 +778,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 19
-#define HWRM_VERSION_STR "1.10.0.19"
+#define HWRM_VERSION_RSVD 48
+#define HWRM_VERSION_STR "1.10.0.48"
/****************
* hwrm_ver_get *
@@ -993,6 +1036,32 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
UINT32_C(0x200)
+ /*
+ * If set to 1, firmware is capable to support advanced flow counters like,
+ * Meter drop counters and EEM counters.
+ * If set to 0, firmware is not capable to support advanced flow counters.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * If set to 1, the firmware is able to support the use of the CFA
+ * Extended Exact Match(EEM) feature.
+ * If set to 0, firmware is not capable to support the use of the
+ * CFA EEM feature.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
+ UINT32_C(0x800)
+ /*
+ * If set to 1, the firmware is able to support advance CFA flow management
+ * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
+ * If set to 0, then the firmware doesn’t support the advance CFA flow management
+ * features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
+ UINT32_C(0x1000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -3695,6 +3764,9 @@ struct hwrm_async_event_cmpl {
/* Reset notification to clients */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
UINT32_C(0x8)
+ /* Master function selection event */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
/* Function driver unloaded */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
UINT32_C(0x10)
@@ -3739,6 +3811,40 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
UINT32_C(0x37)
+ /*
+ * A EEM flow cached memory flush request event being posted to the PF
+ * driver.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ /*
+ * A EEM flow cache memory flush completion event being posted to the
+ * firmware by the PF driver. This is indication that host EEM flush
+ * has completed by the PF.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ /*
+ * A tcp flag action change event being posted to the PF or trusted VF
+ * driver by the firmware. The PF or trusted VF driver should query
+ * the firmware for the new TCP flag action update after receiving
+ * this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ /*
+ * A eem flow active event being posted to the PF or trusted VF driver
+ * by the firmware. The PF or trusted VF driver should update the
+ * flow's aging timer after receiving this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ /*
+ * A eem cfg change event being posted to the trusted VF driver by the
+ * firmware if the parent PF EEM configuration changed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -4450,6 +4556,75 @@ struct hwrm_async_event_cmpl_reset_notify {
16
} __attribute__((packed));
+/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_recovery {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message can be used for selecting or
+ * deselecting master function for error recovery,
+ * and to communicate to all the functions whether error recovery
+ * was enabled/disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates driver action requested */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
+ 0
+ /*
+ * If set to 1, this function is selected as Master function.
+ * This function has responsibility to do 'chip reset' when it
+ * detects a fatal error. If set to 0, master function functionality
+ * is disabled on this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, error recovery is enabled.
+ * If set to 0, error recovery is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
struct hwrm_async_event_cmpl_func_drvr_unload {
uint16_t type;
@@ -5182,8 +5357,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {
HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
} __attribute__((packed));
-/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
-struct hwrm_async_event_cmpl_hwrm_error {
+/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_req {
uint16_t type;
/*
* This field indicates the exact type of the completion.
@@ -5192,133 +5367,549 @@ struct hwrm_async_event_cmpl_hwrm_error {
* records. Odd values indicate 32B
* records.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
UINT32_C(0x3f)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
+ 0
/* HWRM Asynchronous Event Information */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
UINT32_C(0x2e)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
/* Identifiers of events. */
uint16_t event_id;
- /* HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Notification of a eem_cache_flush request */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
/* Event specific data */
uint32_t event_data2;
- /* Severity of HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
- /* Warning */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
- UINT32_C(0x0)
- /* Non-fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
- UINT32_C(0x1)
- /* Fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
- UINT32_C(0x2)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
+ UINT32_C(0x1)
/* opaque is 7 b */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
/* 8-lsb timestamp from POR (100-msec resolution) */
uint8_t timestamp_lo;
/* 16-lsb timestamp from POR (100-msec resolution) */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
- /* Time stamp for error event */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
- UINT32_C(0x1)
} __attribute__((packed));
-/*******************
- * hwrm_func_reset *
- *******************/
-
-
-/* hwrm_func_reset_input (size:192b/24B) */
-struct hwrm_func_reset_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_done {
+ uint16_t type;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t cmpl_ring;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Notification of a host eem_cache_flush has completed. This event
+ * is generated by the host driver.
*/
- uint16_t seq_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- uint16_t target_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates function ID that this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
+ 0
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_tcp_flag_action_change {
+ uint16_t type;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint64_t resp_addr;
- uint32_t enables;
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of tcp flag action change */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * This bit must be '1' for the vf_id_valid field to be
- * configured.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_flow_active {
+ uint16_t type;
/*
- * The ID of the VF that this PF is trying to reset.
- * Only the parent PF shall be allowed to reset a child VF.
- *
- * A parent PF driver shall use this field only when a specific child VF
- * is requested to be reset.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t vf_id;
- /* This value indicates the level of a function reset. */
- uint8_t func_reset_level;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of an active eem flow */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Indicates the 2nd global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
+ 0
/*
- * Reset the caller function and its children VFs (if any). If no
- * children functions exist, then reset the caller function only.
- */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
- UINT32_C(0x0)
- /* Reset the caller function only */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
- UINT32_C(0x1)
+ * Indicates flow direction of the flow identified by
+ * the global_id_2.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
+ uint8_t opaque_v;
/*
- * Reset all children VFs of the caller function driver if the
- * caller is a PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver with
- * no children VFs.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
- UINT32_C(0x2)
- /*
- * Reset a specific VF of the caller function driver if the caller
- * is the parent PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver that is not
- * the parent of the VF that is being requested to reset.
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the 1st global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
+ 0
+ /*
+ * Indicates flow direction of the flow identified by the
+ * global_id_1.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this is rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this is tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
+ /*
+ * Indicates EEM flow aging mode this event occured on. If
+ * this bit is set to 0, the event_data1 is the EEM global
+ * ID. If this bit is set to 1, the event_data1 is the number
+ * of global ID in the context memory.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
+ UINT32_C(0x80000000)
+ /* EEM flow aging mode 0. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
+ (UINT32_C(0x0) << 31)
+ /* EEM flow aging mode 1. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cfg_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of EEM configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Value of 1 to indicate EEM TX configuration is enabled. Value of
+ * 0 to indicate the EEM TX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
+ * to indicate the EEM RX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
+struct hwrm_async_event_cmpl_fw_trace_msg {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Firmware trace log message */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
+ /* Trace byte 0 to 3 */
+ uint32_t event_data2;
+ /* Trace byte0 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
+ /* Trace byte1 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
+ /* Trace byte2 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
+ /* Trace byte3 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
+ /* Trace flags */
+ uint8_t timestamp_lo;
+ /* Indicates if the string is partial or complete. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
+ UINT32_C(0x1)
+ /* Complete string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
+ UINT32_C(0x0)
+ /* Partial string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
+ UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
+ /* Indicates the firmware that sent the trace message. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
+ UINT32_C(0x2)
+ /* Primary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
+ (UINT32_C(0x0) << 1)
+ /* Secondary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
+ /* Trace byte 4 to 5 */
+ uint16_t timestamp_hi;
+ /* Trace byte4 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
+ /* Trace byte5 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
+ /* Trace byte 6 to 9 */
+ uint32_t event_data1;
+ /* Trace byte6 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
+ /* Trace byte7 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
+ /* Trace byte8 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
+ /* Trace byte9 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
+struct hwrm_async_event_cmpl_hwrm_error {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Severity of HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
+ /* Warning */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
+ UINT32_C(0x0)
+ /* Non-fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
+ UINT32_C(0x1)
+ /* Fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Time stamp for error event */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
+ UINT32_C(0x1)
+} __attribute__((packed));
+
+/*******************
+ * hwrm_func_reset *
+ *******************/
+
+
+/* hwrm_func_reset_input (size:192b/24B) */
+struct hwrm_func_reset_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vf_id_valid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ /*
+ * The ID of the VF that this PF is trying to reset.
+ * Only the parent PF shall be allowed to reset a child VF.
+ *
+ * A parent PF driver shall use this field only when a specific child VF
+ * is requested to be reset.
+ */
+ uint16_t vf_id;
+ /* This value indicates the level of a function reset. */
+ uint8_t func_reset_level;
+ /*
+ * Reset the caller function and its children VFs (if any). If no
+ * children functions exist, then reset the caller function only.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
+ UINT32_C(0x0)
+ /* Reset the caller function only */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
+ UINT32_C(0x1)
+ /*
+ * Reset all children VFs of the caller function driver if the
+ * caller is a PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver with
+ * no children VFs.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
+ UINT32_C(0x2)
+ /*
+ * Reset a specific VF of the caller function driver if the caller
+ * is the parent PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver that is not
+ * the parent of the VF that is being requested to reset.
*/
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
UINT32_C(0x3)
@@ -6066,6 +6657,12 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
UINT32_C(0x400000)
+ /*
+ * This flag will be set to 1 by the FW if FW supports adapter error
+ * recovery.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
+ UINT32_C(0x800000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6813,8 +7410,7 @@ struct hwrm_func_cfg_input {
* resident HWRM clients, only the parent PF driver shall be allowed
* to initiate this change on one of its children VFs. If this bit is
* set to 1, then the VF that is being configured is requested to be
- * trusted. If this bit is set to 0, then the VF that is being configured
- * is requested to be not trusted.
+ * trusted.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
@@ -6825,6 +7421,25 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
UINT32_C(0x400000)
+ /*
+ * This bit requests that the firmware test to see if all the assets
+ * requested in this command (i.e. number of NQ rings) are available.
+ * The firmware will return an error if the requested assets are
+ * not available. The firwmare will NOT reserve the assets if they
+ * are available.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
+ UINT32_C(0x800000)
+ /*
+ * This configuration change can be initiated by a PF driver. This
+ * configuration request shall be targeted to a VF. From local host
+ * resident HWRM clients, only the parent PF driver shall be allowed
+ * to initiate this change on one of its children VFs. If this bit is
+ * set to 1, then the VF that is being configured is requested to be
+ * untrusted.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
+ UINT32_C(0x1000000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7593,6 +8208,19 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
UINT32_C(0x10)
+ /*
+ * When this bit is 1, the function is indicating the support of the
+ * error recovery capability. Error recovery support will be used by
+ * firmware only if all the driver instances support error recovery
+ * process. By setting this bit, driver is indicating support for
+ * corresponding async event completion message. These will be
+ * delivered to the driver even if they did not register for it.
+ * If supported, after receiving reset notify async event with fatal
+ * flag set in event data1, then all the drivers have to tear down
+ * their resources without sending any HWRM commands to FW.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
+ UINT32_C(0x20)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10270,17 +10898,384 @@ struct hwrm_func_backing_store_qcfg_output {
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as 1
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
*/
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/****************************
+ * hwrm_error_recovery_qcfg *
+ ****************************/
+
+
+/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
+struct hwrm_error_recovery_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __attribute__((packed));
+
+/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
+struct hwrm_error_recovery_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When this flag is set to 1, error recovery will be initiated
+ * through master function driver.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
+ /*
+ * When this flag is set to 1, error recovery will be performed
+ * through Co processor.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
+ /*
+ * Driver Polling frequency. This value is in units of 100msec.
+ * Typical value would be 10 to indicate 1sec.
+ * Drivers can poll FW health status, Heartbeat, reset_counter with
+ * this frequency.
+ */
+ uint32_t driver_polling_freq;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 30 to indicate 3sec.
+ * Master function wait period from detecting a fatal error to
+ * initiating reset. In this time period Master PF expects every
+ * active driver will detect fatal error.
+ */
+ uint32_t master_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 50 to indicate 5sec.
+ * Normal function wait period from fatal error detection to
+ * polling FW health status. In this time period, drivers should not
+ * do any PCIe MMIO transaction and should not send any HWRM commands.
+ */
+ uint32_t normal_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 20 to indicate 2sec.
+ * This field indicates that, master function wait period after chip
+ * reset. After this time, master function should reinitialize with
+ * FW.
+ */
+ uint32_t master_func_wait_period_after_reset;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 60 to indicate 6sec.
+ * This field is applicable to both master and normal functions.
+ * Even after chip reset, if FW status not changed to ready,
+ * then all the functions can poll for this much time and bailout.
+ */
+ uint32_t max_bailout_time_after_reset;
+ /*
+ * FW health status register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates upper 30bits of the register address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_health_status_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
+ 2
+ /*
+ * FW HeartBeat register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_heartbeat_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
+ 2
+ /*
+ * FW reset counter.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_reset_cnt_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
+ 2
+ /*
+ * Reset Inprogress Register address for PFs.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_inprogress_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
+ 2
+ /* This field indicates the mask value for reset_inprogress_reg. */
+ uint32_t reset_inprogress_reg_mask;
+ uint8_t unused_0[3];
+ /*
+ * Array of registers and value count to reset the Chip
+ * Each array count has reset_reg, reset_reg_val, delay_after_reset
+ * in TLV format. Depending upon Chip type, number of reset registers
+ * will vary. Drivers have to write reset_reg_val in the reset_reg
+ * location in the same sequence in order to recover from a fatal
+ * error.
+ */
+ uint8_t reg_array_cnt;
+ /*
+ * Reset register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_reg[16];
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
+ /* Value to be written in reset_reg to reset the controller. */
+ uint32_t reset_reg_val[16];
+ /*
+ * This value is in units of 1msec.
+ * Typical value would be 10 to indicate 10msec.
+ * Some of the operations like Core reset require delay before
+ * accessing PCIE MMIO register space.
+ * If this value is non-zero, drivers have to wait for
+ * this much time after writing reset_reg_val in reset_reg.
+ */
+ uint8_t delay_after_reset[16];
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
@@ -10894,6 +11889,12 @@ struct hwrm_func_drv_if_change_output {
*/
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that the firmware got changed / reset.
+ * The driver should do complete re-initialization when that bit is set.
+ */
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
+ UINT32_C(0x2)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -14166,6 +15167,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for autonegotiation on this link.
@@ -14215,6 +15219,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for EEE on this link.
@@ -14281,13 +15288,13 @@ struct hwrm_port_phy_qcaps_output {
#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
} __attribute__((packed));
-/*********************
- * hwrm_port_led_cfg *
- *********************/
+/****************************
+ * hwrm_port_phy_mdio_write *
+ ****************************/
-/* hwrm_port_led_cfg_input (size:512b/64B) */
-struct hwrm_port_led_cfg_input {
+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
+struct hwrm_port_phy_mdio_write_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -14315,46 +15322,198 @@ struct hwrm_port_led_cfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ /*
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
+ */
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1[7];
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_write_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This bit must be '1' for the led0_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
- UINT32_C(0x1)
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_port_phy_mdio_read *
+ ***************************/
+
+
+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
+struct hwrm_port_phy_mdio_read_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This bit must be '1' for the led0_state field to be
- * configured.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
- UINT32_C(0x2)
+ uint16_t cmpl_ring;
/*
- * This bit must be '1' for the led0_color field to be
- * configured.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
- UINT32_C(0x4)
+ uint16_t seq_id;
/*
- * This bit must be '1' for the led0_blink_on field to be
- * configured.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
- UINT32_C(0x8)
+ uint16_t target_id;
/*
- * This bit must be '1' for the led0_blink_off field to be
- * configured.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
- UINT32_C(0x10)
+ uint64_t resp_addr;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
/*
- * This bit must be '1' for the led0_group_id field to be
- * configured.
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
- UINT32_C(0x20)
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1;
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_read_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ uint8_t unused_0[5];
/*
- * This bit must be '1' for the led1_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_led_cfg *
+ *********************/
+
+
+/* hwrm_port_led_cfg_input (size:512b/64B) */
+struct hwrm_port_led_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the led0_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the led0_state field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the led0_color field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the led0_blink_on field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the led0_blink_off field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the led0_group_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the led1_id field to be
+ * configured.
*/
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
UINT32_C(0x40)
@@ -20644,7 +21803,9 @@ struct hwrm_ring_reset_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t unused_0[4];
+ /* Position of consumer index after ring reset completes. */
+ uint8_t consumer_idx[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -21209,6 +22370,26 @@ struct hwrm_ring_grp_free_output {
*/
uint8_t valid;
} __attribute__((packed));
+/*
+ * special reserved flow ID to identify per function default
+ * flows for vSwitch offload
+ */
+#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
+/*
+ * special reserved flow ID to identify per function RoCEv1
+ * flows
+ */
+#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * flows
+ */
+#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * CNP flows
+ */
+#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
/****************************
* hwrm_cfa_l2_filter_alloc *
@@ -22968,6 +24149,13 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Setting of this flag indicates the applicability to the loopback path. */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
+ /*
+ * Setting of this flag indicates this encap record is external encap record.
+ * Resetting of this flag indicates this flag is internal encap record and
+ * this is the default setting.
+ */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
+ UINT32_C(0x2)
/* Encapsulation Type. */
uint8_t encap_type;
/* Virtual eXtensible Local Area Network (VXLAN) */
@@ -23003,8 +24191,11 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -23144,6 +24335,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
UINT32_C(0x4)
+ /*
+ * Setting of this flag indicates that the dest_id field contains function ID.
+ * If this is not set it indicates dest_id is VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x8)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
@@ -23605,7 +24802,13 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
UINT32_C(0x4)
- uint8_t unused_0[4];
+ uint32_t flags;
+ /*
+ * Setting this bit to 1 indicates that dest_id field contains FID.
+ * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x1)
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
@@ -24090,6 +25293,118 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/************************
+ * hwrm_cfa_meter_qcaps *
+ ************************/
+
+
+/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_meter_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
+struct hwrm_cfa_meter_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the clock at which the Meter is running with.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
+ /* 375 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
+ /* 625 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
+ HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
+ uint8_t unused_0[4];
+ /*
+ * The minimum guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_tx_profile;
+ /*
+ * The maximum non-guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_tx_profile;
+ /*
+ * The minimum guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_rx_profile;
+ /*
+ * The maximum non-guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_rx_profile;
+ /*
+ * The minimum guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t min_tx_instance;
+ /*
+ * The maximum non-guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t max_tx_instance;
+ /*
+ * The minimum guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t min_rx_instance;
+ /*
+ * The maximum non-guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t max_rx_instance;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/********************************
* hwrm_cfa_meter_profile_alloc *
********************************/
@@ -24200,11 +25515,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24243,7 +25558,7 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24286,11 +25601,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24564,11 +25879,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24607,7 +25922,7 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24650,11 +25965,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24775,7 +26090,7 @@ struct hwrm_cfa_meter_instance_alloc_input {
/* This value identifies a meter profile in CFA. */
uint16_t meter_profile_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* profile is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
@@ -24798,7 +26113,7 @@ struct hwrm_cfa_meter_instance_alloc_output {
/* This value identifies a meter instance in CFA. */
uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* instance is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
@@ -24816,13 +26131,13 @@ struct hwrm_cfa_meter_instance_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_meter_instance_free *
- ********************************/
+/*******************************
+ * hwrm_cfa_meter_instance_cfg *
+ *******************************/
-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
-struct hwrm_cfa_meter_instance_free_input {
+/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24856,31 +26171,39 @@ struct hwrm_cfa_meter_instance_free_input {
* This enumeration is used for resources that are similar for both
* TX and RX paths of the chip.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
uint8_t unused_0;
- /* This value identifies a meter instance in CFA. */
- uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
+ * This value identifies a new meter profile to be associated with
+ * the meter instance specified in this command.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xffff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[4];
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This value identifies the ID of a meter instance that needs to be updated with
+ * a new meter profile specified in this command.
+ */
+ uint16_t meter_instance_id;
+ uint8_t unused_1[2];
} __attribute__((packed));
-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
-struct hwrm_cfa_meter_instance_free_output {
+/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24900,13 +26223,13 @@ struct hwrm_cfa_meter_instance_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24934,22 +26257,106 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
/*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
UINT32_C(0x2)
/*
* This bit must be '1' for the src_macaddr field to be
@@ -25375,6 +26782,9 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
+ /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
+ UINT32_C(0x200)
/*
* Tx Flow: vf fid.
* Rx Flow: pf fid.
@@ -25430,6 +26840,13 @@ struct hwrm_cfa_flow_alloc_input {
/* If set to 1, flow aging is enabled for this flow. */
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
UINT32_C(0x800)
+ /*
+ * If set to 1 an attempt will be made to try to offload this flow to the
+ * most optimal flow table resource. If set to 0, the flow will be
+ * placed to the default flow table resource.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
+ UINT32_C(0x1000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -25569,7 +26986,8 @@ struct hwrm_cfa_flow_alloc_output {
uint32_t flow_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint32_t flow_counter_id;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25646,6 +27064,229 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_action_data (size:960b/120B) */
+struct hwrm_cfa_flow_action_data {
+ uint16_t action_flags;
+ /* Setting of this flag indicates accept action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* Setting of this flag indicates recycle action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /* Setting of this flag indicates drop action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* Setting of this flag indicates meter action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* Setting of this flag indicates tunnel action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /*
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header.
+ */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
+ UINT32_C(0x20)
+ /* Setting of this flag indicates ttl decrement action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
+ UINT32_C(0x40)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x80)
+ /* Setting of this flag indicates encap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
+ UINT32_C(0x100)
+ /* Setting of this flag indicates decap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
+ UINT32_C(0x200)
+ /* Meter id. */
+ uint16_t act_meter_id;
+ /* VNIC id. */
+ uint16_t vnic_id;
+ /* vport number. */
+ uint16_t vport_id;
+ /* The NAT source/destination. */
+ uint16_t nat_port;
+ uint16_t unused_0[3];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ /* Encapsulation Type. */
+ uint8_t encap_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
+ /* VLAN */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
+ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
+ uint8_t unused[7];
+ /* This value is encap data for the associated encap type. */
+ uint32_t encap_data[20];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
+struct hwrm_cfa_flow_tunnel_hdr_data {
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused[3];
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI).
+ */
+ uint32_t tunnel_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
+struct hwrm_cfa_flow_l4_key_data {
+ /* The value of source port. */
+ uint16_t l4_src_port;
+ /* The value of destination port. */
+ uint16_t l4_dst_port;
+ uint32_t unused;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
+struct hwrm_cfa_flow_l3_key_data {
+ /* The value of ip protocol. */
+ uint8_t ip_protocol;
+ uint8_t unused_0[7];
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ uint32_t unused[2];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
+struct hwrm_cfa_flow_l2_key_data {
+ /* Destination MAC address. */
+ uint16_t dmac[3];
+ uint16_t unused_0;
+ /* Source MAC address. */
+ uint16_t smac[3];
+ uint16_t unused_1;
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
+ uint16_t unused_2;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* Ethertype. */
+ uint16_t ethertype;
+ /* Number of VLAN tags. */
+ uint16_t num_vlan_tags;
+ /* VLAN tpid. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci. */
+ uint16_t l2_rewrite_vlan_tci;
+ uint8_t unused_3[2];
+ /* Outer VLAN TPID. */
+ uint16_t ovlan_tpid;
+ /* Outer VLAN TCI. */
+ uint16_t ovlan_tci;
+ /* Inner VLAN TPID. */
+ uint16_t ivlan_tpid;
+ /* Inner VLAN TCI. */
+ uint16_t ivlan_tci;
+ uint8_t unused[8];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_key_data (size:4160b/520B) */
+struct hwrm_cfa_flow_key_data {
+ /* Flow associated tunnel L2 header key info. */
+ uint32_t t_l2_key_data[14];
+ /* Flow associated tunnel L2 header mask info. */
+ uint32_t t_l2_key_mask[14];
+ /* Flow associated tunnel L3 header key info. */
+ uint32_t t_l3_key_data[16];
+ /* Flow associated tunnel L3 header mask info. */
+ uint32_t t_l3_key_mask[16];
+ /* Flow associated tunnel L4 header key info. */
+ uint32_t t_l4_key_data[2];
+ /* Flow associated tunnel L4 header mask info. */
+ uint32_t t_l4_key_mask[2];
+ /* Flow associated tunnel header info. */
+ uint32_t tunnel_hdr[2];
+ /* Flow associated L2 header key info. */
+ uint32_t l2_key_data[14];
+ /* Flow associated L2 header mask info. */
+ uint32_t l2_key_mask[14];
+ /* Flow associated L3 header key info. */
+ uint32_t l3_key_data[16];
+ /* Flow associated L3 header mask info. */
+ uint32_t l3_key_mask[16];
+ /* Flow associated L4 header key info. */
+ uint32_t l4_key_data[2];
+ /* Flow associated L4 header mask info. */
+ uint32_t l4_key_mask[2];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_info *
**********************/
@@ -25703,7 +27344,7 @@ struct hwrm_cfa_flow_info_input {
uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_info_output (size:448b/56B) */
+/* hwrm_cfa_flow_info_output (size:5632b/704B) */
struct hwrm_cfa_flow_info_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -25713,8 +27354,11 @@ struct hwrm_cfa_flow_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* flags is 8 b */
uint8_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
/* profile is 8 b */
uint8_t profile;
/* src_fid is 16 b */
@@ -25737,7 +27381,12 @@ struct hwrm_cfa_flow_info_output {
uint32_t tunnel_handle;
/* The flow aging timer for the flow, the unit is 100 milliseconds */
uint16_t flow_timer;
- uint8_t unused_0[5];
+ uint8_t unused_0[6];
+ /* Flow associated L2, L3 and L4 headers info. */
+ uint32_t flow_key_data[130];
+ /* Flow associated action record info. */
+ uint32_t flow_action_info[30];
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25753,7 +27402,7 @@ struct hwrm_cfa_flow_info_output {
***********************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+/* hwrm_cfa_flow_flush_input (size:256b/32B) */
struct hwrm_cfa_flow_flush_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -25782,8 +27431,73 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* flags is 32 b */
uint32_t flags;
- uint8_t unused_0[4];
+ /*
+ * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
+ * fields are valid. The flow flush operation should only flush the flows from the
+ * flow table specified. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
+ UINT32_C(0x1)
+ /*
+ * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
+ * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
+ UINT32_C(0x2)
+ /*
+ * This specifies the size of flow handle entries provided by the driver
+ * in the flow table specified below. Only two flow handle size enums are defined.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
+ UINT32_C(0xc0000000)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
+ 30
+ /* The flow handle is 16bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
+ (UINT32_C(0x0) << 30)
+ /* The flow handle is 64bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
+ /* Specify page size of the flow table memory. */
+ uint8_t page_size;
+ /* The page size is 4K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* The page size is 8K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* The page size is 64K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* The page size is 256K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* The page size is 1M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* The page size is 2M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* The page size is 4M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* The page size is 1G */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
+ /* FLow table memory indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
+ /* number of flows in the flow table */
+ uint16_t num_flows;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
} __attribute__((packed));
/* hwrm_cfa_flow_flush_output (size:128b/16B) */
@@ -25983,7 +27697,12 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint8_t unused_0[2];
+ /*
+ * New flow timer value for the flow specified in the ext_flow_handle.
+ * The flow timer unit is 100ms.
+ */
+ uint32_t flow_timer;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -26244,13 +27963,13 @@ struct hwrm_cfa_flow_aging_qcaps_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_pair_info *
- **********************/
+/**********************************
+ * hwrm_cfa_tcp_flag_process_qcfg *
+ **********************************/
-/* hwrm_cfa_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_pair_info_input {
+/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26278,23 +27997,10 @@ struct hwrm_cfa_pair_info_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* If this flag is set, lookup by name else lookup by index. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
- /* If this flag is set, lookup by PF id and VF id. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
- /* Pair table index. */
- uint16_t pair_index;
- /* Pair pf index. */
- uint8_t pair_pfid;
- /* Pair vf index. */
- uint8_t pair_vfid;
- /* Pair name (32 byte string). */
- char pair_name[32];
} __attribute__((packed));
-/* hwrm_cfa_pair_info_output (size:576b/72B) */
-struct hwrm_cfa_pair_info_output {
+/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26303,22 +28009,100 @@ struct hwrm_cfa_pair_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Pair table index. */
- uint16_t next_pair_index;
- /* Pair member a's fid. */
- uint16_t a_fid;
- /* Logical host number. */
- uint8_t host_a_index;
- /* Logical PF number. */
- uint8_t pf_a_index;
- /* Pair member a's Linux logical VF number. */
- uint16_t vf_a_index;
- /* Rx CFA code. */
- uint16_t rx_cfa_code_a;
- /* Tx CFA action. */
- uint16_t tx_cfa_action_a;
- /* Pair member b's fid. */
- uint16_t b_fid;
+ /* The port 0 RX mirror action record ID. */
+ uint16_t rx_ar_id_port0;
+ /* The port 1 RX mirror action record ID. */
+ uint16_t rx_ar_id_port1;
+ /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port0;
+ /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port1;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_pair_info *
+ **********************/
+
+
+/* hwrm_cfa_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_pair_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If this flag is set, lookup by name else lookup by index. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
+ /* If this flag is set, lookup by PF id and VF id. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
+ /* Pair table index. */
+ uint16_t pair_index;
+ /* Pair pf index. */
+ uint8_t pair_pfid;
+ /* Pair vf index. */
+ uint8_t pair_vfid;
+ /* Pair name (32 byte string). */
+ char pair_name[32];
+} __attribute__((packed));
+
+/* hwrm_cfa_pair_info_output (size:576b/72B) */
+struct hwrm_cfa_pair_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pair table index. */
+ uint16_t next_pair_index;
+ /* Pair member a's fid. */
+ uint16_t a_fid;
+ /* Logical host number. */
+ uint8_t host_a_index;
+ /* Logical PF number. */
+ uint8_t pf_a_index;
+ /* Pair member a's Linux logical VF number. */
+ uint16_t vf_a_index;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code_a;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action_a;
+ /* Pair member b's fid. */
+ uint16_t b_fid;
/* Logical host number. */
uint8_t host_b_index;
/* Logical PF number. */
@@ -26364,13 +28148,645 @@ struct hwrm_cfa_pair_info_output {
uint8_t valid;
} __attribute__((packed));
-/***************************************
- * hwrm_cfa_redirect_query_tunnel_type *
- ***************************************/
+/***************************************
+ * hwrm_cfa_redirect_query_tunnel_type *
+ ***************************************/
+
+
+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
+struct hwrm_cfa_redirect_query_tunnel_type_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The source function id. */
+ uint16_t src_fid;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
+struct hwrm_cfa_redirect_query_tunnel_type_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Tunnel Mask. */
+ uint32_t tunnel_mask;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ UINT32_C(0x1)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ UINT32_C(0x2)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ UINT32_C(0x4)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ UINT32_C(0x8)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ UINT32_C(0x10)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ UINT32_C(0x20)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ UINT32_C(0x40)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
+ UINT32_C(0x80)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
+ UINT32_C(0x100)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
+ UINT32_C(0x200)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
+ UINT32_C(0x400)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
+ UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_rgtr *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_rgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
+ uint32_t unused_0;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_rgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_cfa_ctx_mem_unrgtr *
+ ***************************/
+
+
+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_unrgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_unrgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_qctx *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_qctx_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_qctx_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
+ uint8_t unused_0[4];
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**************************
+ * hwrm_cfa_ctx_mem_qcaps *
+ **************************/
+
+
+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Indicates the maximum number of context memory which can be registered. */
+ uint16_t max_entries;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_eem_qcaps *
+ **********************/
+
+
+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_eem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
+ uint32_t supported;
+ /*
+ * If set to 1, then EEM KEY0 table is supported using crc32 hash.
+ * If set to 0 EEM KEY0 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
+ * If set to 0 EEM KEY1 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, then EEM External Record table is supported.
+ * If set to 0 EEM External Record table is not supported.
+ * (This table includes action record, EFC pointers, encap pointers)
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, then EEM External Flow Counters table is supported.
+ * If set to 0 EEM External Flow Counters table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+ UINT32_C(0x8)
+ /*
+ * The maximum number of entries supported by EEM. When configuring the host memory
+ * the number of numbers of entries that can supported are -
+ * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
+ * Any value that are not these values, the FW will round down to the closest support
+ * number of entries.
+ */
+ uint32_t max_entries_supported;
+ /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
+ uint16_t key_entry_size;
+ /* The entry size in bytes of each entry in the RECORD EEM tables. */
+ uint16_t record_entry_size;
+ /* The entry size in bytes of each entry in the EFC EEM tables. */
+ uint16_t efc_entry_size;
+ uint8_t unused_1;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************
+ * hwrm_cfa_eem_cfg *
+ ********************/
+
+
+/* hwrm_cfa_eem_cfg_input (size:320b/40B) */
+struct hwrm_cfa_eem_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+ /*
+ * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
+ * RECORD, EFC all have the same number of entries and all tables will be configured
+ * using this value. Current minimum value is 32k. Current maximum value is 128M.
+ */
+ uint32_t num_entries;
+ uint32_t unused_1;
+ /* Configured EEM with the given context if for KEY0 table. */
+ uint16_t key0_ctx_id;
+ /* Configured EEM with the given context if for KEY1 table. */
+ uint16_t key1_ctx_id;
+ /* Configured EEM with the given context if for RECORD table. */
+ uint16_t record_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t efc_ctx_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
+struct hwrm_cfa_eem_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_cfa_eem_qcfg *
+ *********************/
-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
-struct hwrm_cfa_redirect_query_tunnel_type_input {
+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26398,13 +28814,16 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The source function id. */
- uint16_t src_fid;
- uint8_t unused_0[6];
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
} __attribute__((packed));
-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
-struct hwrm_cfa_redirect_query_tunnel_type_output {
+/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26413,50 +28832,219 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Tunnel Mask. */
- uint32_t tunnel_mask;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
UINT32_C(0x1)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
UINT32_C(0x2)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ /* The number of entries the FW has configured for EEM. */
+ uint32_t num_entries;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************
+ * hwrm_cfa_eem_op *
+ *******************/
+
+
+/* hwrm_cfa_eem_op_input (size:192b/24B) */
+struct hwrm_cfa_eem_op_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the TX flow offload function specified in fid.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the RX flow offload function specified in fid.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint16_t unused_0;
+ /* The number of EEM key table entries to be configured. */
+ uint16_t op;
+ /* This value is reserved and should not be used. */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
+ /*
+ * To properly stop EEM and ensure there are no DMA's, the caller
+ * must disable EEM for the given PF, using this call. This will
+ * safely disable EEM and ensure that all DMA'ed to the
+ * keys/records/efc have been completed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
+ /*
+ * Once the EEM host memory has been configured, EEM options have
+ * been configured. Then the caller should enable EEM for the given
+ * PF. Note once this call has been made, then the EEM mechanism
+ * will be active and DMA's will occur as packets are processed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
+ /*
+ * Clear EEM settings for the given PF so that the register values
+ * are reset back to there initial state.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
+ #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
+ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_op_output (size:128b/16B) */
+struct hwrm_cfa_eem_op_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_adv_flow_mgnt_qcaps *
+ ********************************/
+
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Value of 1 to indicate firmware support 16-bit flow handle.
+ * Value of 0 to indicate firmware not support 16-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate firmware support 64-bit flow handle.
+ * Value of 0 to indicate firmware not support 64-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * Value of 1 to indicate firmware support flow batch delete operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 to indicate that the firmware does not support flow batch delete
+ * operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * Value of 1 to indicate that the firmware support flow reset all operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 indicates firmware does not support flow reset all operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
UINT32_C(0x8)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ /*
+ * Value of 1 to indicate that firmware supports use of FID as dest_id in
+ * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
+ * Value of 0 indicates firmware does not support use of FID as dest_id.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
UINT32_C(0x10)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ /*
+ * Value of 1 to indicate that firmware supports TX EEM flows.
+ * Value of 0 indicates firmware does not support TX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
UINT32_C(0x20)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ /*
+ * Value of 1 to indicate that firmware supports RX EEM flows.
+ * Value of 0 indicates firmware does not support RX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
- UINT32_C(0x80)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
- UINT32_C(0x100)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
- UINT32_C(0x200)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
- UINT32_C(0x400)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
- UINT32_C(0x800)
- /* Use fixed layer 2 ether type of 0xFFFF */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
- UINT32_C(0x1000)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
- UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -26874,7 +29462,11 @@ struct hwrm_stat_ctx_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This is the address for statistic block. */
+ /*
+ * This is the address for statistic block.
+ * > For new versions of the chip, this address should be 128B
+ * > aligned.
+ */
uint64_t stats_dma_addr;
/*
* The statistic block update period in ms.
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v4 8/8] net/bnxt: update HWRM API to version 1.10.0.74
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
` (6 preceding siblings ...)
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
@ 2019-05-29 15:02 ` Lance Richardson
7 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 15:02 UTC (permalink / raw)
To: dev; +Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.74
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
doc/guides/rel_notes/release_19_08.rst | 1 +
drivers/net/bnxt/hsi_struct_def_dpdk.h | 1399 ++++++++++++++++++++----
2 files changed, 1169 insertions(+), 231 deletions(-)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 7e5ca3c34..ea8fbcdfd 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -59,6 +59,7 @@ New Features
Updated the bnxt PMD. The major enhancements include:
* Performance optimizations in non-vector Tx path
* Added support for SSE vector mode
+ * Updated HWRM API to version 1.10.0.74
Removed Items
-------------
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 00a8ff87e..305ee09bc 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2019 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -27,7 +27,8 @@ struct hwrm_cmd_hdr {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -221,8 +222,14 @@ struct hwrm_short_input {
#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
#define HWRM_SHORT_INPUT_SIGNATURE_LAST \
HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
- /* Reserved for future use. */
- uint16_t unused_0;
+ /* The target ID of the command */
+ uint16_t target_id;
+ /* Default target_id (0x0) to maintain compatibility with old driver */
+ #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
+ /* Reserved for user-space HWRM interface */
+ #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
+ #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
+ HWRM_SHORT_INPUT_TARGET_ID_TOOLS
/* This value indicates the length of the request. */
uint16_t size;
/*
@@ -394,6 +401,8 @@ struct cmd_nums {
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
#define HWRM_OEM_CMD UINT32_C(0xd4)
+ /* Tells the fw to run PRBS test on a given port and lane. */
+ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
@@ -486,6 +495,8 @@ struct cmd_nums {
#define HWRM_CFA_EEM_OP UINT32_C(0x123)
/* Experimental */
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
+ /* Experimental */
+ #define HWRM_CFA_TFLIB UINT32_C(0x125)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -506,6 +517,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
/* Engine CKV - Configure a label index with a label value. */
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
+ /* Engine CKV - Query a label */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -587,6 +600,19 @@ struct cmd_nums {
/* Experimental */
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
/* Experimental */
+ #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
+ /* Returns the current value of a free running counter from the device. */
+ #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
+ /* Experimental */
+ #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
+ /* Experimental */
+ #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
+ /*
+ * Tells the fw to run the DMA read from the host and DMA write
+ * to the host test.
+ */
+ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
+ /* Experimental */
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
/* Experimental */
#define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
@@ -643,67 +669,85 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
/*
* This error code is only reported by firmware when the specific
* request is not able to process when the HOT reset in progress.
*/
- #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
/*
* This error code is only reported by firmware when the registered
* driver instances are not capable of hot reset.
*/
- #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ /*
+ * This error code is only reported by the firmware when during
+ * flow allocation when a requeest for a flow counter fails because
+ * the number of flow counters are exhausted.
+ */
+ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the requested key's hash collides with the installed keys.
+ */
+ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the same key has already been installed.
+ */
+ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
@@ -711,11 +755,11 @@ struct ret_codes {
* by itself, just an indicatation that the response should be parsed
* as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
*/
- #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -774,12 +818,25 @@ struct hwrm_err_output {
#define HW_HASH_KEY_SIZE 40
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
+/* Reserved for BONO processor */
+#define HWRM_TARGET_ID_BONO 0xFFF8
+/* Reserved for KONG processor */
+#define HWRM_TARGET_ID_KONG 0xFFF9
+/* Reserved for APE processor */
+#define HWRM_TARGET_ID_APE 0xFFFA
+/*
+ * This value will be used by tools for User-space HWRM Interface.
+ * When tool execute any HWRM command with this target_id, firmware
+ * will copy the response and/or data payload via register space instead
+ * of DMAing it.
+ */
+#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 48
-#define HWRM_VERSION_STR "1.10.0.48"
+#define HWRM_VERSION_RSVD 74
+#define HWRM_VERSION_STR "1.10.0.74"
/****************
* hwrm_ver_get *
@@ -804,7 +861,8 @@ struct hwrm_ver_get_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -1062,6 +1120,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
UINT32_C(0x1000)
+ /*
+ * If set to 1, the firmware is able to support TFLIB features.
+ * If set to 0, then the firmware doesn’t support TFLIB features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
+ UINT32_C(0x2000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -1099,12 +1164,8 @@ struct hwrm_ver_get_output {
* firmware (ASCII chars with NULL at the end).
*/
char netctrl_fw_name[16];
- /*
- * This field is reserved for future use.
- * The responder should set it to 0.
- * The requester should ignore this field.
- */
- uint8_t reserved2[16];
+ /* This field represents the active board package name. */
+ char active_pkg_name[16];
/*
* This field represents the name of RoCE FW (ASCII chars
* with NULL at the end).
@@ -3845,6 +3906,12 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
UINT32_C(0x3c)
+ /* TFLIB unique default VNIC Configuration Change */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
+ UINT32_C(0x3d)
+ /* TFLIB unique link status changed */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
+ UINT32_C(0x3e)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -5859,7 +5926,8 @@ struct hwrm_func_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -5962,7 +6030,8 @@ struct hwrm_func_getfid_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6038,7 +6107,8 @@ struct hwrm_func_vf_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6110,7 +6180,8 @@ struct hwrm_func_vf_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6183,7 +6254,8 @@ struct hwrm_func_vf_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6446,7 +6518,8 @@ struct hwrm_func_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6663,6 +6736,13 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
UINT32_C(0x800000)
+ /*
+ * If the query is for a VF, then this flag shall be ignored.
+ * If this query is for a PF and this flag is set to 1, then
+ * the PF has the capability to support extended stats.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
+ UINT32_C(0x1000000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6807,7 +6887,8 @@ struct hwrm_func_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7247,7 +7328,8 @@ struct hwrm_func_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7889,7 +7971,8 @@ struct hwrm_func_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8014,7 +8097,8 @@ struct hwrm_func_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8078,7 +8162,8 @@ struct hwrm_func_vf_resc_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8141,7 +8226,8 @@ struct hwrm_func_drv_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8382,7 +8468,8 @@ struct hwrm_func_drv_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8447,7 +8534,8 @@ struct hwrm_func_buf_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8581,7 +8669,8 @@ struct hwrm_func_buf_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8650,7 +8739,8 @@ struct hwrm_func_drv_qver_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8757,7 +8847,8 @@ struct hwrm_func_resource_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8886,7 +8977,8 @@ struct hwrm_func_backing_store_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8973,7 +9065,10 @@ struct hwrm_func_backing_store_qcaps_output {
* the backing store.
*/
uint32_t tqm_max_entries_per_ring;
- /* Maximum number of MR/AV context entries supported for this function. */
+ /*
+ * Maximum number of MR plus AV context entries supported for this
+ * function.
+ */
uint32_t mrav_max_entries;
/* Number of bytes that must be allocated for each context entry. */
uint16_t mrav_entry_size;
@@ -8981,7 +9076,22 @@ struct hwrm_func_backing_store_qcaps_output {
uint16_t tim_entry_size;
/* Maximum number of Timer context entries supported for this function. */
uint32_t tim_max_entries;
- uint8_t unused_0[2];
+ /*
+ * When this field is zero, the 32b `mrav_num_entries` field in the
+ * `backing_store_cfg` and `backing_store_qcfg` commands represents
+ * the total number of MR plus AV entries allowed in the MR/AV backing
+ * store PBL.
+ *
+ * When this field is non-zero, the 32b `mrav_num_entries` field in
+ * the `backing_store_cfg` and `backing_store_qcfg` commands is
+ * logically divided into two 16b fields. Bits `[31:16]` represents
+ * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
+ * Both of these values are represented in a unit granularity
+ * specified by this field. For example, if this field is 16 and
+ * `mrav_num_entries` is `0x02000100`, then the number of MR entries
+ * is 8192 and the number of AV entries is 4096.
+ */
+ uint16_t mrav_num_entries_units;
/*
* The number of entries specified for any TQM ring must be a
* multiple of this value to prevent any resource allocation
@@ -9021,7 +9131,8 @@ struct hwrm_func_backing_store_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -9041,6 +9152,12 @@ struct hwrm_func_backing_store_cfg_input {
*/
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint32_t enables;
/*
* This bit must be '1' for the qp fields to be
@@ -9958,7 +10075,20 @@ struct hwrm_func_backing_store_cfg_input {
* the backing store.
*/
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10036,7 +10166,8 @@ struct hwrm_func_backing_store_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -10068,6 +10199,12 @@ struct hwrm_func_backing_store_qcfg_output {
*/
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint8_t unused_0[4];
/*
* This bit must be '1' for the qp fields to be
@@ -10891,7 +11028,20 @@ struct hwrm_func_backing_store_qcfg_output {
uint32_t tqm_ring6_num_entries;
/* Number of TQM ring 7 entries. */
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10930,7 +11080,8 @@ struct hwrm_error_recovery_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11296,7 +11447,8 @@ struct hwrm_func_vlan_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11386,7 +11538,8 @@ struct hwrm_func_vlan_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11507,7 +11660,8 @@ struct hwrm_func_vf_vnic_ids_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11580,7 +11734,8 @@ struct hwrm_func_vf_bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11704,7 +11859,8 @@ struct hwrm_func_vf_bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11841,7 +11997,8 @@ struct hwrm_func_drv_if_change_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11929,7 +12086,8 @@ struct hwrm_port_phy_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -12520,7 +12678,8 @@ struct hwrm_port_phy_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13389,7 +13548,7 @@ struct hwrm_port_phy_qcfg_output {
*********************/
-/* hwrm_port_mac_cfg_input (size:320b/40B) */
+/* hwrm_port_mac_cfg_input (size:384b/48B) */
struct hwrm_port_mac_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13407,7 +13566,8 @@ struct hwrm_port_mac_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13527,6 +13687,13 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
UINT32_C(0x1000)
+ /*
+ * When this bit is set to '1', and the ptp_tx_ts_capture_enable
+ * bit is set, then the device uses one step Tx timestamping.
+ * This bit is temporary and used for experimental purposes.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
+ UINT32_C(0x2000)
uint32_t enables;
/*
* This bit must be '1' for the ipg field to be
@@ -13576,6 +13743,12 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ppb field to be
+ * configured.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
+ UINT32_C(0x200)
/* Port ID of port that is to be configured. */
uint16_t port_id;
/*
@@ -13763,6 +13936,12 @@ struct hwrm_port_mac_cfg_input {
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
5
uint8_t unused_0[3];
+ /*
+ * This signed field specifies by how much to adjust the frequency
+ * of sync timer updates (measured in parts per billion).
+ */
+ int32_t ptp_freq_adj_ppb;
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_port_mac_cfg_output (size:128b/16B) */
@@ -13842,7 +14021,8 @@ struct hwrm_port_mac_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14131,7 +14311,8 @@ struct hwrm_port_mac_ptp_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14174,6 +14355,12 @@ struct hwrm_port_mac_ptp_qcfg_output {
*/
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', the device supports one-step
+ * Tx timestamping.
+ */
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
+ UINT32_C(0x4)
uint8_t unused_0[3];
/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
uint32_t rx_ts_reg_off_lower;
@@ -14595,7 +14782,8 @@ struct hwrm_port_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14716,7 +14904,7 @@ struct tx_port_stats_ext {
} __attribute__((packed));
/* Port Rx Statistics extended Formats */
-/* rx_port_stats_ext (size:2368b/296B) */
+/* rx_port_stats_ext (size:3648b/456B) */
struct rx_port_stats_ext {
/* Number of times link state changed to down */
uint64_t link_down_events;
@@ -14792,6 +14980,49 @@ struct rx_port_stats_ext {
uint64_t pfc_pri7_rx_duration_us;
/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
uint64_t pfc_pri7_rx_transitions;
+ /* Total number of received bits */
+ uint64_t rx_bits;
+ /* The number of events where the port receive buffer was over 85% full */
+ uint64_t rx_buffer_passed_threshold;
+ /*
+ * The number of symbol errors that wasn't corrected by FEC correction
+ * alogirithm
+ */
+ uint64_t rx_pcs_symbol_err;
+ /* The number of corrected bits on the port according to active FEC */
+ uint64_t rx_corrected_bits;
+ /* Total number of rx discard bytes count on cos queue 0 */
+ uint64_t rx_discard_bytes_cos0;
+ /* Total number of rx discard bytes count on cos queue 1 */
+ uint64_t rx_discard_bytes_cos1;
+ /* Total number of rx discard bytes count on cos queue 2 */
+ uint64_t rx_discard_bytes_cos2;
+ /* Total number of rx discard bytes count on cos queue 3 */
+ uint64_t rx_discard_bytes_cos3;
+ /* Total number of rx discard bytes count on cos queue 4 */
+ uint64_t rx_discard_bytes_cos4;
+ /* Total number of rx discard bytes count on cos queue 5 */
+ uint64_t rx_discard_bytes_cos5;
+ /* Total number of rx discard bytes count on cos queue 6 */
+ uint64_t rx_discard_bytes_cos6;
+ /* Total number of rx discard bytes count on cos queue 7 */
+ uint64_t rx_discard_bytes_cos7;
+ /* Total number of rx discard packets count on cos queue 0 */
+ uint64_t rx_discard_packets_cos0;
+ /* Total number of rx discard packets count on cos queue 1 */
+ uint64_t rx_discard_packets_cos1;
+ /* Total number of rx discard packets count on cos queue 2 */
+ uint64_t rx_discard_packets_cos2;
+ /* Total number of rx discard packets count on cos queue 3 */
+ uint64_t rx_discard_packets_cos3;
+ /* Total number of rx discard packets count on cos queue 4 */
+ uint64_t rx_discard_packets_cos4;
+ /* Total number of rx discard packets count on cos queue 5 */
+ uint64_t rx_discard_packets_cos5;
+ /* Total number of rx discard packets count on cos queue 6 */
+ uint64_t rx_discard_packets_cos6;
+ /* Total number of rx discard packets count on cos queue 7 */
+ uint64_t rx_discard_packets_cos7;
} __attribute__((packed));
/************************
@@ -14817,7 +15048,8 @@ struct hwrm_port_qstats_ext_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14909,7 +15141,8 @@ struct hwrm_port_lpbk_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14986,7 +15219,8 @@ struct hwrm_port_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15057,7 +15291,8 @@ struct hwrm_port_phy_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15311,7 +15546,8 @@ struct hwrm_port_phy_mdio_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15387,7 +15623,8 @@ struct hwrm_port_phy_mdio_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15463,7 +15700,8 @@ struct hwrm_port_led_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15886,7 +16124,8 @@ struct hwrm_port_led_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16191,7 +16430,8 @@ struct hwrm_port_led_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16519,6 +16759,137 @@ struct hwrm_port_led_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/***********************
+ * hwrm_port_prbs_test *
+ ***********************/
+
+
+/* hwrm_port_prbs_test_input (size:384b/48B) */
+struct hwrm_port_prbs_test_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Host address data is to DMA'd to. */
+ uint64_t resp_data_addr;
+ /*
+ * Size of the buffer pointed to by resp_data_addr. The firmware may
+ * use this entire buffer or less than the entire buffer, but never more.
+ */
+ uint16_t data_len;
+ uint16_t unused_0;
+ uint32_t unused_1;
+ /* Port ID of port where PRBS test to be run. */
+ uint16_t port_id;
+ /* Polynomial selection for PRBS test. */
+ uint16_t poly;
+ /* PRBS7 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
+ /* PRBS9 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
+ /* PRBS11 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
+ /* PRBS15 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
+ /* PRBS23 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
+ /* PRBS31 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
+ /* PRBS58 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* Invalid */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
+ HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
+ /*
+ * Configuration bits for PRBS test.
+ * Use enable bit to start/stop test.
+ * Use tx/rx lane map bits to run test on specific lanes,
+ * if set to 0 test will be run on all lanes.
+ */
+ uint16_t prbs_config;
+ /*
+ * Set 0 to stop test currently in progress
+ * Set 1 to start test with configuration provided.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, tx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, rx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
+ UINT32_C(0x4)
+ /* Duration in seconds to run the PRBS test. */
+ uint16_t timeout;
+ /*
+ * If tx_lane_map_valid is set to 1, this field is a bitmap
+ * of tx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t tx_lane_map;
+ /*
+ * If rx_lane_map_valid is set to 1, this field is a bitmap
+ * of rx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t rx_lane_map;
+} __attribute__((packed));
+
+/* hwrm_port_prbs_test_output (size:128b/16B) */
+struct hwrm_port_prbs_test_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -16542,7 +16913,8 @@ struct hwrm_queue_qportcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16994,7 +17366,8 @@ struct hwrm_queue_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17091,7 +17464,8 @@ struct hwrm_queue_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17194,7 +17568,8 @@ struct hwrm_queue_pfcenable_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17283,7 +17658,8 @@ struct hwrm_queue_pfcenable_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17372,7 +17748,8 @@ struct hwrm_queue_pri2cos_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17522,7 +17899,8 @@ struct hwrm_queue_pri2cos_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17698,7 +18076,8 @@ struct hwrm_queue_cos2bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -18740,7 +19119,8 @@ struct hwrm_queue_cos2bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19831,7 +20211,8 @@ struct hwrm_vnic_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19897,7 +20278,8 @@ struct hwrm_vnic_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19957,7 +20339,8 @@ struct hwrm_vnic_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20172,7 +20555,8 @@ struct hwrm_vnic_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20327,7 +20711,8 @@ struct hwrm_vnic_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20419,7 +20804,13 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
UINT32_C(0x80)
- uint8_t unused_1[7];
+ /*
+ * This field advertises the maximum concurrent TPA aggregations
+ * supported by the VNIC on new devices that support TPA v2.
+ * '0' means that TPA v2 is not supported.
+ */
+ uint16_t max_aggs_supported;
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -20453,7 +20844,8 @@ struct hwrm_vnic_tpa_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20529,6 +20921,15 @@ struct hwrm_vnic_tpa_cfg_input {
*/
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
UINT32_C(0x80)
+ /*
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall DMA payload data using GRO rules.
+ * When this bit is '0', the VNIC shall DMA payload data
+ * using the more efficient LRO rules of filling all
+ * aggregation buffers.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
+ UINT32_C(0x100)
uint32_t enables;
/*
* This bit must be '1' for the max_agg_segs field to be
@@ -20545,16 +20946,15 @@ struct hwrm_vnic_tpa_cfg_input {
* configured.
*/
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
- /*
- * This bit must be '1' for the min_agg_len field to be
- * configured.
- */
+ /* deprecated bit. Do not use!!! */
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
/* Logical vnic ID */
uint16_t vnic_id;
/*
* This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31.
+ * be aggregated (unit is Log2). Max value is 31. On new
+ * devices supporting TPA v2, the unit is multiples of 4 and
+ * valid values are > 0 and <= 63.
*/
uint16_t max_agg_segs;
/* 1 segment */
@@ -20571,7 +20971,10 @@ struct hwrm_vnic_tpa_cfg_input {
HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
/*
* This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7
+ * allowed (unit is Log2). Max value is 7. On new devices
+ * supporting TPA v2, this is in unit of 1 and must be > 0
+ * and <= max_aggs_supported in the hwrm_vnic_qcaps response
+ * to enable TPA v2.
*/
uint16_t max_aggs;
/* 1 aggregation */
@@ -20596,7 +20999,9 @@ struct hwrm_vnic_tpa_cfg_input {
uint32_t max_agg_timer;
/*
* This is the minimum amount of payload length required to
- * start an aggregation context.
+ * start an aggregation context. This field is deprecated and
+ * should be set to 0. The minimum length is set by firmware
+ * and can be queried using hwrm_vnic_tpa_qcfg.
*/
uint32_t min_agg_len;
} __attribute__((packed));
@@ -20645,7 +21050,8 @@ struct hwrm_vnic_rss_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20795,7 +21201,8 @@ struct hwrm_vnic_rss_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20937,7 +21344,8 @@ struct hwrm_vnic_plcmodes_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21100,7 +21508,8 @@ struct hwrm_vnic_plcmodes_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21228,7 +21637,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21287,7 +21697,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21347,7 +21758,8 @@ struct hwrm_ring_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21687,7 +22099,8 @@ struct hwrm_ring_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21764,7 +22177,8 @@ struct hwrm_ring_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21839,7 +22253,8 @@ struct hwrm_ring_aggint_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21988,7 +22403,8 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22094,7 +22510,8 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22250,7 +22667,8 @@ struct hwrm_ring_grp_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22334,7 +22752,8 @@ struct hwrm_ring_grp_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22414,7 +22833,8 @@ struct hwrm_cfa_l2_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22476,6 +22896,22 @@ struct hwrm_cfa_l2_filter_alloc_input {
(UINT32_C(0x2) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
+ /*
+ * Setting of this flag indicates that no XDP filter is created with
+ * L2 filter.
+ * 0 - legacy behavior, XDP filter is created with L2 filter
+ * 1 - XDP filter won't be created with L2 filter
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
+ UINT32_C(0x40)
+ /*
+ * Setting this flag to 1 indicate the L2 fields in this command
+ * pertain to source fields. Setting this flag to 0 indicate the
+ * L2 fields in this command pertain to the destination fields
+ * and this is the default/legacy behavior.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
+ UINT32_C(0x80)
uint32_t enables;
/*
* This bit must be '1' for the l2_addr field to be
@@ -22579,13 +23015,31 @@ struct hwrm_cfa_l2_filter_alloc_input {
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
+ UINT32_C(0x20000)
+ /*
+ * This bit must be '1' for the t_num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
+ UINT32_C(0x40000)
/*
* This value sets the match value for the L2 MAC address.
* Destination MAC address for RX path.
* Source MAC address for TX path.
*/
uint8_t l2_addr[6];
- uint8_t unused_0[2];
+ /* This value sets the match value for the number of VLANs. */
+ uint8_t num_vlans;
+ /*
+ * This value sets the match value for the number of VLANs
+ * in the tunnel headers.
+ */
+ uint8_t t_num_vlans;
/*
* This value sets the mask value for the L2 address.
* A value of 0 will mask the corresponding bit from
@@ -22784,13 +23238,45 @@ struct hwrm_cfa_l2_filter_alloc_output {
*/
uint64_t l2_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -22825,7 +23311,8 @@ struct hwrm_cfa_l2_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22887,7 +23374,8 @@ struct hwrm_cfa_l2_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23014,7 +23502,8 @@ struct hwrm_cfa_l2_set_rx_mask_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23213,7 +23702,8 @@ struct hwrm_cfa_vlan_antispoof_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23287,7 +23777,8 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23366,7 +23857,8 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23602,13 +24094,45 @@ struct hwrm_cfa_tunnel_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t tunnel_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -23643,7 +24167,8 @@ struct hwrm_cfa_tunnel_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23702,7 +24227,8 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23813,7 +24339,8 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23919,7 +24446,8 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24134,7 +24662,8 @@ struct hwrm_cfa_encap_record_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24247,7 +24776,8 @@ struct hwrm_cfa_encap_record_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24289,7 +24819,7 @@ struct hwrm_cfa_encap_record_free_output {
********************************/
-/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
+/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
struct hwrm_cfa_ntuple_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -24307,7 +24837,8 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24456,6 +24987,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
UINT32_C(0x40000)
+ /*
+ * This bit must be '1' for the rfs_ring_tbl_idx field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
+ UINT32_C(0x80000)
/*
* This value identifies a set of CFA data structures used for an L2
* context.
@@ -24639,6 +25176,13 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
* the pri_hint.
*/
uint64_t ntuple_filter_id_hint;
+ /*
+ * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
+ * This index is used in lieu of the RSS hash when selecting the
+ * index into the RSS table to determine the rx ring.
+ */
+ uint16_t rfs_ring_tbl_idx;
+ uint8_t unused_0[6];
} __attribute__((packed));
/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
@@ -24654,13 +25198,45 @@ struct hwrm_cfa_ntuple_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24713,7 +25289,8 @@ struct hwrm_cfa_ntuple_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24772,7 +25349,8 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24884,7 +25462,8 @@ struct hwrm_cfa_em_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25216,13 +25795,45 @@ struct hwrm_cfa_em_flow_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t em_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -25257,7 +25868,8 @@ struct hwrm_cfa_em_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25316,7 +25928,8 @@ struct hwrm_cfa_meter_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25428,7 +26041,8 @@ struct hwrm_cfa_meter_profile_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25705,7 +26319,8 @@ struct hwrm_cfa_meter_profile_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25789,7 +26404,8 @@ struct hwrm_cfa_meter_profile_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26059,7 +26675,8 @@ struct hwrm_cfa_meter_instance_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26154,7 +26771,8 @@ struct hwrm_cfa_meter_instance_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26246,7 +26864,8 @@ struct hwrm_cfa_meter_instance_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26330,7 +26949,8 @@ struct hwrm_cfa_decap_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26654,7 +27274,8 @@ struct hwrm_cfa_decap_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26714,7 +27335,8 @@ struct hwrm_cfa_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26847,6 +27469,15 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
UINT32_C(0x1000)
+ /*
+ * If set to 1 there will be no attempt to allocate an on-chip try to
+ * offload this flow. If set to 0, which will keep compatibility with the
+ * older drivers, will cause the FW to attempt to allocate an on-chip flow
+ * counter for the newly created flow. This will keep the existing behavior
+ * with EM flows which always had an associated flow counter.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
+ UINT32_C(0x2000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -26977,13 +27608,45 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t flow_handle;
uint8_t unused_0[2];
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
uint32_t flow_counter_id;
@@ -26998,6 +27661,34 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
+struct hwrm_cfa_flow_alloc_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* No more L2 Context TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
+ /* No more action records */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
+ /* No more flow counters */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
+ /* No more wild-card TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
+ /* Hash collsion in exact match tables */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
+ /* Key is already installed */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
+ /* Flow Context DB is out of resource */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
+ HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_free *
**********************/
@@ -27021,7 +27712,8 @@ struct hwrm_cfa_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27034,7 +27726,9 @@ struct hwrm_cfa_flow_free_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint16_t unused_0;
+ /* Flow counter id to be freed. */
+ uint32_t flow_counter_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -27310,7 +28004,8 @@ struct hwrm_cfa_flow_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27420,7 +28115,8 @@ struct hwrm_cfa_flow_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27448,6 +28144,9 @@ struct hwrm_cfa_flow_flush_input {
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
UINT32_C(0x2)
+ /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
+ UINT32_C(0x8000000)
/*
* This specifies the size of flow handle entries provided by the driver
* in the flow table specified below. Only two flow handle size enums are defined.
@@ -27544,7 +28243,8 @@ struct hwrm_cfa_flow_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27684,7 +28384,8 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27733,7 +28434,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output {
***************************/
-/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -27751,7 +28452,8 @@ struct hwrm_cfa_flow_aging_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27773,16 +28475,40 @@ struct hwrm_cfa_flow_aging_cfg_input {
/* This bit must be '1' for the udp flow timer field to be configured */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
UINT32_C(0x4)
- /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ /* This bit must be '1' for the eem dma interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
+ UINT32_C(0x8)
+ /* This bit must be '1' for the eem notice interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
+ UINT32_C(0x10)
+ /* This bit must be '1' for the eem context memory maximum entries field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
+ UINT32_C(0x20)
+ /* This bit must be '1' for the eem context memory ID field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
+ UINT32_C(0x40)
+ /* This bit must be '1' for the eem context memory type field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
+ UINT32_C(0x80)
uint8_t flags;
/* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ /* Enumeration denoting the enable, disable eem flow aging configuration. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
+ (UINT32_C(0x0) << 1)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
uint8_t unused_0;
/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
uint32_t tcp_flow_timer;
@@ -27790,6 +28516,21 @@ struct hwrm_cfa_flow_aging_cfg_input {
uint32_t tcp_fin_timer;
/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
uint32_t udp_flow_timer;
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ uint16_t eem_ctx_mem_type;
+ /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
+ UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
@@ -27836,7 +28577,8 @@ struct hwrm_cfa_flow_aging_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27860,7 +28602,7 @@ struct hwrm_cfa_flow_aging_qcfg_input {
uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -27876,7 +28618,17 @@ struct hwrm_cfa_flow_aging_qcfg_output {
uint32_t tcp_fin_timer;
/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
uint32_t udp_flow_timer;
- uint8_t unused_0[3];
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ /* The context memory type for eem flow aging. */
+ uint16_t eem_ctx_mem_type;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -27910,7 +28662,8 @@ struct hwrm_cfa_flow_aging_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27986,7 +28739,8 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28051,7 +28805,8 @@ struct hwrm_cfa_pair_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28171,7 +28926,8 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28275,7 +29031,8 @@ struct hwrm_cfa_ctx_mem_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28371,7 +29128,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28434,7 +29192,8 @@ struct hwrm_cfa_ctx_mem_qctx_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28531,7 +29290,8 @@ struct hwrm_cfa_ctx_mem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28582,7 +29342,8 @@ struct hwrm_cfa_eem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28630,13 +29391,31 @@ struct hwrm_cfa_eem_qcaps_output {
* which are to be offloaded.
* Note if this bit is set then the path_rx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
/*
* When set to 1, indicates the configuration will apply to RX flows
* which are to be offloaded.
* Note if this bit is set then the path_tx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /*
+ * When set to 1, indicates the the FW supports the Centralized
+ * Memory Model. The concept designates one entity for the
+ * memory allocation while all others ‘subscribe’ to it.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * When set to 1, indicates the the FW supports the Detached
+ * Centralized Memory Model. The memory is allocated and managed
+ * as a separate entity. All PFs and VFs will be granted direct
+ * or semi-direct access to the allocated memory while none of
+ * which can interfere with the management of the memory.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x8)
uint32_t unused_0;
uint32_t supported;
/*
@@ -28712,7 +29491,8 @@ struct hwrm_cfa_eem_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28741,7 +29521,15 @@ struct hwrm_cfa_eem_cfg_input {
/* When set to 1, all offloaded flows will be sent to EEM. */
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- uint32_t unused_0;
+ /* When set to 1, secondary, 0 means primary. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
+ UINT32_C(0x8)
+ /*
+ * Group_id which used by Firmware to identify memory pools belonging
+ * to certain group.
+ */
+ uint16_t group_id;
+ uint16_t unused_0;
/*
* Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
* RECORD, EFC all have the same number of entries and all tables will be configured
@@ -28803,7 +29591,8 @@ struct hwrm_cfa_eem_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28878,7 +29667,8 @@ struct hwrm_cfa_eem_op_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28974,7 +29764,8 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29045,6 +29836,42 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
+ /*
+ * Value of 1 to indicate that firmware supports the dynamic allocation of an
+ * on-chip flow counter which can be used for EEM flows.
+ * Value of 0 indicates firmware does not support the dynamic allocation of an
+ * on-chip flow counter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
+ * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * Value of 1 to indicate that firmware supports untagged matching
+ * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
+ * indicates firmware does not support untagged matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * Value of 1 to indicate that firmware supports XDP filter. Value
+ * of 0 indicates firmware does not support XDP filter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * Value of 1 to indicate that the firmware support L2 header source
+ * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
+ * Value of 0 indicates firmware does not support L2 header source
+ * fields matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
+ UINT32_C(0x800)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -29056,6 +29883,81 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/******************
+ * hwrm_cfa_tflib *
+ ******************/
+
+
+/* hwrm_cfa_tflib_input (size:1024b/128B) */
+struct hwrm_cfa_tflib_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* unused. */
+ uint8_t unused0[4];
+ /* TFLIB request data. */
+ uint32_t tf_req[26];
+} __attribute__((packed));
+
+/* hwrm_cfa_tflib_output (size:5632b/704B) */
+struct hwrm_cfa_tflib_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* TFLIB response code */
+ uint32_t tf_resp_code;
+ /* TFLIB response data. */
+ uint32_t tf_resp[170];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/******************************
* hwrm_tunnel_dst_port_query *
******************************/
@@ -29079,7 +29981,8 @@ struct hwrm_tunnel_dst_port_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29177,7 +30080,8 @@ struct hwrm_tunnel_dst_port_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29274,7 +30178,8 @@ struct hwrm_tunnel_dst_port_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29451,7 +30356,8 @@ struct hwrm_stat_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29540,7 +30446,8 @@ struct hwrm_stat_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29602,7 +30509,8 @@ struct hwrm_stat_ctx_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29702,7 +30610,8 @@ struct hwrm_stat_ctx_eng_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29803,7 +30712,8 @@ struct hwrm_stat_ctx_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29863,7 +30773,8 @@ struct hwrm_pcie_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29970,7 +30881,8 @@ struct hwrm_exec_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30043,7 +30955,8 @@ struct hwrm_reject_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30116,7 +31029,8 @@ struct hwrm_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30204,7 +31118,8 @@ struct hwrm_fwd_async_event_cmpl_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30273,7 +31188,8 @@ struct hwrm_nvm_raw_write_blk_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30342,7 +31258,8 @@ struct hwrm_nvm_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30412,7 +31329,8 @@ struct hwrm_nvm_raw_dump_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30478,7 +31396,8 @@ struct hwrm_nvm_get_dir_entries_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30540,7 +31459,8 @@ struct hwrm_nvm_get_dir_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30601,7 +31521,8 @@ struct hwrm_nvm_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30722,7 +31643,8 @@ struct hwrm_nvm_modify_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30795,7 +31717,8 @@ struct hwrm_nvm_find_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30897,7 +31820,8 @@ struct hwrm_nvm_erase_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30957,7 +31881,8 @@ struct hwrm_nvm_get_dev_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30991,7 +31916,12 @@ struct hwrm_nvm_get_dev_info_output {
uint32_t reserved_size;
/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
uint32_t available_size;
- uint8_t unused_0[3];
+ /* This field represents the major version of NVM cfg */
+ uint8_t nvm_cfg_ver_maj;
+ /* This field represents the minor version of NVM cfg */
+ uint8_t nvm_cfg_ver_min;
+ /* This field represents the update version of NVM cfg */
+ uint8_t nvm_cfg_ver_upd;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -31025,7 +31955,8 @@ struct hwrm_nvm_mod_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31104,7 +32035,8 @@ struct hwrm_nvm_verify_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31177,7 +32109,8 @@ struct hwrm_nvm_install_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31340,7 +32273,8 @@ struct hwrm_nvm_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31413,7 +32347,8 @@ struct hwrm_nvm_get_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31548,7 +32483,8 @@ struct hwrm_nvm_set_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31678,7 +32614,8 @@ struct hwrm_nvm_validate_option_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread
* [dpdk-dev] [PATCH v5 0/8] bnxt patchset
2019-05-21 21:39 [dpdk-dev] [PATCH 00/11] bnxt patchset Ajit Khaparde
` (13 preceding siblings ...)
2019-05-29 15:02 ` [dpdk-dev] [PATCH v4 0/8] bnxt patchset Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 1/8] net/bnxt: update release notes for bnxt Lance Richardson
` (8 more replies)
14 siblings, 9 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
This patchset adds the following:
1) Support for vector mode TX and RX.
2) HWRM API update (split into multiple patches).
3) Fixes for RSS reta update and query.
It also updates the release notes.
v2:
* Squashed patches 3 and 4 from v1 patchset.
* Added Meson build support for vector mode PMD.
* Dropped two unnecessary code style changes from patch 3.
v3:
* Squashed three RSS RETA fix patches into one.
* Eliminated RTE_LIBRTE_BNXT_INC_VECTOR configuration flag.
* Addressed commit log issues from check-git-log.sh.
* Made subject line consistent for HWRM API update patches.
* Separated release notes updates to keep update with associated
patch (except for the first update for which the associated patch
has already been applied).
v4:
* The change squashed from patch 4 into patch 3 from the v1
patchset should have been squashed into patch 2; fixed in v4.
v5:
* Corrected commit IDs and added Fixes: tags to patch 01.
Ajit Khaparde (5):
net/bnxt: update release notes for bnxt
net/bnxt: fix RSS RETA indirection table ops
net/bnxt: update HWRM API to version 1.10.0.19
net/bnxt: update HWRM API to version 1.10.0.48
net/bnxt: update HWRM API to version 1.10.0.74
Lance Richardson (3):
net/bnxt: move Tx bd checking to header file
net/bnxt: compute and store scattered Rx status
net/bnxt: implement vector mode driver
doc/guides/rel_notes/release_19_08.rst | 6 +
drivers/net/bnxt/Makefile | 3 +
drivers/net/bnxt/bnxt_ethdev.c | 201 +-
drivers/net/bnxt/bnxt_hwrm.c | 1 +
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 ++
drivers/net/bnxt/bnxt_txr.c | 15 -
drivers/net/bnxt/bnxt_txr.h | 20 +
drivers/net/bnxt/hsi_struct_def_dpdk.h | 7573 ++++++++++++++++++++----
drivers/net/bnxt/meson.build | 4 +
13 files changed, 7219 insertions(+), 1106 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 1/8] net/bnxt: update release notes for bnxt
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
` (7 subsequent siblings)
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update release doc briefly describing updates to bnxt PMD,
including transmit optimization changes in the commits
identified by the "Fixes:" tags below.
Fixes: 5ef3592c97b9 ("net/bnxt: support bulk free of Tx mbufs")
Fixes: 220de9869bc3 ("net/bnxt: optimize Tx batching")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v5:
* Corrected commit IDs and added Fixes: tags to commit log.
doc/guides/rel_notes/release_19_08.rst | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 5ebb564b1..2b66f41f5 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -54,6 +54,10 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
+* **Updated the bnxt PMD.**
+
+ Updated the bnxt PMD. The major enhancements include:
+ * Performance optimizations in non-vector Tx path
Removed Items
-------------
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 2/8] net/bnxt: move Tx bd checking to header file
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 1/8] net/bnxt: update release notes for bnxt Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
` (6 subsequent siblings)
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
To allow sharing of tx_bds_in_hw() and bnxt_tx_avail() between
vector-mode and non-vector transmit functions, move these functions
into bnxt_txr.h.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
drivers/net/bnxt/bnxt_txr.c | 15 ---------------
drivers/net/bnxt/bnxt_txr.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_txr.c b/drivers/net/bnxt/bnxt_txr.c
index 9de12e0d0..16598ba63 100644
--- a/drivers/net/bnxt/bnxt_txr.c
+++ b/drivers/net/bnxt/bnxt_txr.c
@@ -103,21 +103,6 @@ int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id)
return 0;
}
-static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
-{
- return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
- txq->tx_ring->tx_ring_struct->ring_mask);
-}
-
-static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
-{
- /* Tell compiler to fetch tx indices from memory. */
- rte_compiler_barrier();
-
- return ((txq->tx_ring->tx_ring_struct->ring_size -
- bnxt_tx_bds_in_hw(txq)) - 1);
-}
-
static uint16_t bnxt_start_xmit(struct rte_mbuf *tx_pkt,
struct bnxt_tx_queue *txq,
uint16_t *coal_pkts,
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index f802d5080..13ca04676 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -37,6 +37,21 @@ struct bnxt_sw_tx_bd {
unsigned short nr_bds;
};
+static inline uint32_t bnxt_tx_bds_in_hw(struct bnxt_tx_queue *txq)
+{
+ return ((txq->tx_ring->tx_prod - txq->tx_ring->tx_cons) &
+ txq->tx_ring->tx_ring_struct->ring_mask);
+}
+
+static inline uint32_t bnxt_tx_avail(struct bnxt_tx_queue *txq)
+{
+ /* Tell compiler to fetch tx indices from memory. */
+ rte_compiler_barrier();
+
+ return ((txq->tx_ring->tx_ring_struct->ring_size -
+ bnxt_tx_bds_in_hw(txq)) - 1);
+}
+
void bnxt_free_tx_rings(struct bnxt *bp);
int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 3/8] net/bnxt: compute and store scattered Rx status
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 1/8] net/bnxt: update release notes for bnxt Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 2/8] net/bnxt: move Tx bd checking to header file Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 4/8] net/bnxt: implement vector mode driver Lance Richardson
` (5 subsequent siblings)
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
In preparation for a bnxt vector-mode driver, compute and store
scattered_rx status for the device when started.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---
v4:
* Moved a fix to bnxt_scattered_rx(), which is introduced in this patch,
from patch 4 into this patch. (The original version incorrectly
accounted for a possible QinQ header which was in fact already
accounted for).
drivers/net/bnxt/bnxt_ethdev.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index b0244d6d1..6295fec2a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -624,6 +624,26 @@ static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
return 0;
}
+/*
+ * Determine whether the current configuration requires support for scattered
+ * receive; return 1 if scattered receive is required and 0 if not.
+ */
+static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
+{
+ uint16_t buf_size;
+ int i;
+
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i];
+
+ buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) -
+ RTE_PKTMBUF_HEADROOM);
+ if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size)
+ return 1;
+ }
+ return 0;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -642,6 +662,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev);
+
bnxt_link_update_op(eth_dev, 1);
if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 4/8] net/bnxt: implement vector mode driver
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
` (2 preceding siblings ...)
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 3/8] net/bnxt: compute and store scattered Rx status Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
` (4 subsequent siblings)
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
Introduce SSE vector mode support for the bnxt pmd.
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
---
v2:
* Squashed with v1 patch 4 ("fix double counting VLAN tags").
* Dropped two unnecessary coding style changes from bnxt_txr.h.
v3:
* Eliminated vector mode configration flag.
* Added RTE_ARCH_X86 checks around vector mode code.
* Added release notes item for SSE vector mode.
* Added RTE_ prefix to ETHER_HDR_LEN and ETHER_CRC_LEN.
v4:
* Corrected squash that was done for v2 of this patch, the
squashed change is now in patch 3 of this patch set.
doc/guides/rel_notes/release_19_08.rst | 1 +
drivers/net/bnxt/Makefile | 3 +
drivers/net/bnxt/bnxt_ethdev.c | 95 ++++-
drivers/net/bnxt/bnxt_ring.h | 3 +-
drivers/net/bnxt/bnxt_rxq.c | 5 +
drivers/net/bnxt/bnxt_rxq.h | 4 +
drivers/net/bnxt/bnxt_rxr.h | 9 +-
drivers/net/bnxt/bnxt_rxtx_vec_sse.c | 481 +++++++++++++++++++++++++
drivers/net/bnxt/bnxt_txr.h | 5 +
drivers/net/bnxt/meson.build | 4 +
10 files changed, 602 insertions(+), 8 deletions(-)
create mode 100644 drivers/net/bnxt/bnxt_rxtx_vec_sse.c
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 2b66f41f5..7e5ca3c34 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -58,6 +58,7 @@ New Features
Updated the bnxt PMD. The major enhancements include:
* Performance optimizations in non-vector Tx path
+ * Added support for SSE vector mode
Removed Items
-------------
diff --git a/drivers/net/bnxt/Makefile b/drivers/net/bnxt/Makefile
index 8be3cb0e4..21a565063 100644
--- a/drivers/net/bnxt/Makefile
+++ b/drivers/net/bnxt/Makefile
@@ -41,6 +41,9 @@ SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_vnic.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_irq.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_util.c
SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += rte_pmd_bnxt.c
+ifeq ($(CONFIG_RTE_ARCH_X86), y)
+SRCS-$(CONFIG_RTE_LIBRTE_BNXT_PMD) += bnxt_rxtx_vec_sse.c
+endif
#
# Export include files
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index 6295fec2a..bccba445a 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -644,6 +644,67 @@ static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev)
return 0;
}
+static eth_rx_burst_t
+bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_ARCH_X86
+ /*
+ * Vector mode receive can be enabled only if scatter rx is not
+ * in use and rx offloads are limited to VLAN stripping and
+ * CRC stripping.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.rxmode.offloads &
+ ~(DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_KEEP_CRC |
+ DEV_RX_OFFLOAD_JUMBO_FRAME |
+ DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM |
+ DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_VLAN_FILTER))) {
+ PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_recv_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d rx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.rxmode.offloads);
+#endif
+ return bnxt_recv_pkts;
+}
+
+static eth_tx_burst_t
+bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev)
+{
+#ifdef RTE_ARCH_X86
+ /*
+ * Vector mode receive can be enabled only if scatter tx is not
+ * in use and tx offloads other than VLAN insertion are not
+ * in use.
+ */
+ if (!eth_dev->data->scattered_rx &&
+ !(eth_dev->data->dev_conf.txmode.offloads &
+ ~DEV_TX_OFFLOAD_VLAN_INSERT)) {
+ PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n",
+ eth_dev->data->port_id);
+ return bnxt_xmit_pkts_vec;
+ }
+ PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n",
+ eth_dev->data->port_id);
+ PMD_DRV_LOG(INFO,
+ "Port %d scatter: %d tx offload: %" PRIX64 "\n",
+ eth_dev->data->port_id,
+ eth_dev->data->scattered_rx,
+ eth_dev->data->dev_conf.txmode.offloads);
+#endif
+ return bnxt_xmit_pkts;
+}
+
static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
@@ -674,6 +735,8 @@ static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev)
if (rc)
goto error;
+ eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev);
+ eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev);
bp->flags |= BNXT_FLAG_INIT_DONE;
return 0;
@@ -1600,9 +1663,13 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
{
struct bnxt *bp = eth_dev->data->dev_private;
struct rte_eth_dev_info dev_info;
+ uint32_t new_pkt_size;
uint32_t rc = 0;
uint32_t i;
+ new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
+ VLAN_TAG_SIZE * BNXT_NUM_VLANS;
+
bnxt_dev_info_get_op(eth_dev, &dev_info);
if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) {
@@ -1611,6 +1678,23 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
return -EINVAL;
}
+#ifdef RTE_ARCH_X86
+ /*
+ * If vector-mode tx/rx is active, disallow any MTU change that would
+ * require scattered receive support.
+ */
+ if (eth_dev->data->dev_started &&
+ (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec ||
+ eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) &&
+ (new_pkt_size >
+ eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
+ PMD_DRV_LOG(ERR,
+ "MTU change would require scattered rx support. ");
+ PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n");
+ return -EINVAL;
+ }
+#endif
+
if (new_mtu > RTE_ETHER_MTU) {
bp->flags |= BNXT_FLAG_JUMBO;
bp->eth_dev->data->dev_conf.rxmode.offloads |=
@@ -1621,9 +1705,7 @@ static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu)
bp->flags &= ~BNXT_FLAG_JUMBO;
}
- eth_dev->data->dev_conf.rxmode.max_rx_pkt_len =
- new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
- VLAN_TAG_SIZE * 2;
+ eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size;
eth_dev->data->mtu = new_mtu;
PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu);
@@ -2658,9 +2740,10 @@ bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev)
RTE_PTYPE_UNKNOWN
};
- if (dev->rx_pkt_burst == bnxt_recv_pkts)
- return ptypes;
- return NULL;
+ if (!dev->rx_pkt_burst)
+ return NULL;
+
+ return ptypes;
}
static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count,
diff --git a/drivers/net/bnxt/bnxt_ring.h b/drivers/net/bnxt/bnxt_ring.h
index 1446d784f..fd3d0bd73 100644
--- a/drivers/net/bnxt/bnxt_ring.h
+++ b/drivers/net/bnxt/bnxt_ring.h
@@ -10,7 +10,8 @@
#include <rte_memory.h>
-#define RING_NEXT(ring, idx) (((idx) + 1) & (ring)->ring_mask)
+#define RING_ADV(ring, idx, n) (((idx) + (n)) & (ring)->ring_mask)
+#define RING_NEXT(ring, idx) RING_ADV(ring, idx, 1)
#define DB_IDX_MASK 0xffffff
#define DB_IDX_VALID (0x1 << 26)
diff --git a/drivers/net/bnxt/bnxt_rxq.c b/drivers/net/bnxt/bnxt_rxq.c
index f1ee9eede..2ce2ef427 100644
--- a/drivers/net/bnxt/bnxt_rxq.c
+++ b/drivers/net/bnxt/bnxt_rxq.c
@@ -355,6 +355,11 @@ int bnxt_rx_queue_setup_op(struct rte_eth_dev *eth_dev,
RTE_ETH_QUEUE_STATE_STARTED;
eth_dev->data->rx_queue_state[queue_idx] = queue_state;
rte_spinlock_init(&rxq->lock);
+
+#ifdef RTE_ARCH_X86
+ bnxt_rxq_vec_setup(rxq);
+#endif
+
out:
return rc;
}
diff --git a/drivers/net/bnxt/bnxt_rxq.h b/drivers/net/bnxt/bnxt_rxq.h
index e5d6001d3..7c6b4dec9 100644
--- a/drivers/net/bnxt/bnxt_rxq.h
+++ b/drivers/net/bnxt/bnxt_rxq.h
@@ -22,6 +22,10 @@ struct bnxt_rx_queue {
uint16_t nb_rx_hold; /* num held free RX desc */
uint16_t rx_free_thresh; /* max free RX desc to hold */
uint16_t queue_id; /* RX queue index */
+#ifdef RTE_ARCH_X86
+ uint16_t rxrearm_nb; /* number of descs to reinit. */
+ uint16_t rxrearm_start; /* next desc index to reinit. */
+#endif
uint16_t reg_idx; /* RX queue register index */
uint16_t port_id; /* Device port identifier */
uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
diff --git a/drivers/net/bnxt/bnxt_rxr.h b/drivers/net/bnxt/bnxt_rxr.h
index 3815a2199..d10cefb93 100644
--- a/drivers/net/bnxt/bnxt_rxr.h
+++ b/drivers/net/bnxt/bnxt_rxr.h
@@ -7,7 +7,7 @@
#define _BNXT_RXR_H_
#define B_RX_DB(db, prod) \
- (*(uint32_t *)db = (DB_KEY_RX | prod))
+ (*(uint32_t *)db = (DB_KEY_RX | (prod)))
#define BNXT_TPA_L4_SIZE(x) \
{ \
@@ -110,4 +110,11 @@ int bnxt_init_rx_ring_struct(struct bnxt_rx_queue *rxq, unsigned int socket_id);
int bnxt_init_one_rx_ring(struct bnxt_rx_queue *rxq);
int bnxt_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
int bnxt_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
+
+#ifdef RTE_ARCH_X86
+uint16_t bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts);
+int bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq);
+#endif
+
#endif
diff --git a/drivers/net/bnxt/bnxt_rxtx_vec_sse.c b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
new file mode 100644
index 000000000..1c32c986c
--- /dev/null
+++ b/drivers/net/bnxt/bnxt_rxtx_vec_sse.c
@@ -0,0 +1,481 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright(c) 2019 Broadcom All rights reserved. */
+
+#include <inttypes.h>
+#include <stdbool.h>
+
+#include <rte_bitmap.h>
+#include <rte_byteorder.h>
+#include <rte_malloc.h>
+#include <rte_memory.h>
+#if defined(RTE_ARCH_X86)
+#include <tmmintrin.h>
+#else
+#error "bnxt vector pmd: unsupported target."
+#endif
+
+#include "bnxt.h"
+#include "bnxt_cpr.h"
+#include "bnxt_ring.h"
+#include "bnxt_rxr.h"
+#include "bnxt_rxq.h"
+#include "hsi_struct_def_dpdk.h"
+
+#include "bnxt_txq.h"
+#include "bnxt_txr.h"
+
+/*
+ * RX Ring handling
+ */
+
+#define RTE_BNXT_MAX_RX_BURST 32
+#define RTE_BNXT_MAX_TX_BURST 32
+#define RTE_BNXT_RXQ_REARM_THRESH 32
+#define RTE_BNXT_DESCS_PER_LOOP 4
+
+static inline void
+bnxt_rxq_rearm(struct bnxt_rx_queue *rxq, struct bnxt_rx_ring_info *rxr)
+{
+ struct rx_prod_pkt_bd *rxbds = &rxr->rx_desc_ring[rxq->rxrearm_start];
+ struct bnxt_sw_rx_bd *rx_bufs = &rxr->rx_buf_ring[rxq->rxrearm_start];
+ struct rte_mbuf *mb0, *mb1;
+ int i;
+
+ const __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM, 0);
+ const __m128i addrmask = _mm_set_epi64x(UINT64_MAX, 0);
+
+ /* Pull RTE_BNXT_RXQ_REARM_THRESH more mbufs into the software ring */
+ if (rte_mempool_get_bulk(rxq->mb_pool,
+ (void *)rx_bufs,
+ RTE_BNXT_RXQ_REARM_THRESH) < 0) {
+ rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
+ RTE_BNXT_RXQ_REARM_THRESH;
+
+ return;
+ }
+
+ /* Initialize the mbufs in vector, process 2 mbufs in one loop */
+ for (i = 0; i < RTE_BNXT_RXQ_REARM_THRESH; i += 2, rx_bufs += 2) {
+ __m128i buf_addr0, buf_addr1;
+ __m128i rxbd0, rxbd1;
+
+ mb0 = rx_bufs[0].mbuf;
+ mb1 = rx_bufs[1].mbuf;
+
+ /* Load address fields from both mbufs */
+ buf_addr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
+ buf_addr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
+
+ /* Load both rx descriptors (preserving some existing fields) */
+ rxbd0 = _mm_loadu_si128((__m128i *)(rxbds + 0));
+ rxbd1 = _mm_loadu_si128((__m128i *)(rxbds + 1));
+
+ /* Add default offset to buffer address. */
+ buf_addr0 = _mm_add_epi64(buf_addr0, hdr_room);
+ buf_addr1 = _mm_add_epi64(buf_addr1, hdr_room);
+
+ /* Clear all fields except address. */
+ buf_addr0 = _mm_and_si128(buf_addr0, addrmask);
+ buf_addr1 = _mm_and_si128(buf_addr1, addrmask);
+
+ /* Clear address field in descriptor. */
+ rxbd0 = _mm_andnot_si128(addrmask, rxbd0);
+ rxbd1 = _mm_andnot_si128(addrmask, rxbd1);
+
+ /* Set address field in descriptor. */
+ rxbd0 = _mm_add_epi64(rxbd0, buf_addr0);
+ rxbd1 = _mm_add_epi64(rxbd1, buf_addr1);
+
+ /* Store descriptors to memory. */
+ _mm_store_si128((__m128i *)(rxbds++), rxbd0);
+ _mm_store_si128((__m128i *)(rxbds++), rxbd1);
+ }
+
+ rxq->rxrearm_start += RTE_BNXT_RXQ_REARM_THRESH;
+ B_RX_DB(rxr->rx_doorbell, rxq->rxrearm_start - 1);
+ if (rxq->rxrearm_start >= rxq->nb_rx_desc)
+ rxq->rxrearm_start = 0;
+
+ rxq->rxrearm_nb -= RTE_BNXT_RXQ_REARM_THRESH;
+}
+
+static uint32_t
+bnxt_parse_pkt_type(struct rx_pkt_cmpl *rxcmp, struct rx_pkt_cmpl_hi *rxcmp1)
+{
+ uint32_t l3, pkt_type = 0;
+ uint32_t t_ipcs = 0, ip6 = 0, vlan = 0;
+ uint32_t flags_type;
+
+ vlan = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN));
+ pkt_type |= vlan ? RTE_PTYPE_L2_ETHER_VLAN : RTE_PTYPE_L2_ETHER;
+
+ t_ipcs = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC));
+ ip6 = !!(rxcmp1->flags2 &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS2_IP_TYPE));
+
+ flags_type = rxcmp->flags_type &
+ rte_cpu_to_le_32(RX_PKT_CMPL_FLAGS_ITYPE_MASK);
+
+ if (!t_ipcs && !ip6)
+ l3 = RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
+ else if (!t_ipcs && ip6)
+ l3 = RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
+ else if (t_ipcs && !ip6)
+ l3 = RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
+ else
+ l3 = RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
+
+ switch (flags_type) {
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_ICMP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_ICMP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_ICMP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_TCP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_TCP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_TCP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_UDP):
+ if (!t_ipcs)
+ pkt_type |= l3 | RTE_PTYPE_L4_UDP;
+ else
+ pkt_type |= l3 | RTE_PTYPE_INNER_L4_UDP;
+ break;
+
+ case RTE_LE32(RX_PKT_CMPL_FLAGS_ITYPE_IP):
+ pkt_type |= l3;
+ break;
+ }
+
+ return pkt_type;
+}
+
+uint16_t
+bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_rx_queue *rxq = rx_queue;
+ struct bnxt_cp_ring_info *cpr = rxq->cp_ring;
+ struct bnxt_rx_ring_info *rxr = rxq->rx_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ int nb_rx_pkts = 0;
+ struct rx_pkt_cmpl *rxcmp;
+ bool evt = false;
+ const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
+ const __m128i shuf_msk =
+ _mm_set_epi8(15, 14, 13, 12, /* rss */
+ 0xFF, 0xFF, /* vlan_tci (zeroes) */
+ 3, 2, /* data_len */
+ 0xFF, 0xFF, 3, 2, /* pkt_len */
+ 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */
+
+ /* If Rx Q was stopped return */
+ if (rxq->rx_deferred_start)
+ return 0;
+
+ if (rxq->rxrearm_nb >= RTE_BNXT_RXQ_REARM_THRESH)
+ bnxt_rxq_rearm(rxq, rxr);
+
+ /* Return no more than RTE_BNXT_MAX_RX_BURST per call. */
+ nb_pkts = RTE_MIN(nb_pkts, RTE_BNXT_MAX_RX_BURST);
+
+ /* Make nb_pkts an integer multiple of RTE_BNXT_DESCS_PER_LOOP */
+ nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_BNXT_DESCS_PER_LOOP);
+
+ /* Handle RX burst request */
+ while (1) {
+ cons = RING_CMP(cpr->cp_ring_struct, raw_cons);
+
+ rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons];
+
+ if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct))
+ break;
+
+ cpr->valid = FLIP_VALID(cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ if (likely(CMP_TYPE(rxcmp) == RX_PKT_CMPL_TYPE_RX_L2)) {
+ struct rx_pkt_cmpl_hi *rxcmp1;
+ uint32_t tmp_raw_cons;
+ uint16_t cp_cons;
+ struct rte_mbuf *mbuf;
+ __m128i mm_rxcmp, pkt_mb;
+
+ tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
+ cp_cons = RING_CMP(cpr->cp_ring_struct, tmp_raw_cons);
+ rxcmp1 = (struct rx_pkt_cmpl_hi *)
+ &cpr->cp_desc_ring[cp_cons];
+
+ if (!CMP_VALID(rxcmp1, tmp_raw_cons,
+ cpr->cp_ring_struct))
+ break;
+
+ raw_cons = tmp_raw_cons;
+ cons = rxcmp->opaque;
+
+ mbuf = rxr->rx_buf_ring[cons].mbuf;
+ rte_prefetch0(mbuf);
+ rxr->rx_buf_ring[cons].mbuf = NULL;
+
+ cpr->valid = FLIP_VALID(cp_cons,
+ cpr->cp_ring_struct->ring_mask,
+ cpr->valid);
+
+ /* Set constant fields from mbuf initializer. */
+ _mm_store_si128((__m128i *)&mbuf->rearm_data,
+ mbuf_init);
+
+ /* Set mbuf pkt_len, data_len, and rss_hash fields. */
+ mm_rxcmp = _mm_load_si128((__m128i *)rxcmp);
+ pkt_mb = _mm_shuffle_epi8(mm_rxcmp, shuf_msk);
+ _mm_storeu_si128((void *)&mbuf->rx_descriptor_fields1,
+ pkt_mb);
+
+ rte_compiler_barrier();
+
+ if (rxcmp->flags_type & RX_PKT_CMPL_FLAGS_RSS_VALID)
+ mbuf->ol_flags |= PKT_RX_RSS_HASH;
+
+ if (rxcmp1->flags2 &
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN) {
+ mbuf->vlan_tci = rxcmp1->metadata &
+ (RX_PKT_CMPL_METADATA_VID_MASK |
+ RX_PKT_CMPL_METADATA_DE |
+ RX_PKT_CMPL_METADATA_PRI_MASK);
+ mbuf->ol_flags |= PKT_RX_VLAN;
+ }
+
+ mbuf->packet_type = bnxt_parse_pkt_type(rxcmp, rxcmp1);
+
+ rx_pkts[nb_rx_pkts++] = mbuf;
+ } else {
+ evt =
+ bnxt_event_hwrm_resp_handler(rxq->bp,
+ (struct cmpl_base *)rxcmp);
+ }
+
+ raw_cons = NEXT_RAW_CMP(raw_cons);
+ if (nb_rx_pkts == nb_pkts || evt)
+ break;
+ }
+ rxr->rx_prod = RING_ADV(rxr->rx_ring_struct, rxr->rx_prod, nb_rx_pkts);
+
+ rxq->rxrearm_nb += nb_rx_pkts;
+ cpr->cp_raw_cons = raw_cons;
+ if (nb_rx_pkts || evt)
+ B_CP_DIS_DB(cpr, cpr->cp_raw_cons);
+
+ return nb_rx_pkts;
+}
+
+static inline void bnxt_next_cmpl(struct bnxt_cp_ring_info *cpr, uint32_t *idx,
+ bool *v, uint32_t inc)
+{
+ *idx += inc;
+ if (unlikely(*idx == cpr->cp_ring_struct->ring_size)) {
+ *v = !*v;
+ *idx = 0;
+ }
+}
+
+static void
+bnxt_tx_cmp_vec(struct bnxt_tx_queue *txq, int nr_pkts)
+{
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ struct rte_mbuf **free = txq->free;
+ uint16_t cons = txr->tx_cons;
+ unsigned int blk = 0;
+
+ while (nr_pkts--) {
+ struct bnxt_sw_tx_bd *tx_buf;
+ struct rte_mbuf *mbuf;
+
+ tx_buf = &txr->tx_buf_ring[cons];
+ cons = RING_NEXT(txr->tx_ring_struct, cons);
+ mbuf = rte_pktmbuf_prefree_seg(tx_buf->mbuf);
+ tx_buf->mbuf = NULL;
+
+ if (blk && mbuf->pool != free[0]->pool) {
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+ blk = 0;
+ }
+ free[blk++] = mbuf;
+ }
+ if (blk)
+ rte_mempool_put_bulk(free[0]->pool, (void **)free, blk);
+
+ txr->tx_cons = cons;
+}
+
+static void
+bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq)
+{
+ struct bnxt_cp_ring_info *cpr = txq->cp_ring;
+ uint32_t raw_cons = cpr->cp_raw_cons;
+ uint32_t cons;
+ uint32_t nb_tx_pkts = 0;
+ struct tx_cmpl *txcmp;
+ struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring;
+ struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct;
+ uint32_t ring_mask = cp_ring_struct->ring_mask;
+
+ do {
+ cons = RING_CMPL(ring_mask, raw_cons);
+ txcmp = (struct tx_cmpl *)&cp_desc_ring[cons];
+
+ if (!CMPL_VALID(txcmp, cpr->valid))
+ break;
+ bnxt_next_cmpl(cpr, &cons, &cpr->valid, 1);
+ rte_prefetch0(&cp_desc_ring[cons]);
+
+ if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2))
+ nb_tx_pkts += txcmp->opaque;
+ else
+ RTE_LOG_DP(ERR, PMD,
+ "Unhandled CMP type %02x\n",
+ CMP_TYPE(txcmp));
+ raw_cons = cons;
+ } while (nb_tx_pkts < ring_mask);
+
+ if (nb_tx_pkts) {
+ bnxt_tx_cmp_vec(txq, nb_tx_pkts);
+ cpr->cp_raw_cons = raw_cons;
+ B_CP_DB(cpr, raw_cons, ring_mask);
+ }
+}
+
+#define TX_BD_FLAGS_CMPL ((1 << TX_BD_LONG_FLAGS_BD_CNT_SFT) | \
+ TX_BD_SHORT_FLAGS_COAL_NOW | \
+ TX_BD_SHORT_TYPE_TX_BD_SHORT | \
+ TX_BD_LONG_FLAGS_PACKET_END)
+
+#define TX_BD_FLAGS_NOCMPL (TX_BD_FLAGS_CMPL | TX_BD_LONG_FLAGS_NO_CMPL)
+
+static inline uint32_t
+bnxt_xmit_flags_len(uint16_t len, uint16_t flags)
+{
+ switch (len >> 9) {
+ case 0:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT512;
+ case 1:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT1K;
+ case 2:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ case 3:
+ return flags | TX_BD_LONG_FLAGS_LHINT_LT2K;
+ default:
+ return flags | TX_BD_LONG_FLAGS_LHINT_GTE2K;
+ }
+}
+
+static uint16_t
+bnxt_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ struct bnxt_tx_queue *txq = tx_queue;
+ struct bnxt_tx_ring_info *txr = txq->tx_ring;
+ uint16_t prod = txr->tx_prod;
+ struct rte_mbuf *tx_mbuf;
+ struct tx_bd_long *txbd = NULL;
+ struct bnxt_sw_tx_bd *tx_buf;
+ uint16_t to_send;
+
+ nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq));
+
+ if (unlikely(nb_pkts == 0))
+ return 0;
+
+ /* Handle TX burst request */
+ to_send = nb_pkts;
+ while (to_send) {
+ tx_mbuf = *tx_pkts++;
+ rte_prefetch0(tx_mbuf);
+
+ tx_buf = &txr->tx_buf_ring[prod];
+ tx_buf->mbuf = tx_mbuf;
+ tx_buf->nr_bds = 1;
+
+ txbd = &txr->tx_desc_ring[prod];
+ txbd->address = tx_mbuf->buf_iova + tx_mbuf->data_off;
+ txbd->len = tx_mbuf->data_len;
+ txbd->flags_type = bnxt_xmit_flags_len(tx_mbuf->data_len,
+ TX_BD_FLAGS_NOCMPL);
+ prod = RING_NEXT(txr->tx_ring_struct, prod);
+ to_send--;
+ }
+
+ /* Request a completion for last packet in burst */
+ if (txbd) {
+ txbd->opaque = nb_pkts;
+ txbd->flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL;
+ }
+
+ rte_compiler_barrier();
+ B_TX_DB(txr->tx_doorbell, prod);
+
+ txr->tx_prod = prod;
+
+ return nb_pkts;
+}
+
+uint16_t
+bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts)
+{
+ int nb_sent = 0;
+ struct bnxt_tx_queue *txq = tx_queue;
+
+ /* Tx queue was stopped; wait for it to be restarted */
+ if (unlikely(txq->tx_deferred_start)) {
+ PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n");
+ return 0;
+ }
+
+ /* Handle TX completions */
+ if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh)
+ bnxt_handle_tx_cp_vec(txq);
+
+ while (nb_pkts) {
+ uint16_t ret, num;
+
+ num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST);
+ ret = bnxt_xmit_fixed_burst_vec(tx_queue,
+ &tx_pkts[nb_sent],
+ num);
+ nb_sent += ret;
+ nb_pkts -= ret;
+ if (ret < num)
+ break;
+ }
+
+ return nb_sent;
+}
+
+int __attribute__((cold))
+bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq)
+{
+ uintptr_t p;
+ struct rte_mbuf mb_def = { .buf_addr = 0 }; /* zeroed mbuf */
+
+ mb_def.nb_segs = 1;
+ mb_def.data_off = RTE_PKTMBUF_HEADROOM;
+ mb_def.port = rxq->port_id;
+ rte_mbuf_refcnt_set(&mb_def, 1);
+
+ /* prevent compiler reordering: rearm_data covers previous fields */
+ rte_compiler_barrier();
+ p = (uintptr_t)&mb_def.rearm_data;
+ rxq->mbuf_initializer = *(uint64_t *)p;
+ rxq->rxrearm_nb = 0;
+ rxq->rxrearm_start = 0;
+ return 0;
+}
diff --git a/drivers/net/bnxt/bnxt_txr.h b/drivers/net/bnxt/bnxt_txr.h
index 13ca04676..58678a1c8 100644
--- a/drivers/net/bnxt/bnxt_txr.h
+++ b/drivers/net/bnxt/bnxt_txr.h
@@ -57,6 +57,11 @@ int bnxt_init_one_tx_ring(struct bnxt_tx_queue *txq);
int bnxt_init_tx_ring_struct(struct bnxt_tx_queue *txq, unsigned int socket_id);
uint16_t bnxt_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
uint16_t nb_pkts);
+#ifdef RTE_ARCH_X86
+uint16_t bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t nb_pkts);
+#endif
+
int bnxt_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
int bnxt_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
diff --git a/drivers/net/bnxt/meson.build b/drivers/net/bnxt/meson.build
index e130f2712..4dda28f5b 100644
--- a/drivers/net/bnxt/meson.build
+++ b/drivers/net/bnxt/meson.build
@@ -18,3 +18,7 @@ sources = files('bnxt_cpr.c',
'bnxt_util.c',
'bnxt_vnic.c',
'rte_pmd_bnxt.c')
+
+if arch_subdir == 'x86'
+ sources += files('bnxt_rxtx_vec_sse.c')
+endif
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 5/8] net/bnxt: fix RSS RETA indirection table ops
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
` (3 preceding siblings ...)
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 4/8] net/bnxt: implement vector mode driver Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
` (3 subsequent siblings)
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor,
Lance Richardson, stable
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
We are trying to update the indirection table for all the VNICs.
We should update the table only for the default vnic0.
Fix the reta update function to only update table entries that are
selected by the update mask. Translate queue number to firmware
group ID when updating an entry.
Fix reta query op to only return table entries as identfied by the
provided mask. Translate firmware group IDs to queue numbers.
Removed extraneous code from bnxt_reta_query_op().
Fixes: d819382543f3 ("net/bnxt: add RSS redirection table operations")
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Rahul Gupta <rahul.gupta@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Cc: stable@dpdk.org
---
v3:
* Squashed three RSS RETA fix commits into one.
drivers/net/bnxt/bnxt_ethdev.c | 92 +++++++++++++++++++++++++---------
drivers/net/bnxt/bnxt_hwrm.c | 1 +
2 files changed, 70 insertions(+), 23 deletions(-)
diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c
index bccba445a..30dff72a6 100644
--- a/drivers/net/bnxt/bnxt_ethdev.c
+++ b/drivers/net/bnxt/bnxt_ethdev.c
@@ -618,12 +618,6 @@ static void bnxt_print_link_info(struct rte_eth_dev *eth_dev)
eth_dev->data->port_id);
}
-static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev)
-{
- bnxt_print_link_info(eth_dev);
- return 0;
-}
-
/*
* Determine whether the current configuration requires support for scattered
* receive; return 1 if scattered receive is required and 0 if not.
@@ -977,30 +971,72 @@ static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev)
bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL);
}
+/* Return bnxt_rx_queue pointer corresponding to a given rxq. */
+static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid)
+{
+ if (qid >= bp->rx_nr_rings)
+ return NULL;
+
+ return bp->eth_dev->data->rx_queues[qid];
+}
+
+/* Return rxq corresponding to a given rss table ring/group ID. */
+static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr)
+{
+ unsigned int i;
+
+ for (i = 0; i < bp->rx_nr_rings; i++) {
+ if (bp->grp_info[i].fw_grp_id == fwr)
+ return i;
+ }
+
+ return INVALID_HW_RING_ID;
+}
+
static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev,
struct rte_eth_rss_reta_entry64 *reta_conf,
uint16_t reta_size)
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf;
- struct bnxt_vnic_info *vnic;
+ struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft;
int i;
+ if (!vnic->rss_table)
+ return -EINVAL;
+
if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG))
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* Update the RSS VNIC(s) */
- for (i = 0; i < bp->max_vnics; i++) {
- vnic = &bp->vnic_info[i];
- memcpy(vnic->rss_table, reta_conf, reta_size);
- bnxt_hwrm_vnic_rss_cfg(bp, vnic);
+
+ for (i = 0; i < reta_size; i++) {
+ struct bnxt_rx_queue *rxq;
+
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (!(reta_conf[idx].mask & (1ULL << sft)))
+ continue;
+
+ rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]);
+ if (!rxq) {
+ PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n");
+ return -EINVAL;
+ }
+
+ vnic->rss_table[i] =
+ vnic->fw_grp_ids[reta_conf[idx].reta[sft]];
}
+
+ bnxt_hwrm_vnic_rss_cfg(bp, vnic);
return 0;
}
@@ -1010,8 +1046,8 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
{
struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private;
struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
- struct rte_intr_handle *intr_handle
- = &bp->pdev->intr_handle;
+ uint16_t tbl_size = HW_HASH_INDEX_SIZE;
+ uint16_t idx, sft, i;
/* Retrieve from the default VNIC */
if (!vnic)
@@ -1019,18 +1055,28 @@ static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev,
if (!vnic->rss_table)
return -EINVAL;
- if (reta_size != HW_HASH_INDEX_SIZE) {
+ if (reta_size != tbl_size) {
PMD_DRV_LOG(ERR, "The configured hash table lookup size "
"(%d) must equal the size supported by the hardware "
- "(%d)\n", reta_size, HW_HASH_INDEX_SIZE);
+ "(%d)\n", reta_size, tbl_size);
return -EINVAL;
}
- /* EW - need to revisit here copying from uint64_t to uint16_t */
- memcpy(reta_conf, vnic->rss_table, reta_size);
- if (rte_intr_allow_others(intr_handle)) {
- if (eth_dev->data->dev_conf.intr_conf.lsc != 0)
- bnxt_dev_lsc_intr_setup(eth_dev);
+ for (idx = 0, i = 0; i < reta_size; i++) {
+ idx = i / RTE_RETA_GROUP_SIZE;
+ sft = i % RTE_RETA_GROUP_SIZE;
+
+ if (reta_conf[idx].mask & (1ULL << sft)) {
+ uint16_t qid;
+
+ qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]);
+
+ if (qid == INVALID_HW_RING_ID) {
+ PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n");
+ return -EINVAL;
+ }
+ reta_conf[idx].reta[sft] = qid;
+ }
}
return 0;
diff --git a/drivers/net/bnxt/bnxt_hwrm.c b/drivers/net/bnxt/bnxt_hwrm.c
index c5aca89b2..0c6af1622 100644
--- a/drivers/net/bnxt/bnxt_hwrm.c
+++ b/drivers/net/bnxt/bnxt_hwrm.c
@@ -1607,6 +1607,7 @@ int bnxt_hwrm_vnic_rss_cfg(struct bnxt *bp,
req.hash_key_tbl_addr =
rte_cpu_to_le_64(vnic->rss_hash_key_dma_addr);
req.rss_ctx_idx = rte_cpu_to_le_16(vnic->rss_rule);
+ req.vnic_id = rte_cpu_to_le_16(vnic->fw_vnic_id);
rc = bnxt_hwrm_send_message(bp, &req, sizeof(req), BNXT_USE_CHIMP_MB);
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 6/8] net/bnxt: update HWRM API to version 1.10.0.19
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
` (4 preceding siblings ...)
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 5/8] net/bnxt: fix RSS RETA indirection table ops Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
` (2 subsequent siblings)
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.19
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3112 +++++++++++++++++++-----
1 file changed, 2514 insertions(+), 598 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index e80057936..ea9a7d40e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2018 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Limited
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -68,9 +68,9 @@ struct hwrm_resp_hdr {
/* RoCE slow path command */
#define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
/* RoCE slow path command to query CC Gen1 support. */
-#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
/* RoCE slow path command to modify CC Gen1 support. */
-#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0xcommand 0x0005)
+#define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
/* Engine CKV - The device's serial number. */
#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER UINT32_C(0x8001)
/* Engine CKV - Per-function random nonce data. */
@@ -366,6 +366,7 @@ struct cmd_nums {
#define HWRM_TUNNEL_DST_PORT_QUERY UINT32_C(0xa0)
#define HWRM_TUNNEL_DST_PORT_ALLOC UINT32_C(0xa1)
#define HWRM_TUNNEL_DST_PORT_FREE UINT32_C(0xa2)
+ #define HWRM_STAT_CTX_ENG_QUERY UINT32_C(0xaf)
#define HWRM_STAT_CTX_ALLOC UINT32_C(0xb0)
#define HWRM_STAT_CTX_FREE UINT32_C(0xb1)
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
@@ -442,6 +443,14 @@ struct cmd_nums {
#define HWRM_FW_IPC_MSG UINT32_C(0x110)
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO UINT32_C(0x111)
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE UINT32_C(0x112)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_TIMER_RESET UINT32_C(0x113)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_CFG UINT32_C(0x114)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
+ /* Experimental */
+ #define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -591,61 +600,79 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ /*
+ * This error code is only reported by firmware when the specific
+ * request is not able to process when the HOT reset in progress.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances are not capable of hot reset.
+ */
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ /*
+ * This value indicates that the HWRM response is in TLV format and
+ * should be interpreted as one or more TLVs starting with the
+ * hwrm_resp_hdr TLV. This value is not an indicatation of any error
+ * by itself, just an indicatation that the response should be parsed
+ * as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
+ */
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -705,11 +732,11 @@ struct hwrm_err_output {
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
#define HWRM_VERSION_MAJOR 1
-#define HWRM_VERSION_MINOR 9
-#define HWRM_VERSION_UPDATE 2
+#define HWRM_VERSION_MINOR 10
+#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 53
-#define HWRM_VERSION_STR "1.9.2.53"
+#define HWRM_VERSION_RSVD 19
+#define HWRM_VERSION_STR "1.10.0.19"
/****************
* hwrm_ver_get *
@@ -959,6 +986,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED \
UINT32_C(0x100)
+ /*
+ * If set to 1, firmware is capable to support flow aging.
+ * If set to 0, firmware is not capable to support flow aging.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
+ UINT32_C(0x200)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -2031,7 +2065,7 @@ struct cmpl_base {
#define CMPL_BASE_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define CMPL_BASE_TYPE_TX_L2 UINT32_C(0x0)
/*
@@ -2116,7 +2150,7 @@ struct tx_cmpl {
#define TX_CMPL_TYPE_SFT 0
/*
* TX L2 completion:
- * Completion of TX packet. Length = 16B
+ * Completion of TX packet. Length = 16B
*/
#define TX_CMPL_TYPE_TX_L2 UINT32_C(0x0)
#define TX_CMPL_TYPE_LAST TX_CMPL_TYPE_TX_L2
@@ -2408,30 +2442,31 @@ struct rx_pkt_cmpl_hi {
* inner packet and that the ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_PKT_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_PKT_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the t_ip_cs_error field indicates if there
* was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_PKT_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the t_l4_cs_error field
* indicates if there was an error.
*/
- #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_PKT_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE (UINT32_C(0x0) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_NONE \
+ (UINT32_C(0x0) << 4)
/*
* The metadata field contains the VLAN tag and TPID value.
* - metadata[11:0] contains the vlan VID value.
@@ -2439,16 +2474,70 @@ struct rx_pkt_cmpl_hi {
* - metadata[15:13] contains the vlan PRI value.
* - metadata[31:16] contains the vlan TPID value.
*/
- #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN (UINT32_C(0x1) << 4)
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN \
+ (UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_PKT_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_PKT_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_PKT_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
* This value is only valid if itype indicates a packet
* with an IP header.
*/
- #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_PKT_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_MASK UINT32_C(0xc00)
+ #define RX_PKT_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set.
+ */
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_PKT_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2511,8 +2600,14 @@ struct rx_pkt_cmpl_hi {
*/
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
(UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_PKT_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_PKT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT
+ RX_PKT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This indicates that there was an error in the IP header
* checksum.
@@ -2553,7 +2648,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_SFT 9
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 9)
@@ -2611,7 +2706,7 @@ struct rx_pkt_cmpl_hi {
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_SFT 12
/*
* No additional error occurred on the tunnel portion
- * of the packet of the packet does not have a tunnel.
+ * or the packet of the packet does not have a tunnel.
*/
#define RX_PKT_CMPL_ERRORS_PKT_ERROR_NO_ERROR \
(UINT32_C(0x0) << 12)
@@ -2854,28 +2949,33 @@ struct rx_tpa_start_cmpl_hi {
* inner packet and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_CS_CALC \
+ UINT32_C(0x1)
/*
* This indicates that the TCP, UDP or ICMP checksum was
* calculated for the inner packet and that the sum passed
* for all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC UINT32_C(0x2)
+ #define RX_TPA_START_CMPL_FLAGS2_L4_CS_CALC \
+ UINT32_C(0x2)
/*
* This indicates that the ip checksum was calculated for the
* tunnel header and that the sum passed for all segments
* included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC UINT32_C(0x4)
+ #define RX_TPA_START_CMPL_FLAGS2_T_IP_CS_CALC \
+ UINT32_C(0x4)
/*
* This indicates that the UDP checksum was
* calculated for the tunnel packet and that the sum passed for
* all segments included in the aggregation.
*/
- #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC UINT32_C(0x8)
+ #define RX_TPA_START_CMPL_FLAGS2_T_L4_CS_CALC \
+ UINT32_C(0x8)
/* This value indicates what format the metadata field is. */
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK UINT32_C(0xf0)
- #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_MASK \
+ UINT32_C(0xf0)
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_SFT 4
/* No metadata informtaion. Value is zero. */
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_NONE \
(UINT32_C(0x0) << 4)
@@ -2888,13 +2988,71 @@ struct rx_tpa_start_cmpl_hi {
*/
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN \
(UINT32_C(0x1) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field
+ * contains the lower 16b of the tunnel ID value, justified
+ * to LSB
+ * - VXLAN = VNI[23:0] -> VXLAN Network ID
+ * - Geneve (NGE) = VNI[23:0] a-> Virtual Network Identifier.
+ * - NVGRE = TNI[23:0] -> Tenant Network ID
+ * - GRE = KEY[31:0 -> key fieled with bit mask. zero if K = 0
+ * - IPV4 = 0 (not populated)
+ * - IPV6 = Flow Label[19:0]
+ * - PPPoE = sessionID[15:0]
+ * - MPLs = Outer label[19:0]
+ * - UPAR = Selected[31:0] with bit mask
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_TUNNEL_ID \
+ (UINT32_C(0x2) << 4)
+ /*
+ * if ext_meta_format is equal to 1, metadata field contains
+ * 16b metadata from the prepended header (chdr_data).
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_CHDR_DATA \
+ (UINT32_C(0x3) << 4)
+ /*
+ * If ext_meta_format is equal to 1, the metadata field contains
+ * the outer_l3_offset, inner_l2_offset, inner_l3_offset and
+ * inner_l4_size.
+ * - metadata[8:0] contains the outer_l3_offset.
+ * - metadata[17:9] contains the inner_l2_offset.
+ * - metadata[26:18] contains the inner_l3_offset.
+ * - metadata[31:27] contains the inner_l4_size.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET \
+ (UINT32_C(0x4) << 4)
#define RX_TPA_START_CMPL_FLAGS2_META_FORMAT_LAST \
- RX_TPA_START_CMPL_FLAGS2_META_FORMAT_VLAN
+ RX_TPA_START_CMPL_FLAGS2_META_FORMAT_HDR_OFFSET
/*
* This field indicates the IP type for the inner-most IP header.
* A value of '0' indicates IPv4. A value of '1' indicates IPv6.
*/
- #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE UINT32_C(0x100)
+ #define RX_TPA_START_CMPL_FLAGS2_IP_TYPE \
+ UINT32_C(0x100)
+ /*
+ * This indicates that the complete 1's complement checksum was
+ * calculated for the packet.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_CALC \
+ UINT32_C(0x200)
+ /*
+ * The combination of this value and meta_format indicated what
+ * format the metadata field is.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_MASK \
+ UINT32_C(0xc00)
+ #define RX_TPA_START_CMPL_FLAGS2_EXT_META_FORMAT_SFT 10
+ /*
+ * This value is the complete 1's complement checksum calculated from
+ * the start of the outer L3 header to the end of the packet (not
+ * including the ethernet crc). It is valid when the
+ * 'complete_checksum_calc' flag is set. For TPA Start completions,
+ * the complete checksum is calculated for the first packet in the
+ * aggregation only.
+ */
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_MASK \
+ UINT32_C(0xffff0000)
+ #define RX_TPA_START_CMPL_FLAGS2_COMPLETE_CHECKSUM_SFT 16
/*
* This is data from the CFA block as indicated by the meta_format
* field.
@@ -2911,13 +3069,41 @@ struct rx_tpa_start_cmpl_hi {
/* When meta_format=1, this value is the VLAN TPID. */
#define RX_TPA_START_CMPL_METADATA_TPID_MASK UINT32_C(0xffff0000)
#define RX_TPA_START_CMPL_METADATA_TPID_SFT 16
- uint16_t v2;
+ uint16_t errors_v2;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_V2 UINT32_C(0x1)
+ #define RX_TPA_START_CMPL_ERRORS_MASK \
+ UINT32_C(0xfffe)
+ #define RX_TPA_START_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for the packet that was found after part of the
+ * packet was already placed. The packet should be treated as
+ * invalid.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ RX_TPA_START_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/*
* This field identifies the CFA action rule that was used for this
* packet.
@@ -3034,11 +3220,11 @@ struct rx_tpa_end_cmpl {
/*
* This value indicates what the inner packet determined for the
* packet was.
- * - 2 TCP Packet
- * Indicates that the packet was IP and TCP. This indicates
- * that the ip_cs field is valid and that the tcp_udp_cs
- * field is valid and contains the TCP checksum.
- * This also indicates that the payload_offset field is valid.
+ * - 2 TCP Packet
+ * Indicates that the packet was IP and TCP. This indicates
+ * that the ip_cs field is valid and that the tcp_udp_cs
+ * field is valid and contains the TCP checksum.
+ * This also indicates that the payload_offset field is valid.
*/
#define RX_TPA_END_CMPL_FLAGS_ITYPE_MASK UINT32_C(0xf000)
#define RX_TPA_END_CMPL_FLAGS_ITYPE_SFT 12
@@ -3117,13 +3303,28 @@ struct rx_tpa_end_cmpl_hi {
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
- uint32_t tpa_dup_acks;
+ uint16_t tpa_dup_acks;
/*
* This value is the number of duplicate ACKs that have been
* received as part of the TPA operation.
*/
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_MASK UINT32_C(0xf)
#define RX_TPA_END_CMPL_TPA_DUP_ACKS_SFT 0
+ /*
+ * This value indicated the offset in bytes from the beginning of
+ * the packet where the inner payload starts. This value is valid
+ * for TCP, UDP, FCoE and RoCE packets
+ */
+ uint8_t payload_offset;
+ /*
+ * The value is the total number of aggregation buffers that were
+ * used in the TPA operation. All TPA aggregation buffer completions
+ * preceed the TPA End completion. If the value is zero, then the
+ * aggregation is completely contained in the buffer space provided
+ * in the aggregation start completion.
+ * Note that the field is simply provided as a cross check.
+ */
+ uint8_t tpa_agg_bufs;
/*
* This value is the valid when TPA completion is active. It
* indicates the length of the longest segment of the TPA operation
@@ -3154,6 +3355,9 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
/*
* This error occurs when there is a fatal HW problem in
* the chip only. It indicates that there were not
@@ -3162,6 +3366,12 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP \
(UINT32_C(0x2) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
/*
* This error occurs when TPA block was not configured to
* reserve adequate BDs for TPA operations on this RX
@@ -3174,8 +3384,14 @@ struct rx_tpa_end_cmpl_hi {
*/
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR \
(UINT32_C(0x4) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
#define RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_LAST \
- RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_RSV_ERROR
+ RX_TPA_END_CMPL_ERRORS_BUFFER_ERROR_FLUSH
/* unused5 is 16 b */
uint16_t unused_4;
/*
@@ -3239,15 +3455,23 @@ struct eject_cmpl {
* records. Odd values indicate 32B
* records.
*/
- #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
- #define EJECT_CMPL_TYPE_SFT 0
+ #define EJECT_CMPL_TYPE_MASK UINT32_C(0x3f)
+ #define EJECT_CMPL_TYPE_SFT 0
/*
* Statistics Ejection Completion:
* Completion of statistics data ejection buffer.
* Length = 16B
*/
- #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
- #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_TYPE_STAT_EJECT UINT32_C(0x1a)
+ #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT
+ #define EJECT_CMPL_FLAGS_MASK UINT32_C(0xffc0)
+ #define EJECT_CMPL_FLAGS_SFT 6
+ /*
+ * When this bit is '1', it indicates a packet that has an
+ * error of some type. Type of error is indicated in
+ * error_flags.
+ */
+ #define EJECT_CMPL_FLAGS_ERROR UINT32_C(0x40)
/*
* This is the length of the statistics data stored in this
* buffer.
@@ -3258,13 +3482,47 @@ struct eject_cmpl {
* buffer corresponds to.
*/
uint32_t opaque;
- uint32_t v;
+ uint16_t v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_V UINT32_C(0x1)
+ #define EJECT_CMPL_ERRORS_MASK UINT32_C(0xfffe)
+ #define EJECT_CMPL_ERRORS_SFT 1
+ /*
+ * This error indicates that there was some sort of problem with
+ * the BDs for statistics ejection. The statistics ejection should
+ * be treated as invalid
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK UINT32_C(0xe)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT 1
+ /* No buffer error */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER \
+ (UINT32_C(0x0) << 1)
+ /*
+ * Did Not Fit:
+ * Statistics did not fit into aggregation buffer provided.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT \
+ (UINT32_C(0x1) << 1)
+ /*
+ * Bad Format:
+ * BDs were not formatted correctly.
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT \
+ (UINT32_C(0x3) << 1)
+ /*
+ * Flush:
+ * There was a bad_format error on the previous operation
+ */
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH \
+ (UINT32_C(0x5) << 1)
+ #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST \
+ EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
+ /* reserved16 is 16 b */
+ uint16_t reserved16;
/* unused3 is 32 b */
uint32_t unused_2;
} __attribute__((packed));
@@ -3470,6 +3728,24 @@ struct hwrm_async_event_cmpl {
/* Default VNIC Configuration Change */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE \
UINT32_C(0x35)
+ /* HW flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ /*
+ * A debug notification being posted to the driver. These
+ * notifications are purely for diagnostic purpose and should not be
+ * used for functional purpose. The driver is not supposed to act
+ * on these messages except to log/record it.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
+ UINT32_C(0x37)
+ /*
+ * A trace log message. This contains firmware trace logs string
+ * embedded in the asynchronous message. This is an experimental
+ * event, not meant for production use at this time.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
/* HWRM Error */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR \
UINT32_C(0xff)
@@ -4111,9 +4387,19 @@ struct hwrm_async_event_cmpl_reset_notify {
/* opaque is 7 b */
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK UINT32_C(0xfe)
#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
- /* 8-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 8-lsb timestamp (100-msec resolution)
+ * The Minimum time required for the Firmware readiness after sending this
+ * notification to the driver instances.
+ */
uint8_t timestamp_lo;
- /* 16-lsb timestamp from POR (100-msec resolution) */
+ /*
+ * 16-lsb timestamp (100-msec resolution)
+ * The Maximum Firmware Reset bail out value in the order of 100
+ * milli seconds. The driver instances will use this value to re-initiate the
+ * registration process again if the core firmware didn’t set the ready
+ * state bit.
+ */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
@@ -4829,6 +5115,73 @@ struct hwrm_async_event_cmpl_default_vnic_change {
10
} __attribute__((packed));
+/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
+struct hwrm_async_event_cmpl_hw_flow_aged {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of a hw flow aged */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED \
+ UINT32_C(0x36)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates flow ID this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK \
+ UINT32_C(0x7fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT \
+ 0
+ /* Indicates flow direction this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x80000000)
+ /*
+ * If this bit set to 0, then it indicates that the aged
+ * event was rx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 31)
+ /*
+ * If this bit is set to 1, then it indicates that the aged
+ * event was tx flow.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
struct hwrm_async_event_cmpl_hwrm_error {
uint16_t type;
@@ -5682,7 +6035,7 @@ struct hwrm_func_qcaps_output {
/*
* If the query is for a VF, then this flag shall be ignored,
* If this query is for a PF and this flag is set to 1,
- * then the PF has the capability to administer another PF.
+ * then the PF has the administrative privilege to configure another PF
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ADMIN_PF_SUPPORTED \
UINT32_C(0x40000)
@@ -5700,6 +6053,19 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_WCB_PUSH_MODE \
UINT32_C(0x100000)
+ /*
+ * If 1, then FW has capability to allocate TX rings dynamically
+ * in ring alloc even if PF reserved pool is zero.
+ * This bit will be used only for PFs.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x200000)
+ /*
+ * When this bit is '1', it indicates that core firmware is
+ * capable of Hot Reset.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
+ UINT32_C(0x400000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5864,7 +6230,7 @@ struct hwrm_func_qcfg_input {
uint8_t unused_0[6];
} __attribute__((packed));
-/* hwrm_func_qcfg_output (size:640b/80B) */
+/* hwrm_func_qcfg_output (size:704b/88B) */
struct hwrm_func_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -5951,6 +6317,13 @@ struct hwrm_func_qcfg_output {
*/
#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_TRUSTED_VF \
UINT32_C(0x40)
+ /*
+ * If set to 1, then secure mode is enabled for this function or device.
+ * If set to 0, then secure mode is disabled (or normal mode) for this
+ * function or device.
+ */
+ #define HWRM_FUNC_QCFG_OUTPUT_FLAGS_SECURE_MODE_ENABLED \
+ UINT32_C(0x80)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -5995,7 +6368,8 @@ struct hwrm_func_qcfg_output {
uint16_t alloc_vnics;
/*
* The maximum transmission unit of the function.
- * For rings allocated on this function, this default
+ * If the reported mtu value is non-zero then it will used for the
+ * rings allocated on this function. otherwise the default
* value is used if ring MTU is not specified.
*/
uint16_t mtu;
@@ -6222,7 +6596,27 @@ struct hwrm_func_qcfg_output {
* reserved for itself (since the NQs must be contiguous in HW).
*/
uint16_t alloc_msix;
- uint8_t unused_2[5];
+ /*
+ * The number of registered VF’s associated with the PF. This field
+ * should be ignored when the request received on the VF interface.
+ * This field will be updated on the PF interface to initiate
+ * the unregister request on PF in the HOT Reset Process.
+ */
+ uint16_t registered_vfs;
+ uint8_t unused_1[3];
+ /*
+ * For backward compatibility this field must be set to 1.
+ * Older drivers might look for this field to be 1 before
+ * processing the message.
+ */
+ uint8_t always_1;
+ /*
+ * This GRC address location is used by the Host driver interfaces to poll
+ * the adapter ready state to re-initiate the registration process again
+ * after receiving the RESET Notify event.
+ */
+ uint32_t reset_addr_poll;
+ uint8_t unused_2[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -6424,6 +6818,13 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
+ /*
+ * When this bit it set, even if PF reserved pool size is zero,
+ * FW will allow driver to create TX rings in ring alloc,
+ * by reserving TX ring, S3 node dynamically.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
+ UINT32_C(0x400000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7181,6 +7582,17 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FLOW_HANDLE_64BIT_MODE \
UINT32_C(0x8)
+ /*
+ * When this bit is '1', the function is indicating support of
+ * Hot Reset. The driver interface will destroy the resources,
+ * unregister the function and register again up on receiving
+ * the RESET_NOTIFY Async notification from the core firmware.
+ * The core firmware will this use flag and trigger the Hot Reset
+ * process only if all the registered driver instances are capable
+ * of this support.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
+ UINT32_C(0x10)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10774,6 +11186,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_FORCE_LINK_SPEED_LAST \
@@ -10878,6 +11292,8 @@ struct hwrm_port_phy_cfg_input {
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_LAST \
@@ -10930,6 +11346,9 @@ struct hwrm_port_phy_cfg_input {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_CFG_INPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* This value controls the wirespeed feature. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11159,6 +11578,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_10MB UINT32_C(0xffff)
#define HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_LAST \
@@ -11238,6 +11659,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_200GB \
+ UINT32_C(0x4000)
/*
* Current setting of forced link speed.
* When the link speed is not being forced, this
@@ -11267,6 +11691,9 @@ struct hwrm_port_phy_qcfg_output {
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_100GB \
UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_200GB \
+ UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_FORCE_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11353,6 +11780,8 @@ struct hwrm_port_phy_qcfg_output {
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_50GB UINT32_C(0x1f4)
/* 100Gb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_100GB UINT32_C(0x3e8)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_200GB UINT32_C(0x7d0)
/* 10Mb link speed */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_10MB \
UINT32_C(0xffff)
@@ -11408,6 +11837,9 @@ struct hwrm_port_phy_qcfg_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_LINK_SPEED_MASK_200GB \
+ UINT32_C(0x4000)
/* Current setting for wirespeed. */
uint8_t wirespeed;
/* Wirespeed feature is disabled. */
@@ -11574,8 +12006,20 @@ struct hwrm_port_phy_qcfg_output {
/* 1G_baseCX */
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX \
UINT32_C(0x1b)
+ /* 100G_BASECR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASECR4 \
+ UINT32_C(0x1c)
+ /* 100G_BASESR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASESR4 \
+ UINT32_C(0x1d)
+ /* 100G_BASELR4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASELR4 \
+ UINT32_C(0x1e)
+ /* 100G_BASEER4 */
+ #define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4 \
+ UINT32_C(0x1f)
#define HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_LAST \
- HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_1G_BASECX
+ HWRM_PORT_PHY_QCFG_OUTPUT_PHY_TYPE_200G_BASEER4
/* This value represents a media type. */
uint8_t media_type;
/* Unknown */
@@ -21081,6 +21525,15 @@ struct hwrm_cfa_l2_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -21887,6 +22340,15 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22107,6 +22569,12 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22212,6 +22680,12 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22312,6 +22786,12 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -22517,8 +22997,14 @@ struct hwrm_cfa_encap_record_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -22872,6 +23358,15 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23381,6 +23876,15 @@ struct hwrm_cfa_em_flow_alloc_input {
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
@@ -23586,13 +24090,13 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_profile_alloc *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_profile_alloc_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23620,266 +24124,1670 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- /*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
- */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115 \
UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_METER_TYPE_RFC4115
/*
- * This bit must be '1' for the src_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
- UINT32_C(0x4)
+ uint16_t reserved1;
/*
- * This bit must be '1' for the dst_macaddr field to be
- * configured.
+ * This field is reserved for the future use.
+ * It shall be set to 0.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
- UINT32_C(0x8)
- /*
+ uint32_t reserved2;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_ALLOC_OUTPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_meter_profile_free *
+ *******************************/
+
+
+/* hwrm_cfa_meter_profile_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_profile_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_FREE_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_meter_profile_cfg *
+ ******************************/
+
+
+/* hwrm_cfa_meter_profile_cfg_input (size:320b/40B) */
+struct hwrm_cfa_meter_profile_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_FLAGS_PATH_RX
+ /* The meter algorithm type. */
+ uint8_t meter_type;
+ /* RFC 2697 (srTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2697 \
+ UINT32_C(0x0)
+ /* RFC 2698 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC2698 \
+ UINT32_C(0x1)
+ /* RFC 4115 (trTCM) */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115 \
+ UINT32_C(0x2)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_TYPE_RFC4115
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This field is reserved for the future use.
+ * It shall be set to 0.
+ */
+ uint32_t reserved;
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t commit_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t commit_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID
+ /* A meter rate specified in bytes-per-second. */
+ uint32_t excess_peak_rate;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ /* A meter burst size specified in bytes. */
+ uint32_t excess_peak_burst;
+ /* The bandwidth value. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_MASK \
+ UINT32_C(0xfffffff)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_SFT \
+ 0
+ /* The granularity of the value (bits or bytes). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE \
+ UINT32_C(0x10000000)
+ /* Value is in bits. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BITS \
+ (UINT32_C(0x0) << 28)
+ /* Value is in bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES \
+ (UINT32_C(0x1) << 28)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_SCALE_BYTES
+ /* bw_value_unit is 3 b */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MASK \
+ UINT32_C(0xe0000000)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_SFT \
+ 29
+ /* Value is in Mb or MB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_MEGA \
+ (UINT32_C(0x0) << 29)
+ /* Value is in Kb or KB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_KILO \
+ (UINT32_C(0x2) << 29)
+ /* Value is in bits or bytes. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_BASE \
+ (UINT32_C(0x4) << 29)
+ /* Value is in Gb or GB (base 10). */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_GIGA \
+ (UINT32_C(0x6) << 29)
+ /* Value is in 1/100th of a percentage of total bandwidth. */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_PERCENT1_100 \
+ (UINT32_C(0x1) << 29)
+ /* Invalid unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID \
+ (UINT32_C(0x7) << 29)
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_LAST \
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_BURST_BW_VALUE_UNIT_INVALID
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_profile_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_profile_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************************
+ * hwrm_cfa_meter_instance_alloc *
+ *********************************/
+
+
+/* hwrm_cfa_meter_instance_alloc_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH \
+ UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter profile in CFA. */
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_alloc_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
+
+
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t flags;
+ /*
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
+ /*
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the src_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_MACADDR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the dst_macaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
+ UINT32_C(0x8)
+ /*
* This bit must be '1' for the ovlan_vid field to be
* configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
- UINT32_C(0x10)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_OVLAN_VID \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the t_ovlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ UINT32_C(0x40)
+ /*
+ * This bit must be '1' for the t_ivlan_vid field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ UINT32_C(0x80)
+ /*
+ * This bit must be '1' for the ethertype field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the src_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ UINT32_C(0x200)
+ /*
+ * This bit must be '1' for the dst_ipaddr field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ UINT32_C(0x400)
+ /*
+ * This bit must be '1' for the ipaddr_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
+ UINT32_C(0x800)
+ /*
+ * This bit must be '1' for the ip_protocol field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
+ UINT32_C(0x1000)
+ /*
+ * This bit must be '1' for the src_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
+ UINT32_C(0x2000)
+ /*
+ * This bit must be '1' for the dst_port field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
+ UINT32_C(0x4000)
+ /*
+ * This bit must be '1' for the dst_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
+ UINT32_C(0x8000)
+ /*
+ * This bit must be '1' for the mirror_vnic_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
+ UINT32_C(0x10000)
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI). Only valid with
+ * tunnel_types VXLAN, NVGRE, and Geneve.
+ * Only lower 24-bits of VNI field are used
+ * in setting up the filter.
+ */
+ uint32_t tunnel_id;
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused_0;
+ uint16_t unused_1;
+ /*
+ * This value indicates the source MAC address in
+ * the Ethernet header.
+ */
+ uint8_t src_macaddr[6];
+ uint8_t unused_2[2];
/*
- * This bit must be '1' for the ivlan_vid field to be
- * configured.
+ * This value indicates the destination MAC address in
+ * the Ethernet header.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IVLAN_VID \
- UINT32_C(0x20)
+ uint8_t dst_macaddr[6];
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the Ethernet header.
+ */
+ uint16_t ivlan_vid;
+ /*
+ * This value indicates the VLAN ID of the outer VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ovlan_vid;
+ /*
+ * This value indicates the VLAN ID of the inner VLAN tag
+ * in the tunnel Ethernet header.
+ */
+ uint16_t t_ivlan_vid;
+ /* This value indicates the ethertype in the Ethernet header. */
+ uint16_t ethertype;
+ /*
+ * This value indicates the type of IP address.
+ * 4 - IPv4
+ * 6 - IPv6
+ * All others are invalid.
+ */
+ uint8_t ip_addr_type;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
+ UINT32_C(0x0)
+ /* IPv4 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
+ UINT32_C(0x4)
+ /* IPv6 */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
+ UINT32_C(0x6)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ /*
+ * The value of protocol filed in IP header.
+ * Applies to UDP and TCP traffic.
+ * 6 - TCP
+ * 17 - UDP
+ */
+ uint8_t ip_protocol;
+ /* invalid */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
+ UINT32_C(0x0)
+ /* TCP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
+ UINT32_C(0x6)
+ /* UDP */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
+ UINT32_C(0x11)
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
+ HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
+ uint16_t unused_3;
+ uint32_t unused_4;
+ /*
+ * The value of source IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t src_ipaddr[4];
+ /*
+ * The value of destination IP address to be used in filtering.
+ * For IPv4, first four bytes represent the IP address.
+ */
+ uint32_t dst_ipaddr[4];
+ /*
+ * The value of source port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t src_port;
+ /*
+ * The value of destination port to be used in filtering.
+ * Applies to UDP and TCP traffic.
+ */
+ uint16_t dst_port;
+ /*
+ * If set, this value shall represent the
+ * Logical VNIC ID of the destination VNIC for the RX
+ * path.
+ */
+ uint16_t dst_id;
+ /*
+ * If set, this value shall represent the L2 context that matches the L2
+ * information of the decap filter.
+ */
+ uint16_t l2_ctxt_ref_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/******************************
+ * hwrm_cfa_decap_filter_free *
+ ******************************/
+
+
+/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
+struct hwrm_cfa_decap_filter_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* This value is an opaque id into CFA data structures. */
+ uint32_t decap_filter_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
+struct hwrm_cfa_decap_filter_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_alloc *
+ ***********************/
+
+
+/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
+struct hwrm_cfa_flow_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
+ UINT32_C(0x1)
+ /* num_vlan is 2 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
+ UINT32_C(0x6)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
+ /* no tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
+ (UINT32_C(0x0) << 1)
+ /* 1 tag */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
+ (UINT32_C(0x1) << 1)
+ /* 2 tags */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
+ (UINT32_C(0x2) << 1)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
+ /* Enumeration denoting the Flow Type. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
+ UINT32_C(0x38)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
+ /* L2 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
+ (UINT32_C(0x0) << 3)
+ /* IPV4 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
+ (UINT32_C(0x1) << 3)
+ /* IPV6 flow */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
+ (UINT32_C(0x2) << 3)
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
/*
- * This bit must be '1' for the t_ovlan_vid field to be
- * configured.
+ * when set to 1, indicates TX flow offload for function specified in src_fid and
+ * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
+ * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
+ * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
+ * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
+ * belong to the children VFs of the same PF to indicate VM to VM flow.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_OVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
UINT32_C(0x40)
/*
- * This bit must be '1' for the t_ivlan_vid field to be
- * configured.
+ * when set to 1, indicates RX flow offload for function specified in dst_fid and
+ * the src_fid should be set to invalid value.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_T_IVLAN_VID \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
UINT32_C(0x80)
/*
- * This bit must be '1' for the ethertype field to be
- * configured.
+ * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
+ * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
+ * This flag is only valid when the flow direction is RX.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_ETHERTYPE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
/*
- * This bit must be '1' for the src_ipaddr field to be
- * configured.
+ * Tx Flow: vf fid.
+ * Rx Flow: pf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_IPADDR \
+ uint16_t src_fid;
+ /* Tunnel handle valid when tunnel flag is set. */
+ uint32_t tunnel_handle;
+ uint16_t action_flags;
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* recycle is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /*
+ * Setting of this flag indicates drop action. If this flag is not set,
+ * then it should be considered accept action.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* meter is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* tunnel is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /* nat_src is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
+ UINT32_C(0x20)
+ /* nat_dest is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
+ UINT32_C(0x40)
+ /* nat_ipv4_address is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
+ UINT32_C(0x80)
+ /* l2_header_rewrite is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
+ UINT32_C(0x100)
+ /* ttl_decrement is 1 b */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
UINT32_C(0x200)
/*
- * This bit must be '1' for the dst_ipaddr field to be
- * configured.
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header. The type of tunnel
+ * is specified in the tunnel_type field.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_IPADDR \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
UINT32_C(0x400)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x800)
/*
- * This bit must be '1' for the ipaddr_type field to be
- * configured.
+ * Tx Flow: pf or vf fid.
+ * Rx Flow: vf fid.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IPADDR_TYPE \
- UINT32_C(0x800)
+ uint16_t dst_fid;
+ /* VLAN tpid, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci, valid when push_vlan flag is set. */
+ uint16_t l2_rewrite_vlan_tci;
+ /* Meter id, valid when meter flag is set. */
+ uint16_t act_meter_id;
+ /* Flow with the same l2 context tcam key. */
+ uint16_t ref_flow_handle;
+ /* This value sets the match value for the ethertype. */
+ uint16_t ethertype;
+ /* valid when num tags is 1 or 2. */
+ uint16_t outer_vlan_tci;
+ /* This value sets the match value for the Destination MAC address. */
+ uint16_t dmac[3];
+ /* valid when num tags is 2. */
+ uint16_t inner_vlan_tci;
+ /* This value sets the match value for the Source MAC address. */
+ uint16_t smac[3];
+ /* The bit length of destination IP address mask. */
+ uint8_t ip_dst_mask_len;
+ /* The bit length of source IP address mask. */
+ uint8_t ip_src_mask_len;
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
/*
- * This bit must be '1' for the ip_protocol field to be
- * configured.
+ * The value of source port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_IP_PROTOCOL \
- UINT32_C(0x1000)
+ uint16_t l4_src_port;
/*
- * This bit must be '1' for the src_port field to be
- * configured.
+ * The value of source port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_SRC_PORT \
- UINT32_C(0x2000)
+ uint16_t l4_src_port_mask;
/*
- * This bit must be '1' for the dst_port field to be
- * configured.
+ * The value of destination port.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_PORT \
- UINT32_C(0x4000)
+ uint16_t l4_dst_port;
/*
- * This bit must be '1' for the dst_id field to be
- * configured.
+ * The value of destination port mask.
+ * Applies to UDP and TCP traffic.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_DST_ID \
- UINT32_C(0x8000)
+ uint16_t l4_dst_port_mask;
/*
- * This bit must be '1' for the mirror_vnic_id field to be
- * configured.
+ * NAT IPv4/6 address based on address type flag.
+ * 0 values are ignored.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
- UINT32_C(0x10000)
+ uint32_t nat_ip_address[4];
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
/*
- * Tunnel identifier.
- * Virtual Network Identifier (VNI). Only valid with
- * tunnel_types VXLAN, NVGRE, and Geneve.
- * Only lower 24-bits of VNI field are used
- * in setting up the filter.
+ * The NAT source/destination port based on direction flag.
+ * Applies to UDP and TCP traffic.
+ * 0 values are ignored.
*/
- uint32_t tunnel_id;
+ uint16_t nat_port;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* The value of ip protocol. */
+ uint8_t ip_proto;
/* Tunnel Type. */
uint8_t tunnel_type;
/* Non-tunnel */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL \
UINT32_C(0x0)
/* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN \
UINT32_C(0x1)
/* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE \
UINT32_C(0x2)
/* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE \
UINT32_C(0x3)
/* IP in IP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP \
UINT32_C(0x4)
/* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE \
UINT32_C(0x5)
/* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS \
UINT32_C(0x6)
/* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_STT \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT \
UINT32_C(0x7)
/* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE \
UINT32_C(0x8)
/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \
UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
/* Any tunneled traffic */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL \
UINT32_C(0xff)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
- uint8_t unused_0;
- uint16_t unused_1;
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
+struct hwrm_cfa_flow_alloc_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[2];
/*
- * This value indicates the source MAC address in
- * the Ethernet header.
+ * This is the ID of the flow associated with this
+ * filter.
+ * This value shall be used to match and associate the
+ * flow identifier returned in completion records.
+ * A value of 0xFFFFFFFF shall indicate no flow id.
+ */
+ uint32_t flow_id;
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_free *
+ **********************/
+
+
+/* hwrm_cfa_flow_free_input (size:256b/32B) */
+struct hwrm_cfa_flow_free_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint8_t src_macaddr[6];
- uint8_t unused_2[2];
+ uint16_t cmpl_ring;
/*
- * This value indicates the destination MAC address in
- * the Ethernet header.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t dst_macaddr[6];
+ uint16_t seq_id;
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the Ethernet header.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t ovlan_vid;
+ uint16_t target_id;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the Ethernet header.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t ivlan_vid;
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_free_output (size:256b/32B) */
+struct hwrm_cfa_flow_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* packet is 64 b */
+ uint64_t packet;
+ /* byte is 64 b */
+ uint64_t byte;
+ uint8_t unused_0[7];
/*
- * This value indicates the VLAN ID of the outer VLAN tag
- * in the tunnel Ethernet header.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint16_t t_ovlan_vid;
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_flow_info *
+ **********************/
+
+
+/* hwrm_cfa_flow_info_input (size:256b/32B) */
+struct hwrm_cfa_flow_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This value indicates the VLAN ID of the inner VLAN tag
- * in the tunnel Ethernet header.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t t_ivlan_vid;
- /* This value indicates the ethertype in the Ethernet header. */
- uint16_t ethertype;
+ uint16_t cmpl_ring;
/*
- * This value indicates the type of IP address.
- * 4 - IPv4
- * 6 - IPv6
- * All others are invalid.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint8_t ip_addr_type;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_UNKNOWN \
- UINT32_C(0x0)
- /* IPv4 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV4 \
- UINT32_C(0x4)
- /* IPv6 */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6 \
- UINT32_C(0x6)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_ADDR_TYPE_IPV6
+ uint16_t seq_id;
/*
- * The value of protocol filed in IP header.
- * Applies to UDP and TCP traffic.
- * 6 - TCP
- * 17 - UDP
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint8_t ip_protocol;
- /* invalid */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UNKNOWN \
- UINT32_C(0x0)
- /* TCP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_TCP \
- UINT32_C(0x6)
- /* UDP */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP \
- UINT32_C(0x11)
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_LAST \
- HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_IP_PROTOCOL_UDP
- uint16_t unused_3;
- uint32_t unused_4;
+ uint16_t target_id;
/*
- * The value of source IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint32_t src_ipaddr[4];
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ /* Max flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_MASK \
+ UINT32_C(0xfff)
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_MAX_SFT 0
+ /* CNP flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_CNP_CNT \
+ UINT32_C(0x1000)
+ /* RoCEv1 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV1_CNT \
+ UINT32_C(0x2000)
+ /* RoCEv2 flow handle */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_ROCEV2_CNT \
+ UINT32_C(0x4000)
+ /* Direction rx = 1 */
+ #define HWRM_CFA_FLOW_INFO_INPUT_FLOW_HANDLE_DIR_RX \
+ UINT32_C(0x8000)
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_info_output (size:448b/56B) */
+struct hwrm_cfa_flow_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* flags is 8 b */
+ uint8_t flags;
+ /* profile is 8 b */
+ uint8_t profile;
+ /* src_fid is 16 b */
+ uint16_t src_fid;
+ /* dst_fid is 16 b */
+ uint16_t dst_fid;
+ /* l2_ctxt_id is 16 b */
+ uint16_t l2_ctxt_id;
+ /* em_info is 64 b */
+ uint64_t em_info;
+ /* tcam_info is 64 b */
+ uint64_t tcam_info;
+ /* vfp_tcam_info is 64 b */
+ uint64_t vfp_tcam_info;
+ /* ar_id is 16 b */
+ uint16_t ar_id;
+ /* flow_handle is 16 b */
+ uint16_t flow_handle;
+ /* tunnel_handle is 32 b */
+ uint32_t tunnel_handle;
+ /* The flow aging timer for the flow, the unit is 100 milliseconds */
+ uint16_t flow_timer;
+ uint8_t unused_0[5];
/*
- * The value of destination IP address to be used in filtering.
- * For IPv4, first four bytes represent the IP address.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- uint32_t dst_ipaddr[4];
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_cfa_flow_flush *
+ ***********************/
+
+
+/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+struct hwrm_cfa_flow_flush_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * The value of source port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- uint16_t src_port;
+ uint16_t cmpl_ring;
/*
- * The value of destination port to be used in filtering.
- * Applies to UDP and TCP traffic.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- uint16_t dst_port;
+ uint16_t seq_id;
/*
- * If set, this value shall represent the
- * Logical VNIC ID of the destination VNIC for the RX
- * path.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- uint16_t dst_id;
+ uint16_t target_id;
/*
- * If set, this value shall represent the L2 context that matches the L2
- * information of the decap filter.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- uint16_t l2_ctxt_ref_id;
+ uint64_t resp_addr;
+ uint32_t flags;
+ uint8_t unused_0[4];
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_alloc_output {
+/* hwrm_cfa_flow_flush_output (size:128b/16B) */
+struct hwrm_cfa_flow_flush_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23888,9 +25796,7 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[3];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -23901,13 +25807,13 @@ struct hwrm_cfa_decap_filter_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/******************************
- * hwrm_cfa_decap_filter_free *
- ******************************/
+/***********************
+ * hwrm_cfa_flow_stats *
+ ***********************/
-/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */
-struct hwrm_cfa_decap_filter_free_input {
+/* hwrm_cfa_flow_stats_input (size:640b/80B) */
+struct hwrm_cfa_flow_stats_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23935,13 +25841,53 @@ struct hwrm_cfa_decap_filter_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This value is an opaque id into CFA data structures. */
- uint32_t decap_filter_id;
- uint8_t unused_0[4];
+ /* Flow handle. */
+ uint16_t num_flows;
+ /* Flow handle. */
+ uint16_t flow_handle_0;
+ /* Flow handle. */
+ uint16_t flow_handle_1;
+ /* Flow handle. */
+ uint16_t flow_handle_2;
+ /* Flow handle. */
+ uint16_t flow_handle_3;
+ /* Flow handle. */
+ uint16_t flow_handle_4;
+ /* Flow handle. */
+ uint16_t flow_handle_5;
+ /* Flow handle. */
+ uint16_t flow_handle_6;
+ /* Flow handle. */
+ uint16_t flow_handle_7;
+ /* Flow handle. */
+ uint16_t flow_handle_8;
+ /* Flow handle. */
+ uint16_t flow_handle_9;
+ uint8_t unused_0[2];
+ /* Flow ID of a flow. */
+ uint32_t flow_id_0;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_1;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_2;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_3;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_4;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_5;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_6;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_7;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_8;
+ /* Flow ID of a flow. */
+ uint32_t flow_id_9;
} __attribute__((packed));
-/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */
-struct hwrm_cfa_decap_filter_free_output {
+/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
+struct hwrm_cfa_flow_stats_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -23950,6 +25896,46 @@ struct hwrm_cfa_decap_filter_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
+ /* packet_0 is 64 b */
+ uint64_t packet_0;
+ /* packet_1 is 64 b */
+ uint64_t packet_1;
+ /* packet_2 is 64 b */
+ uint64_t packet_2;
+ /* packet_3 is 64 b */
+ uint64_t packet_3;
+ /* packet_4 is 64 b */
+ uint64_t packet_4;
+ /* packet_5 is 64 b */
+ uint64_t packet_5;
+ /* packet_6 is 64 b */
+ uint64_t packet_6;
+ /* packet_7 is 64 b */
+ uint64_t packet_7;
+ /* packet_8 is 64 b */
+ uint64_t packet_8;
+ /* packet_9 is 64 b */
+ uint64_t packet_9;
+ /* byte_0 is 64 b */
+ uint64_t byte_0;
+ /* byte_1 is 64 b */
+ uint64_t byte_1;
+ /* byte_2 is 64 b */
+ uint64_t byte_2;
+ /* byte_3 is 64 b */
+ uint64_t byte_3;
+ /* byte_4 is 64 b */
+ uint64_t byte_4;
+ /* byte_5 is 64 b */
+ uint64_t byte_5;
+ /* byte_6 is 64 b */
+ uint64_t byte_6;
+ /* byte_7 is 64 b */
+ uint64_t byte_7;
+ /* byte_8 is 64 b */
+ uint64_t byte_8;
+ /* byte_9 is 64 b */
+ uint64_t byte_9;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -23961,13 +25947,13 @@ struct hwrm_cfa_decap_filter_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_alloc *
- ***********************/
+/***********************************
+ * hwrm_cfa_flow_aging_timer_reset *
+ ***********************************/
-/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */
-struct hwrm_cfa_flow_alloc_input {
+/* hwrm_cfa_flow_aging_timer_reset_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_timer_reset_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -23989,219 +25975,21 @@ struct hwrm_cfa_flow_alloc_input {
*/
uint16_t target_id;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
- */
- uint64_t resp_addr;
- uint16_t flags;
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_TUNNEL \
- UINT32_C(0x1)
- /* num_vlan is 2 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_MASK \
- UINT32_C(0x6)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_SFT 1
- /* no tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_NONE \
- (UINT32_C(0x0) << 1)
- /* 1 tag */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_ONE \
- (UINT32_C(0x1) << 1)
- /* 2 tags */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO \
- (UINT32_C(0x2) << 1)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_NUM_VLAN_TWO
- /* Enumeration denoting the Flow Type. */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_MASK \
- UINT32_C(0x38)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_SFT 3
- /* L2 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_L2 \
- (UINT32_C(0x0) << 3)
- /* IPV4 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV4 \
- (UINT32_C(0x1) << 3)
- /* IPV6 flow */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6 \
- (UINT32_C(0x2) << 3)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6
- /*
- * when set to 1, indicates TX flow offload for function specified in src_fid and
- * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both
- * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload
- * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV
- * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID
- * belong to the children VFs of the same PF to indicate VM to VM flow.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \
- UINT32_C(0x40)
- /*
- * when set to 1, indicates RX flow offload for function specified in dst_fid and
- * the src_fid should be set to invalid value.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \
- UINT32_C(0x80)
- /*
- * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is
- * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.
- * This flag is only valid when the flow direction is RX.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
- UINT32_C(0x100)
- /*
- * Tx Flow: vf fid.
- * Rx Flow: pf fid.
- */
- uint16_t src_fid;
- /* Tunnel handle valid when tunnel flag is set. */
- uint32_t tunnel_handle;
- uint16_t action_flags;
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \
- UINT32_C(0x1)
- /* recycle is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \
- UINT32_C(0x2)
- /*
- * Setting of this flag indicates drop action. If this flag is not set,
- * then it should be considered accept action.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \
- UINT32_C(0x4)
- /* meter is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_METER \
- UINT32_C(0x8)
- /* tunnel is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL \
- UINT32_C(0x10)
- /* nat_src is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_SRC \
- UINT32_C(0x20)
- /* nat_dest is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_DEST \
- UINT32_C(0x40)
- /* nat_ipv4_address is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NAT_IPV4_ADDRESS \
- UINT32_C(0x80)
- /* l2_header_rewrite is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_L2_HEADER_REWRITE \
- UINT32_C(0x100)
- /* ttl_decrement is 1 b */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \
- UINT32_C(0x200)
- /*
- * If set to 1 and flow direction is TX, it indicates decap of L2 header
- * and encap of tunnel header. If set to 1 and flow direction is RX, it
- * indicates decap of tunnel header and encap L2 header. The type of tunnel
- * is specified in the tunnel_type field.
- */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \
- UINT32_C(0x400)
- /*
- * Tx Flow: pf or vf fid.
- * Rx Flow: vf fid.
- */
- uint16_t dst_fid;
- /* VLAN tpid, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tpid;
- /* VLAN tci, valid when push_vlan flag is set. */
- uint16_t l2_rewrite_vlan_tci;
- /* Meter id, valid when meter flag is set. */
- uint16_t act_meter_id;
- /* Flow with the same l2 context tcam key. */
- uint16_t ref_flow_handle;
- /* This value sets the match value for the ethertype. */
- uint16_t ethertype;
- /* valid when num tags is 1 or 2. */
- uint16_t outer_vlan_tci;
- /* This value sets the match value for the Destination MAC address. */
- uint16_t dmac[3];
- /* valid when num tags is 2. */
- uint16_t inner_vlan_tci;
- /* This value sets the match value for the Source MAC address. */
- uint16_t smac[3];
- /* The bit length of destination IP address mask. */
- uint8_t ip_dst_mask_len;
- /* The bit length of source IP address mask. */
- uint8_t ip_src_mask_len;
- /* The value of destination IPv4/IPv6 address. */
- uint32_t ip_dst[4];
- /* The source IPv4/IPv6 address. */
- uint32_t ip_src[4];
- /*
- * The value of source port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port;
- /*
- * The value of source port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_src_port_mask;
- /*
- * The value of destination port.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port;
- /*
- * The value of destination port mask.
- * Applies to UDP and TCP traffic.
- */
- uint16_t l4_dst_port_mask;
- /*
- * NAT IPv4/6 address based on address type flag.
- * 0 values are ignored.
- */
- uint32_t nat_ip_address[4];
- /* L2 header re-write Destination MAC address. */
- uint16_t l2_rewrite_dmac[3];
- /*
- * The NAT source/destination port based on direction flag.
- * Applies to UDP and TCP traffic.
- * 0 values are ignored.
- */
- uint16_t nat_port;
- /* L2 header re-write Source MAC address. */
- uint16_t l2_rewrite_smac[3];
- /* The value of ip protocol. */
- uint8_t ip_proto;
- /* Tunnel Type. */
- uint8_t tunnel_type;
- /* Non-tunnel */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NONTUNNEL UINT32_C(0x0)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN UINT32_C(0x1)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_NVGRE UINT32_C(0x2)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2GRE UINT32_C(0x3)
- /* IP in IP */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPIP UINT32_C(0x4)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_GENEVE UINT32_C(0x5)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_MPLS UINT32_C(0x6)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_STT UINT32_C(0x7)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE UINT32_C(0x8)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 UINT32_C(0x9)
- /* Any tunneled traffic */
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL UINT32_C(0xff)
- #define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Flow record index. */
+ uint16_t flow_handle;
+ uint8_t unused_0[6];
+ /* This value identifies a set of CFA data structures used for a flow. */
+ uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_alloc_output (size:256b/32B) */
-struct hwrm_cfa_flow_alloc_output {
+/* hwrm_cfa_flow_aging_timer_reset_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_timer_reset_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24210,20 +25998,7 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[2];
- /*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
- */
- uint32_t flow_id;
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24234,13 +26009,13 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_flow_free *
- **********************/
+/***************************
+ * hwrm_cfa_flow_aging_cfg *
+ ***************************/
-/* hwrm_cfa_flow_free_input (size:256b/32B) */
-struct hwrm_cfa_flow_free_input {
+/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24268,15 +26043,38 @@ struct hwrm_cfa_flow_free_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow record index. */
- uint16_t flow_handle;
- uint8_t unused_0[6];
- /* This value identifies a set of CFA data structures used for a flow. */
- uint64_t ext_flow_handle;
+ /* The bit field to enable per flow aging configuration. */
+ uint16_t enables;
+ /* This bit must be '1' for the tcp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \
+ UINT32_C(0x1)
+ /* This bit must be '1' for the tcp finish timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \
+ UINT32_C(0x2)
+ /* This bit must be '1' for the udp flow timer field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
+ UINT32_C(0x4)
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_flow_timer;
+ /* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */
+ uint32_t tcp_fin_timer;
+ /* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
+ uint32_t udp_flow_timer;
} __attribute__((packed));
-/* hwrm_cfa_flow_free_output (size:256b/32B) */
-struct hwrm_cfa_flow_free_output {
+/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
+struct hwrm_cfa_flow_aging_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24285,10 +26083,6 @@ struct hwrm_cfa_flow_free_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet is 64 b */
- uint64_t packet;
- /* byte is 64 b */
- uint64_t byte;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24300,13 +26094,13 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_flush *
- ***********************/
+/****************************
+ * hwrm_cfa_flow_aging_qcfg *
+ ****************************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
-struct hwrm_cfa_flow_flush_input {
+/* hwrm_cfa_flow_aging_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24334,12 +26128,21 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- uint8_t unused_0[4];
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_flush_output (size:128b/16B) */
-struct hwrm_cfa_flow_flush_output {
+/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24348,7 +26151,13 @@ struct hwrm_cfa_flow_flush_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ /* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_flow_timer;
+ /* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t tcp_fin_timer;
+ /* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t udp_flow_timer;
+ uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -24359,13 +26168,13 @@ struct hwrm_cfa_flow_flush_output {
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_cfa_flow_stats *
- ***********************/
+/*****************************
+ * hwrm_cfa_flow_aging_qcaps *
+ *****************************/
-/* hwrm_cfa_flow_stats_input (size:640b/80B) */
-struct hwrm_cfa_flow_stats_input {
+/* hwrm_cfa_flow_aging_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_flow_aging_qcaps_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24393,53 +26202,21 @@ struct hwrm_cfa_flow_stats_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* Flow handle. */
- uint16_t num_flows;
- /* Flow handle. */
- uint16_t flow_handle_0;
- /* Flow handle. */
- uint16_t flow_handle_1;
- /* Flow handle. */
- uint16_t flow_handle_2;
- /* Flow handle. */
- uint16_t flow_handle_3;
- /* Flow handle. */
- uint16_t flow_handle_4;
- /* Flow handle. */
- uint16_t flow_handle_5;
- /* Flow handle. */
- uint16_t flow_handle_6;
- /* Flow handle. */
- uint16_t flow_handle_7;
- /* Flow handle. */
- uint16_t flow_handle_8;
- /* Flow handle. */
- uint16_t flow_handle_9;
- uint8_t unused_0[2];
- /* Flow ID of a flow. */
- uint32_t flow_id_0;
- /* Flow ID of a flow. */
- uint32_t flow_id_1;
- /* Flow ID of a flow. */
- uint32_t flow_id_2;
- /* Flow ID of a flow. */
- uint32_t flow_id_3;
- /* Flow ID of a flow. */
- uint32_t flow_id_4;
- /* Flow ID of a flow. */
- uint32_t flow_id_5;
- /* Flow ID of a flow. */
- uint32_t flow_id_6;
- /* Flow ID of a flow. */
- uint32_t flow_id_7;
- /* Flow ID of a flow. */
- uint32_t flow_id_8;
- /* Flow ID of a flow. */
- uint32_t flow_id_9;
+ /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ uint8_t flags;
+ /* Enumeration denoting the RX, TX type of the resource. */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_stats_output (size:1408b/176B) */
-struct hwrm_cfa_flow_stats_output {
+/* hwrm_cfa_flow_aging_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_flow_aging_qcaps_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24448,46 +26225,14 @@ struct hwrm_cfa_flow_stats_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* packet_0 is 64 b */
- uint64_t packet_0;
- /* packet_1 is 64 b */
- uint64_t packet_1;
- /* packet_2 is 64 b */
- uint64_t packet_2;
- /* packet_3 is 64 b */
- uint64_t packet_3;
- /* packet_4 is 64 b */
- uint64_t packet_4;
- /* packet_5 is 64 b */
- uint64_t packet_5;
- /* packet_6 is 64 b */
- uint64_t packet_6;
- /* packet_7 is 64 b */
- uint64_t packet_7;
- /* packet_8 is 64 b */
- uint64_t packet_8;
- /* packet_9 is 64 b */
- uint64_t packet_9;
- /* byte_0 is 64 b */
- uint64_t byte_0;
- /* byte_1 is 64 b */
- uint64_t byte_1;
- /* byte_2 is 64 b */
- uint64_t byte_2;
- /* byte_3 is 64 b */
- uint64_t byte_3;
- /* byte_4 is 64 b */
- uint64_t byte_4;
- /* byte_5 is 64 b */
- uint64_t byte_5;
- /* byte_6 is 64 b */
- uint64_t byte_6;
- /* byte_7 is 64 b */
- uint64_t byte_7;
- /* byte_8 is 64 b */
- uint64_t byte_8;
- /* byte_9 is 64 b */
- uint64_t byte_9;
+ /* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_flow_timer;
+ /* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */
+ uint32_t max_tcp_fin_timer;
+ /* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */
+ uint32_t max_udp_flow_timer;
+ /* The maximum aging flows that HW can support. */
+ uint32_t max_aging_flows;
uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
@@ -24706,6 +26451,12 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
/* Any tunneled traffic */
#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24765,8 +26516,14 @@ struct hwrm_tunnel_dst_port_query_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_QUERY_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0[7];
} __attribute__((packed));
@@ -24857,8 +26614,14 @@ struct hwrm_tunnel_dst_port_alloc_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* This field represents the value of L4 destination port used
@@ -24948,8 +26711,14 @@ struct hwrm_tunnel_dst_port_free_input {
/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \
UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_LAST \
- HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1
+ HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6
uint8_t unused_0;
/*
* Identifier of a tunnel L4 destination port value. Only applies to tunnel
@@ -25025,6 +26794,52 @@ struct ctx_hw_stats {
uint64_t tpa_aborts;
} __attribute__((packed));
+/* Periodic Engine statistics context DMA to host. */
+/* ctx_eng_stats (size:512b/64B) */
+struct ctx_eng_stats {
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+} __attribute__((packed));
+
/***********************
* hwrm_stat_ctx_alloc *
***********************/
@@ -25081,7 +26896,7 @@ struct hwrm_stat_ctx_alloc_input {
* than offloaded RoCE traffic shall not be included in this
* statistic context.
* When this bit is set to '0', the statistics context shall be
- * used for the network traffic other than offloaded RoCE traffic.
+ * used for network traffic or engine traffic.
*/
#define HWRM_STAT_CTX_ALLOC_INPUT_STAT_CTX_FLAGS_ROCE UINT32_C(0x1)
uint8_t unused_0[3];
@@ -25272,6 +27087,107 @@ struct hwrm_stat_ctx_query_output {
uint8_t valid;
} __attribute__((packed));
+/***************************
+ * hwrm_stat_ctx_eng_query *
+ ***************************/
+
+
+/* hwrm_stat_ctx_eng_query_input (size:192b/24B) */
+struct hwrm_stat_ctx_eng_query_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* ID of the statistics context that is being queried. */
+ uint32_t stat_ctx_id;
+ uint8_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_stat_ctx_eng_query_output (size:640b/80B) */
+struct hwrm_stat_ctx_eng_query_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Count of data bytes into the Engine.
+ * This includes any user supplied prefix,
+ * but does not include any predefined
+ * prefix data.
+ */
+ uint64_t eng_bytes_in;
+ /* Count of data bytes out of the Engine. */
+ uint64_t eng_bytes_out;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are input as auxillary data.
+ * This includes the aux_cmd data.
+ */
+ uint64_t aux_bytes_in;
+ /*
+ * Count, in 4-byte (dword) units, of bytes
+ * that are output as auxillary data.
+ * This count is the buffer space for aux_data
+ * output provided in the RQE, not the actual
+ * aux_data written
+ */
+ uint64_t aux_bytes_out;
+ /* Count of number of commands executed. */
+ uint64_t commands;
+ /*
+ * Count of number of error commands.
+ * These are the commands with a
+ * non-zero status value.
+ */
+ uint64_t error_commands;
+ /*
+ * Compression/Encryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cce_engine_usage;
+ /*
+ * De-Compression/De-cryption Engine usage,
+ * the unit is count of clock cycles
+ */
+ uint64_t cdd_engine_usage;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***************************
* hwrm_stat_ctx_clr_stats *
***************************/
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 7/8] net/bnxt: update HWRM API to version 1.10.0.48
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
` (5 preceding siblings ...)
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 6/8] net/bnxt: update HWRM API to version 1.10.0.19 Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
2019-06-04 16:07 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Ferruh Yigit
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM version to 1.10.0.48
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
drivers/net/bnxt/hsi_struct_def_dpdk.h | 3156 +++++++++++++++++++++---
1 file changed, 2874 insertions(+), 282 deletions(-)
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index ea9a7d40e..00a8ff87e 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -260,6 +260,7 @@ struct cmd_nums {
*/
uint16_t req_type;
#define HWRM_VER_GET UINT32_C(0x0)
+ #define HWRM_ERROR_RECOVERY_QCFG UINT32_C(0xc)
#define HWRM_FUNC_DRV_IF_CHANGE UINT32_C(0xd)
#define HWRM_FUNC_BUF_UNRGTR UINT32_C(0xe)
#define HWRM_FUNC_VF_CFG UINT32_C(0xf)
@@ -372,6 +373,8 @@ struct cmd_nums {
#define HWRM_STAT_CTX_QUERY UINT32_C(0xb2)
#define HWRM_STAT_CTX_CLR_STATS UINT32_C(0xb3)
#define HWRM_PORT_QSTATS_EXT UINT32_C(0xb4)
+ #define HWRM_PORT_PHY_MDIO_WRITE UINT32_C(0xb5)
+ #define HWRM_PORT_PHY_MDIO_READ UINT32_C(0xb6)
#define HWRM_FW_RESET UINT32_C(0xc0)
#define HWRM_FW_QSTATUS UINT32_C(0xc1)
#define HWRM_FW_HEALTH_CHECK UINT32_C(0xc2)
@@ -397,6 +400,8 @@ struct cmd_nums {
#define HWRM_WOL_FILTER_QCFG UINT32_C(0xf2)
#define HWRM_WOL_REASON_QCFG UINT32_C(0xf3)
/* Experimental */
+ #define HWRM_CFA_METER_QCAPS UINT32_C(0xf4)
+ /* Experimental */
#define HWRM_CFA_METER_PROFILE_ALLOC UINT32_C(0xf5)
/* Experimental */
#define HWRM_CFA_METER_PROFILE_FREE UINT32_C(0xf6)
@@ -407,6 +412,8 @@ struct cmd_nums {
/* Experimental */
#define HWRM_CFA_METER_INSTANCE_FREE UINT32_C(0xf9)
/* Experimental */
+ #define HWRM_CFA_METER_INSTANCE_CFG UINT32_C(0xfa)
+ /* Experimental */
#define HWRM_CFA_VFR_ALLOC UINT32_C(0xfd)
/* Experimental */
#define HWRM_CFA_VFR_FREE UINT32_C(0xfe)
@@ -451,6 +458,34 @@ struct cmd_nums {
#define HWRM_CFA_FLOW_AGING_QCFG UINT32_C(0x115)
/* Experimental */
#define HWRM_CFA_FLOW_AGING_QCAPS UINT32_C(0x116)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_RGTR UINT32_C(0x117)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_UNRGTR UINT32_C(0x118)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCTX UINT32_C(0x119)
+ /* Experimental */
+ #define HWRM_CFA_CTX_MEM_QCAPS UINT32_C(0x11a)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCAPS UINT32_C(0x11b)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_CFG UINT32_C(0x11c)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QCFG UINT32_C(0x11d)
+ /* Experimental */
+ #define HWRM_CFA_COUNTER_QSTATS UINT32_C(0x11e)
+ /* Experimental */
+ #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG UINT32_C(0x11f)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCAPS UINT32_C(0x120)
+ /* Experimental */
+ #define HWRM_CFA_EEM_CFG UINT32_C(0x121)
+ /* Experimental */
+ #define HWRM_CFA_EEM_QCFG UINT32_C(0x122)
+ /* Experimental */
+ #define HWRM_CFA_EEM_OP UINT32_C(0x123)
+ /* Experimental */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -469,6 +504,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_RNG_GET UINT32_C(0x134)
/* Engine CKV - Generate and encrypt a new AES key. */
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
+ /* Engine CKV - Configure a label index with a label value. */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -523,6 +560,8 @@ struct cmd_nums {
#define HWRM_ENGINE_NQ_FREE UINT32_C(0x163)
/* Engine - Set the on-die RQE credit update location. */
#define HWRM_ENGINE_ON_DIE_RQE_CREDITS UINT32_C(0x164)
+ /* Engine - Query the engine function configuration. */
+ #define HWRM_ENGINE_FUNC_QCFG UINT32_C(0x165)
/* Experimental */
#define HWRM_FUNC_RESOURCE_QCAPS UINT32_C(0x190)
/* Experimental */
@@ -573,6 +612,10 @@ struct cmd_nums {
/* */
#define HWRM_DBG_RING_INFO_GET UINT32_C(0xff1c)
/* Experimental */
+ #define HWRM_DBG_CRASHDUMP_HEADER UINT32_C(0xff1d)
+ /* Experimental */
+ #define HWRM_DBG_CRASHDUMP_ERASE UINT32_C(0xff1e)
+ /* Experimental */
#define HWRM_NVM_FACTORY_DEFAULTS UINT32_C(0xffee)
#define HWRM_NVM_VALIDATE_OPTION UINT32_C(0xffef)
#define HWRM_NVM_FLUSH UINT32_C(0xfff0)
@@ -724,8 +767,8 @@ struct hwrm_err_output {
#define HWRM_NA_SIGNATURE ((uint32_t)(-1))
/* hwrm_func_buf_rgtr */
#define HWRM_MAX_REQ_LEN 128
-/* hwrm_selftest_qlist */
-#define HWRM_MAX_RESP_LEN 280
+/* hwrm_cfa_flow_info */
+#define HWRM_MAX_RESP_LEN 704
/* 7 bit indirection table index. */
#define HW_HASH_INDEX_SIZE 0x80
#define HW_HASH_KEY_SIZE 40
@@ -735,8 +778,8 @@ struct hwrm_err_output {
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 19
-#define HWRM_VERSION_STR "1.10.0.19"
+#define HWRM_VERSION_RSVD 48
+#define HWRM_VERSION_STR "1.10.0.48"
/****************
* hwrm_ver_get *
@@ -993,6 +1036,32 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED \
UINT32_C(0x200)
+ /*
+ * If set to 1, firmware is capable to support advanced flow counters like,
+ * Meter drop counters and EEM counters.
+ * If set to 0, firmware is not capable to support advanced flow counters.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * If set to 1, the firmware is able to support the use of the CFA
+ * Extended Exact Match(EEM) feature.
+ * If set to 0, firmware is not capable to support the use of the
+ * CFA EEM feature.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_EEM_SUPPORTED \
+ UINT32_C(0x800)
+ /*
+ * If set to 1, the firmware is able to support advance CFA flow management
+ * features reported in the HWRM_CFA_FLOW_MGNT_QCAPS.
+ * If set to 0, then the firmware doesn’t support the advance CFA flow management
+ * features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
+ UINT32_C(0x1000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -3695,6 +3764,9 @@ struct hwrm_async_event_cmpl {
/* Reset notification to clients */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY \
UINT32_C(0x8)
+ /* Master function selection event */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
/* Function driver unloaded */
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD \
UINT32_C(0x10)
@@ -3739,6 +3811,40 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION \
UINT32_C(0x37)
+ /*
+ * A EEM flow cached memory flush request event being posted to the PF
+ * driver.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ /*
+ * A EEM flow cache memory flush completion event being posted to the
+ * firmware by the PF driver. This is indication that host EEM flush
+ * has completed by the PF.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ /*
+ * A tcp flag action change event being posted to the PF or trusted VF
+ * driver by the firmware. The PF or trusted VF driver should query
+ * the firmware for the new TCP flag action update after receiving
+ * this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ /*
+ * A eem flow active event being posted to the PF or trusted VF driver
+ * by the firmware. The PF or trusted VF driver should update the
+ * flow's aging timer after receiving this async event.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ /*
+ * A eem cfg change event being posted to the trusted VF driver by the
+ * firmware if the parent PF EEM configuration changed.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -4450,6 +4556,75 @@ struct hwrm_async_event_cmpl_reset_notify {
16
} __attribute__((packed));
+/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
+struct hwrm_async_event_cmpl_error_recovery {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /*
+ * This async notification message can be used for selecting or
+ * deselecting master function for error recovery,
+ * and to communicate to all the functions whether error recovery
+ * was enabled/disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY \
+ UINT32_C(0x9)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
+ /* 8-lsb timestamp (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates driver action requested */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT \
+ 0
+ /*
+ * If set to 1, this function is selected as Master function.
+ * This function has responsibility to do 'chip reset' when it
+ * detects a fatal error. If set to 0, master function functionality
+ * is disabled on this function.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, error recovery is enabled.
+ * If set to 0, error recovery is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
/* hwrm_async_event_cmpl_func_drvr_unload (size:128b/16B) */
struct hwrm_async_event_cmpl_func_drvr_unload {
uint16_t type;
@@ -5182,8 +5357,8 @@ struct hwrm_async_event_cmpl_hw_flow_aged {
HWRM_ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
} __attribute__((packed));
-/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
-struct hwrm_async_event_cmpl_hwrm_error {
+/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_req {
uint16_t type;
/*
* This field indicates the exact type of the completion.
@@ -5192,133 +5367,549 @@ struct hwrm_async_event_cmpl_hwrm_error {
* records. Odd values indicate 32B
* records.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK \
UINT32_C(0x3f)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT \
+ 0
/* HWRM Asynchronous Event Information */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT \
UINT32_C(0x2e)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
/* Identifiers of events. */
uint16_t event_id;
- /* HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Notification of a eem_cache_flush request */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ \
+ UINT32_C(0x38)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
/* Event specific data */
uint32_t event_data2;
- /* Severity of HWRM Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
- UINT32_C(0xff)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
- /* Warning */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
- UINT32_C(0x0)
- /* Non-fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
- UINT32_C(0x1)
- /* Fatal Error */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
- UINT32_C(0x2)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
- HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
uint8_t opaque_v;
/*
* This value is written by the NIC such that it will be different
* for each pass through the completion queue. The even passes
* will write 1. The odd passes will write 0.
*/
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V \
+ UINT32_C(0x1)
/* opaque is 7 b */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
/* 8-lsb timestamp from POR (100-msec resolution) */
uint8_t timestamp_lo;
/* 16-lsb timestamp from POR (100-msec resolution) */
uint16_t timestamp_hi;
/* Event specific data */
uint32_t event_data1;
- /* Time stamp for error event */
- #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
- UINT32_C(0x1)
} __attribute__((packed));
-/*******************
- * hwrm_func_reset *
- *******************/
-
-
-/* hwrm_func_reset_input (size:192b/24B) */
-struct hwrm_func_reset_input {
- /* The HWRM command request type. */
- uint16_t req_type;
+/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cache_flush_done {
+ uint16_t type;
/*
- * The completion ring to send the completion event on. This should
- * be the NQ ID returned from the `nq_alloc` HWRM command.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t cmpl_ring;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
/*
- * The sequence ID is used by the driver for tracking multiple
- * commands. This ID is treated as opaque data by the firmware and
- * the value is returned in the `hwrm_resp_hdr` upon completion.
+ * Notification of a host eem_cache_flush has completed. This event
+ * is generated by the host driver.
*/
- uint16_t seq_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE \
+ UINT32_C(0x39)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * The target ID of the command:
- * * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
- * * 0xFFFF - HWRM
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- uint16_t target_id;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates function ID that this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK \
+ UINT32_C(0xffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT \
+ 0
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_tcp_flag_action_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_tcp_flag_action_change {
+ uint16_t type;
/*
- * A physical address pointer pointing to a host buffer that the
- * command's response data will be written. This can be either a host
- * physical address (HPA) or a guest physical address (GPA) and must
- * point to a physically contiguous block of memory.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint64_t resp_addr;
- uint32_t enables;
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_SFT \
+ 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of tcp flag action change */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE \
+ UINT32_C(0x3a)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_EVENT_ID_TCP_FLAG_ACTION_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
/*
- * This bit must be '1' for the vf_id_valid field to be
- * configured.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_V \
+ UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_TCP_FLAG_ACTION_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_flow_active (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_flow_active {
+ uint16_t type;
/*
- * The ID of the VF that this PF is trying to reset.
- * Only the parent PF shall be allowed to reset a child VF.
- *
- * A parent PF driver shall use this field only when a specific child VF
- * is requested to be reset.
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
*/
- uint16_t vf_id;
- /* This value indicates the level of a function reset. */
- uint8_t func_reset_level;
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of an active eem flow */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE \
+ UINT32_C(0x3b)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_ID_EEM_FLOW_ACTIVE
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Indicates the 2nd global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_GLOBAL_ID_2_SFT \
+ 0
/*
- * Reset the caller function and its children VFs (if any). If no
- * children functions exist, then reset the caller function only.
- */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
- UINT32_C(0x0)
- /* Reset the caller function only */
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
- UINT32_C(0x1)
+ * Indicates flow direction of the flow identified by
+ * the global_id_2.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA2_FLOW_DIRECTION_TX
+ uint8_t opaque_v;
/*
- * Reset all children VFs of the caller function driver if the
- * caller is a PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver with
- * no children VFs.
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
*/
- #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
- UINT32_C(0x2)
- /*
- * Reset a specific VF of the caller function driver if the caller
- * is the parent PF driver.
- * It is an error to specify this level by a VF driver.
- * It is an error to specify this level by a PF driver that is not
- * the parent of the VF that is being requested to reset.
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_MASK \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Indicates the 1st global id this event occured on. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_GLOBAL_ID_1_SFT \
+ 0
+ /*
+ * Indicates flow direction of the flow identified by the
+ * global_id_1.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION \
+ UINT32_C(0x40000000)
+ /* If this bit is set to 0, then it indicates that this is rx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_RX \
+ (UINT32_C(0x0) << 30)
+ /* If this bit is set to 1, then it indicates that this is tx flow. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_FLOW_DIRECTION_TX
+ /*
+ * Indicates EEM flow aging mode this event occured on. If
+ * this bit is set to 0, the event_data1 is the EEM global
+ * ID. If this bit is set to 1, the event_data1 is the number
+ * of global ID in the context memory.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE \
+ UINT32_C(0x80000000)
+ /* EEM flow aging mode 0. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_0 \
+ (UINT32_C(0x0) << 31)
+ /* EEM flow aging mode 1. */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1 \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_FLOW_ACTIVE_EVENT_DATA1_MODE_1
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_eem_cfg_change (size:128b/16B) */
+struct hwrm_async_event_cmpl_eem_cfg_change {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Notification of EEM configuration change */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE \
+ UINT32_C(0x3c)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_ID_EEM_CFG_CHANGE
+ /* Event specific data */
+ uint32_t event_data2;
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /*
+ * Value of 1 to indicate EEM TX configuration is enabled. Value of
+ * 0 to indicate the EEM TX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_TX_ENABLE \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate EEM RX configuration is enabled. Value of 0
+ * to indicate the EEM RX configuration is disabled.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_EEM_CFG_CHANGE_EVENT_DATA1_EEM_RX_ENABLE \
+ UINT32_C(0x2)
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */
+struct hwrm_async_event_cmpl_fw_trace_msg {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* Firmware trace log message */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG \
+ UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_ID_FW_TRACE_MSG
+ /* Trace byte 0 to 3 */
+ uint32_t event_data2;
+ /* Trace byte0 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE0_SFT 0
+ /* Trace byte1 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE1_SFT 8
+ /* Trace byte2 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE2_SFT 16
+ /* Trace byte3 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA2_BYTE3_SFT 24
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_OPAQUE_SFT 1
+ /* Trace flags */
+ uint8_t timestamp_lo;
+ /* Indicates if the string is partial or complete. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING \
+ UINT32_C(0x1)
+ /* Complete string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_COMPLETE \
+ UINT32_C(0x0)
+ /* Partial string */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL \
+ UINT32_C(0x1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_STRING_PARTIAL
+ /* Indicates the firmware that sent the trace message. */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE \
+ UINT32_C(0x2)
+ /* Primary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_PRIMARY \
+ (UINT32_C(0x0) << 1)
+ /* Secondary firmware */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_LO_FIRMWARE_SECONDARY
+ /* Trace byte 4 to 5 */
+ uint16_t timestamp_hi;
+ /* Trace byte4 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE4_SFT 0
+ /* Trace byte5 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_TIMESTAMP_HI_BYTE5_SFT 8
+ /* Trace byte 6 to 9 */
+ uint32_t event_data1;
+ /* Trace byte6 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE6_SFT 0
+ /* Trace byte7 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_MASK \
+ UINT32_C(0xff00)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE7_SFT 8
+ /* Trace byte8 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_MASK \
+ UINT32_C(0xff0000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE8_SFT 16
+ /* Trace byte9 */
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_MASK \
+ UINT32_C(0xff000000)
+ #define HWRM_ASYNC_EVENT_CMPL_FW_TRACE_MSG_EVENT_DATA1_BYTE9_SFT 24
+} __attribute__((packed));
+
+/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
+struct hwrm_async_event_cmpl_hwrm_error {
+ uint16_t type;
+ /*
+ * This field indicates the exact type of the completion.
+ * By convention, the LSB identifies the length of the
+ * record in 16B units. Even values indicate 16B
+ * records. Odd values indicate 32B
+ * records.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK \
+ UINT32_C(0x3f)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT 0
+ /* HWRM Asynchronous Event Information */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT \
+ UINT32_C(0x2e)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
+ /* Identifiers of events. */
+ uint16_t event_id;
+ /* HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
+ /* Event specific data */
+ uint32_t event_data2;
+ /* Severity of HWRM Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK \
+ UINT32_C(0xff)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT 0
+ /* Warning */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING \
+ UINT32_C(0x0)
+ /* Non-fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL \
+ UINT32_C(0x1)
+ /* Fatal Error */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL \
+ UINT32_C(0x2)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST \
+ HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
+ uint8_t opaque_v;
+ /*
+ * This value is written by the NIC such that it will be different
+ * for each pass through the completion queue. The even passes
+ * will write 1. The odd passes will write 0.
+ */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_V UINT32_C(0x1)
+ /* opaque is 7 b */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK UINT32_C(0xfe)
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
+ /* 8-lsb timestamp from POR (100-msec resolution) */
+ uint8_t timestamp_lo;
+ /* 16-lsb timestamp from POR (100-msec resolution) */
+ uint16_t timestamp_hi;
+ /* Event specific data */
+ uint32_t event_data1;
+ /* Time stamp for error event */
+ #define HWRM_ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP \
+ UINT32_C(0x1)
+} __attribute__((packed));
+
+/*******************
+ * hwrm_func_reset *
+ *******************/
+
+
+/* hwrm_func_reset_input (size:192b/24B) */
+struct hwrm_func_reset_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the vf_id_valid field to be
+ * configured.
+ */
+ #define HWRM_FUNC_RESET_INPUT_ENABLES_VF_ID_VALID UINT32_C(0x1)
+ /*
+ * The ID of the VF that this PF is trying to reset.
+ * Only the parent PF shall be allowed to reset a child VF.
+ *
+ * A parent PF driver shall use this field only when a specific child VF
+ * is requested to be reset.
+ */
+ uint16_t vf_id;
+ /* This value indicates the level of a function reset. */
+ uint8_t func_reset_level;
+ /*
+ * Reset the caller function and its children VFs (if any). If no
+ * children functions exist, then reset the caller function only.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETALL \
+ UINT32_C(0x0)
+ /* Reset the caller function only */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETME \
+ UINT32_C(0x1)
+ /*
+ * Reset all children VFs of the caller function driver if the
+ * caller is a PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver with
+ * no children VFs.
+ */
+ #define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETCHILDREN \
+ UINT32_C(0x2)
+ /*
+ * Reset a specific VF of the caller function driver if the caller
+ * is the parent PF driver.
+ * It is an error to specify this level by a VF driver.
+ * It is an error to specify this level by a PF driver that is not
+ * the parent of the VF that is being requested to reset.
*/
#define HWRM_FUNC_RESET_INPUT_FUNC_RESET_LEVEL_RESETVF \
UINT32_C(0x3)
@@ -6066,6 +6657,12 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_HOT_RESET_CAPABLE \
UINT32_C(0x400000)
+ /*
+ * This flag will be set to 1 by the FW if FW supports adapter error
+ * recovery.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
+ UINT32_C(0x800000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6813,8 +7410,7 @@ struct hwrm_func_cfg_input {
* resident HWRM clients, only the parent PF driver shall be allowed
* to initiate this change on one of its children VFs. If this bit is
* set to 1, then the VF that is being configured is requested to be
- * trusted. If this bit is set to 0, then the VF that is being configured
- * is requested to be not trusted.
+ * trusted.
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_ENABLE \
UINT32_C(0x200000)
@@ -6825,6 +7421,25 @@ struct hwrm_func_cfg_input {
*/
#define HWRM_FUNC_CFG_INPUT_FLAGS_DYNAMIC_TX_RING_ALLOC \
UINT32_C(0x400000)
+ /*
+ * This bit requests that the firmware test to see if all the assets
+ * requested in this command (i.e. number of NQ rings) are available.
+ * The firmware will return an error if the requested assets are
+ * not available. The firwmare will NOT reserve the assets if they
+ * are available.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_NQ_ASSETS_TEST \
+ UINT32_C(0x800000)
+ /*
+ * This configuration change can be initiated by a PF driver. This
+ * configuration request shall be targeted to a VF. From local host
+ * resident HWRM clients, only the parent PF driver shall be allowed
+ * to initiate this change on one of its children VFs. If this bit is
+ * set to 1, then the VF that is being configured is requested to be
+ * untrusted.
+ */
+ #define HWRM_FUNC_CFG_INPUT_FLAGS_TRUSTED_VF_DISABLE \
+ UINT32_C(0x1000000)
uint32_t enables;
/*
* This bit must be '1' for the mtu field to be
@@ -7593,6 +8208,19 @@ struct hwrm_func_drv_rgtr_input {
*/
#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_HOT_RESET_SUPPORT \
UINT32_C(0x10)
+ /*
+ * When this bit is 1, the function is indicating the support of the
+ * error recovery capability. Error recovery support will be used by
+ * firmware only if all the driver instances support error recovery
+ * process. By setting this bit, driver is indicating support for
+ * corresponding async event completion message. These will be
+ * delivered to the driver even if they did not register for it.
+ * If supported, after receiving reset notify async event with fatal
+ * flag set in event data1, then all the drivers have to tear down
+ * their resources without sending any HWRM commands to FW.
+ */
+ #define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_ERROR_RECOVERY_SUPPORT \
+ UINT32_C(0x20)
uint32_t enables;
/*
* This bit must be '1' for the os_type field to be
@@ -10270,17 +10898,384 @@ struct hwrm_func_backing_store_qcfg_output {
uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
- * is completely written to RAM. This field should be read as '1'
+ * is completely written to RAM. This field should be read as 1
* to indicate that the output has been completely written.
- * When writing a command completion or response to an internal processor,
- * the order of writes has to be such that this field is written last.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
*/
uint8_t valid;
} __attribute__((packed));
-/***********************
- * hwrm_func_vlan_qcfg *
- ***********************/
+/****************************
+ * hwrm_error_recovery_qcfg *
+ ****************************/
+
+
+/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
+struct hwrm_error_recovery_qcfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint8_t unused_0[8];
+} __attribute__((packed));
+
+/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
+struct hwrm_error_recovery_qcfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When this flag is set to 1, error recovery will be initiated
+ * through master function driver.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_HOST UINT32_C(0x1)
+ /*
+ * When this flag is set to 1, error recovery will be performed
+ * through Co processor.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FLAGS_CO_CPU UINT32_C(0x2)
+ /*
+ * Driver Polling frequency. This value is in units of 100msec.
+ * Typical value would be 10 to indicate 1sec.
+ * Drivers can poll FW health status, Heartbeat, reset_counter with
+ * this frequency.
+ */
+ uint32_t driver_polling_freq;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 30 to indicate 3sec.
+ * Master function wait period from detecting a fatal error to
+ * initiating reset. In this time period Master PF expects every
+ * active driver will detect fatal error.
+ */
+ uint32_t master_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 50 to indicate 5sec.
+ * Normal function wait period from fatal error detection to
+ * polling FW health status. In this time period, drivers should not
+ * do any PCIe MMIO transaction and should not send any HWRM commands.
+ */
+ uint32_t normal_func_wait_period;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 20 to indicate 2sec.
+ * This field indicates that, master function wait period after chip
+ * reset. After this time, master function should reinitialize with
+ * FW.
+ */
+ uint32_t master_func_wait_period_after_reset;
+ /*
+ * This value is in units of 100msec.
+ * Typical value would be 60 to indicate 6sec.
+ * This field is applicable to both master and normal functions.
+ * Even after chip reset, if FW status not changed to ready,
+ * then all the functions can poll for this much time and bailout.
+ */
+ uint32_t max_bailout_time_after_reset;
+ /*
+ * FW health status register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates upper 30bits of the register address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_health_status_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEALTH_STATUS_REG_ADDR_SFT \
+ 2
+ /*
+ * FW HeartBeat register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_heartbeat_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_HEARTBEAT_REG_ADDR_SFT \
+ 2
+ /*
+ * FW reset counter.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t fw_reset_cnt_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_FW_RESET_CNT_REG_ADDR_SFT \
+ 2
+ /*
+ * Reset Inprogress Register address for PFs.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_inprogress_reg;
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_SFT \
+ 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_INPROGRESS_REG_ADDR_SFT \
+ 2
+ /* This field indicates the mask value for reset_inprogress_reg. */
+ uint32_t reset_inprogress_reg_mask;
+ uint8_t unused_0[3];
+ /*
+ * Array of registers and value count to reset the Chip
+ * Each array count has reset_reg, reset_reg_val, delay_after_reset
+ * in TLV format. Depending upon Chip type, number of reset registers
+ * will vary. Drivers have to write reset_reg_val in the reset_reg
+ * location in the same sequence in order to recover from a fatal
+ * error.
+ */
+ uint8_t reg_array_cnt;
+ /*
+ * Reset register.
+ * Lower 2 bits indicates address space location and upper 30 bits
+ * indicates actual address.
+ * A value of 0xFFFF-FFFF indicates this register does not exist.
+ */
+ uint32_t reset_reg[16];
+ /* Lower 2 bits indicates address space location. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_MASK \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_SFT 0
+ /*
+ * If value is 0, this register is located in PCIe config space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_PCIE_CFG \
+ UINT32_C(0x0)
+ /*
+ * If value is 1, this register is located in GRC address space.
+ * Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_GRC \
+ UINT32_C(0x1)
+ /*
+ * If value is 2, this register is located in first BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR0 \
+ UINT32_C(0x2)
+ /*
+ * If value is 3, this register is located in second BAR address
+ * space. Drivers have to map appropriate window to access this
+ * register.
+ */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1 \
+ UINT32_C(0x3)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_LAST \
+ HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SPACE_BAR1
+ /* Upper 30bits of the register address. */
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_MASK \
+ UINT32_C(0xfffffffc)
+ #define HWRM_ERROR_RECOVERY_QCFG_OUTPUT_RESET_REG_ADDR_SFT 2
+ /* Value to be written in reset_reg to reset the controller. */
+ uint32_t reset_reg_val[16];
+ /*
+ * This value is in units of 1msec.
+ * Typical value would be 10 to indicate 10msec.
+ * Some of the operations like Core reset require delay before
+ * accessing PCIE MMIO register space.
+ * If this value is non-zero, drivers have to wait for
+ * this much time after writing reset_reg_val in reset_reg.
+ */
+ uint8_t delay_after_reset[16];
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal
+ * processor, the order of writes has to be such that this field
+ * is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***********************
+ * hwrm_func_vlan_qcfg *
+ ***********************/
/* hwrm_func_vlan_qcfg_input (size:192b/24B) */
@@ -10894,6 +11889,12 @@ struct hwrm_func_drv_if_change_output {
*/
#define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_RESC_CHANGE \
UINT32_C(0x1)
+ /*
+ * When this bit is '1', it indicates that the firmware got changed / reset.
+ * The driver should do complete re-initialization when that bit is set.
+ */
+ #define HWRM_FUNC_DRV_IF_CHANGE_OUTPUT_FLAGS_HOT_FW_RESET_DONE \
+ UINT32_C(0x2)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -14166,6 +15167,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_FORCE_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for autonegotiation on this link.
@@ -14215,6 +15219,9 @@ struct hwrm_port_phy_qcaps_output {
/* 10Mb link speed (Full-duplex) */
#define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_10MB \
UINT32_C(0x2000)
+ /* 200Gb link speed */
+ #define HWRM_PORT_PHY_QCAPS_OUTPUT_SUPPORTED_SPEEDS_AUTO_MODE_200GB \
+ UINT32_C(0x4000)
/*
* This is a bit mask to indicate what speeds are supported
* for EEE on this link.
@@ -14281,13 +15288,13 @@ struct hwrm_port_phy_qcaps_output {
#define HWRM_PORT_PHY_QCAPS_OUTPUT_VALID_SFT 24
} __attribute__((packed));
-/*********************
- * hwrm_port_led_cfg *
- *********************/
+/****************************
+ * hwrm_port_phy_mdio_write *
+ ****************************/
-/* hwrm_port_led_cfg_input (size:512b/64B) */
-struct hwrm_port_led_cfg_input {
+/* hwrm_port_phy_mdio_write_input (size:320b/40B) */
+struct hwrm_port_phy_mdio_write_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -14315,46 +15322,198 @@ struct hwrm_port_led_cfg_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t enables;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ /*
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
+ */
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1[7];
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_write_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_write_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
/*
- * This bit must be '1' for the led0_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
- UINT32_C(0x1)
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_port_phy_mdio_read *
+ ***************************/
+
+
+/* hwrm_port_phy_mdio_read_input (size:256b/32B) */
+struct hwrm_port_phy_mdio_read_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
/*
- * This bit must be '1' for the led0_state field to be
- * configured.
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
- UINT32_C(0x2)
+ uint16_t cmpl_ring;
/*
- * This bit must be '1' for the led0_color field to be
- * configured.
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
- UINT32_C(0x4)
+ uint16_t seq_id;
/*
- * This bit must be '1' for the led0_blink_on field to be
- * configured.
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
- UINT32_C(0x8)
+ uint16_t target_id;
/*
- * This bit must be '1' for the led0_blink_off field to be
- * configured.
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
- UINT32_C(0x10)
+ uint64_t resp_addr;
+ /* Reserved for future use. */
+ uint32_t unused_0[2];
+ /* Port ID of port. */
+ uint16_t port_id;
+ /* If phy_address is 0xFF, port_id will be used to derive phy_addr. */
+ uint8_t phy_addr;
+ /* 8-bit device address. */
+ uint8_t dev_addr;
+ /* 16-bit register address. */
+ uint16_t reg_addr;
/*
- * This bit must be '1' for the led0_group_id field to be
- * configured.
+ * When this bit is set to 1 a Clause 45 mdio access is done.
+ * when this bit is set to 0 a Clause 22 mdio access is done.
*/
- #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
- UINT32_C(0x20)
+ uint8_t cl45_mdio;
+ /* */
+ uint8_t unused_1;
+} __attribute__((packed));
+
+/* hwrm_port_phy_mdio_read_output (size:128b/16B) */
+struct hwrm_port_phy_mdio_read_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* 16-bit register data. */
+ uint16_t reg_data;
+ uint8_t unused_0[5];
/*
- * This bit must be '1' for the led1_id field to be
- * configured.
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_port_led_cfg *
+ *********************/
+
+
+/* hwrm_port_led_cfg_input (size:512b/64B) */
+struct hwrm_port_led_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the led0_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_ID \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the led0_state field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_STATE \
+ UINT32_C(0x2)
+ /*
+ * This bit must be '1' for the led0_color field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_COLOR \
+ UINT32_C(0x4)
+ /*
+ * This bit must be '1' for the led0_blink_on field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_ON \
+ UINT32_C(0x8)
+ /*
+ * This bit must be '1' for the led0_blink_off field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_BLINK_OFF \
+ UINT32_C(0x10)
+ /*
+ * This bit must be '1' for the led0_group_id field to be
+ * configured.
+ */
+ #define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED0_GROUP_ID \
+ UINT32_C(0x20)
+ /*
+ * This bit must be '1' for the led1_id field to be
+ * configured.
*/
#define HWRM_PORT_LED_CFG_INPUT_ENABLES_LED1_ID \
UINT32_C(0x40)
@@ -20644,7 +21803,9 @@ struct hwrm_ring_reset_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- uint8_t unused_0[7];
+ uint8_t unused_0[4];
+ /* Position of consumer index after ring reset completes. */
+ uint8_t consumer_idx[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -21209,6 +22370,26 @@ struct hwrm_ring_grp_free_output {
*/
uint8_t valid;
} __attribute__((packed));
+/*
+ * special reserved flow ID to identify per function default
+ * flows for vSwitch offload
+ */
+#define DEFAULT_FLOW_ID 0xFFFFFFFFUL
+/*
+ * special reserved flow ID to identify per function RoCEv1
+ * flows
+ */
+#define ROCEV1_FLOW_ID 0xFFFFFFFEUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * flows
+ */
+#define ROCEV2_FLOW_ID 0xFFFFFFFDUL
+/*
+ * special reserved flow ID to identify per function RoCEv2
+ * CNP flows
+ */
+#define ROCEV2_CNP_FLOW_ID 0xFFFFFFFCUL
/****************************
* hwrm_cfa_l2_filter_alloc *
@@ -22968,6 +24149,13 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Setting of this flag indicates the applicability to the loopback path. */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \
UINT32_C(0x1)
+ /*
+ * Setting of this flag indicates this encap record is external encap record.
+ * Resetting of this flag indicates this flag is internal encap record and
+ * this is the default setting.
+ */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \
+ UINT32_C(0x2)
/* Encapsulation Type. */
uint8_t encap_type;
/* Virtual eXtensible Local Area Network (VXLAN) */
@@ -23003,8 +24191,11 @@ struct hwrm_cfa_encap_record_alloc_input {
/* Use fixed layer 2 ether type of 0xFFFF */
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \
UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \
- HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE
+ HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6
uint8_t unused_0[3];
/* This value is encap data used for the given encap type. */
uint32_t encap_data[20];
@@ -23144,6 +24335,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \
UINT32_C(0x4)
+ /*
+ * Setting of this flag indicates that the dest_id field contains function ID.
+ * If this is not set it indicates dest_id is VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x8)
uint32_t enables;
/*
* This bit must be '1' for the l2_filter_id field to be
@@ -23605,7 +24802,13 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_ENABLES_NEW_METER_INSTANCE_ID \
UINT32_C(0x4)
- uint8_t unused_0[4];
+ uint32_t flags;
+ /*
+ * Setting this bit to 1 indicates that dest_id field contains FID.
+ * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \
+ UINT32_C(0x1)
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
@@ -24090,6 +25293,118 @@ struct hwrm_cfa_em_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/************************
+ * hwrm_cfa_meter_qcaps *
+ ************************/
+
+
+/* hwrm_cfa_meter_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_meter_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_qcaps_output (size:320b/40B) */
+struct hwrm_cfa_meter_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Enumeration denoting the clock at which the Meter is running with.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
+ */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK UINT32_C(0xf)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT 0
+ /* 375 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_375MHZ UINT32_C(0x0)
+ /* 625 MHz */
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ UINT32_C(0x1)
+ #define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_LAST \
+ HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_625MHZ
+ uint8_t unused_0[4];
+ /*
+ * The minimum guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_tx_profile;
+ /*
+ * The maximum non-guaranteed number of tx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_tx_profile;
+ /*
+ * The minimum guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t min_rx_profile;
+ /*
+ * The maximum non-guaranteed number of rx meter profiles supported
+ * for this function.
+ */
+ uint16_t max_rx_profile;
+ /*
+ * The minimum guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t min_tx_instance;
+ /*
+ * The maximum non-guaranteed number of tx meter instances supported
+ * for this function.
+ */
+ uint16_t max_tx_instance;
+ /*
+ * The minimum guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t min_rx_instance;
+ /*
+ * The maximum non-guaranteed number of rx meter instances supported
+ * for this function.
+ */
+ uint16_t max_rx_instance;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/********************************
* hwrm_cfa_meter_profile_alloc *
********************************/
@@ -24200,11 +25515,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24243,7 +25558,7 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24286,11 +25601,11 @@ struct hwrm_cfa_meter_profile_alloc_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_ALLOC_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24564,11 +25879,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw value */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t commit_burst;
/* The bandwidth value. */
@@ -24607,7 +25922,7 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
+ /* Invalid value */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_INVALID \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_COMMIT_BURST_BW_VALUE_UNIT_LAST \
@@ -24650,11 +25965,11 @@ struct hwrm_cfa_meter_profile_cfg_input {
/* Value is in 1/100th of a percentage of total bandwidth. */
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_PERCENT1_100 \
(UINT32_C(0x1) << 29)
- /* Invalid unit */
- #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID \
+ /* Raw unit */
+ #define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW \
(UINT32_C(0x7) << 29)
#define HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_LAST \
- HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_INVALID
+ HWRM_CFA_METER_PROFILE_CFG_INPUT_EXCESS_PEAK_RATE_BW_VALUE_UNIT_RAW
/* A meter burst size specified in bytes. */
uint32_t excess_peak_burst;
/* The bandwidth value. */
@@ -24775,7 +26090,7 @@ struct hwrm_cfa_meter_instance_alloc_input {
/* This value identifies a meter profile in CFA. */
uint16_t meter_profile_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* profile is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_INPUT_METER_PROFILE_ID_INVALID \
@@ -24798,7 +26113,7 @@ struct hwrm_cfa_meter_instance_alloc_output {
/* This value identifies a meter instance in CFA. */
uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
+ * A value of 0xffff is considered invalid and implies the
* instance is not configured.
*/
#define HWRM_CFA_METER_INSTANCE_ALLOC_OUTPUT_METER_INSTANCE_ID_INVALID \
@@ -24816,13 +26131,13 @@ struct hwrm_cfa_meter_instance_alloc_output {
uint8_t valid;
} __attribute__((packed));
-/********************************
- * hwrm_cfa_meter_instance_free *
- ********************************/
+/*******************************
+ * hwrm_cfa_meter_instance_cfg *
+ *******************************/
-/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
-struct hwrm_cfa_meter_instance_free_input {
+/* hwrm_cfa_meter_instance_cfg_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24856,31 +26171,39 @@ struct hwrm_cfa_meter_instance_free_input {
* This enumeration is used for resources that are similar for both
* TX and RX paths of the chip.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_TX \
UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_FLAGS_PATH_RX
uint8_t unused_0;
- /* This value identifies a meter instance in CFA. */
- uint16_t meter_instance_id;
/*
- * A value of 0xfff is considered invalid and implies the
- * instance is not configured.
+ * This value identifies a new meter profile to be associated with
+ * the meter instance specified in this command.
*/
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ uint16_t meter_profile_id;
+ /*
+ * A value of 0xffff is considered invalid and implies the
+ * profile is not configured.
+ */
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID \
UINT32_C(0xffff)
- #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
- HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
- uint8_t unused_1[4];
+ #define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID
+ /*
+ * This value identifies the ID of a meter instance that needs to be updated with
+ * a new meter profile specified in this command.
+ */
+ uint16_t meter_instance_id;
+ uint8_t unused_1[2];
} __attribute__((packed));
-/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
-struct hwrm_cfa_meter_instance_free_output {
+/* hwrm_cfa_meter_instance_cfg_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_cfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -24900,13 +26223,13 @@ struct hwrm_cfa_meter_instance_free_output {
uint8_t valid;
} __attribute__((packed));
-/*******************************
- * hwrm_cfa_decap_filter_alloc *
- *******************************/
+/********************************
+ * hwrm_cfa_meter_instance_free *
+ ********************************/
-/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
-struct hwrm_cfa_decap_filter_alloc_input {
+/* hwrm_cfa_meter_instance_free_input (size:192b/24B) */
+struct hwrm_cfa_meter_instance_free_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -24934,22 +26257,106 @@ struct hwrm_cfa_decap_filter_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* ovs_tunnel is 1 b */
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
- UINT32_C(0x1)
- uint32_t enables;
+ uint8_t flags;
/*
- * This bit must be '1' for the tunnel_type field to be
- * configured.
+ * Enumeration denoting the RX, TX type of the resource.
+ * This enumeration is used for resources that are similar for both
+ * TX and RX paths of the chip.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH UINT32_C(0x1)
+ /* tx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x0)
+ /* rx path */
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX \
UINT32_C(0x1)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_FLAGS_PATH_RX
+ uint8_t unused_0;
+ /* This value identifies a meter instance in CFA. */
+ uint16_t meter_instance_id;
/*
- * This bit must be '1' for the tunnel_id field to be
- * configured.
+ * A value of 0xfff is considered invalid and implies the
+ * instance is not configured.
*/
- #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID \
+ UINT32_C(0xffff)
+ #define HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_LAST \
+ HWRM_CFA_METER_INSTANCE_FREE_INPUT_METER_INSTANCE_ID_INVALID
+ uint8_t unused_1[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_meter_instance_free_output (size:128b/16B) */
+struct hwrm_cfa_meter_instance_free_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************************
+ * hwrm_cfa_decap_filter_alloc *
+ *******************************/
+
+
+/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */
+struct hwrm_cfa_decap_filter_alloc_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* ovs_tunnel is 1 b */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_FLAGS_OVS_TUNNEL \
+ UINT32_C(0x1)
+ uint32_t enables;
+ /*
+ * This bit must be '1' for the tunnel_type field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE \
+ UINT32_C(0x1)
+ /*
+ * This bit must be '1' for the tunnel_id field to be
+ * configured.
+ */
+ #define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_ID \
UINT32_C(0x2)
/*
* This bit must be '1' for the src_macaddr field to be
@@ -25375,6 +26782,9 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \
UINT32_C(0x100)
+ /* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \
+ UINT32_C(0x200)
/*
* Tx Flow: vf fid.
* Rx Flow: pf fid.
@@ -25430,6 +26840,13 @@ struct hwrm_cfa_flow_alloc_input {
/* If set to 1, flow aging is enabled for this flow. */
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \
UINT32_C(0x800)
+ /*
+ * If set to 1 an attempt will be made to try to offload this flow to the
+ * most optimal flow table resource. If set to 0, the flow will be
+ * placed to the default flow table resource.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
+ UINT32_C(0x1000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -25569,7 +26986,8 @@ struct hwrm_cfa_flow_alloc_output {
uint32_t flow_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
- uint8_t unused_1[7];
+ uint32_t flow_counter_id;
+ uint8_t unused_1[3];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25646,6 +27064,229 @@ struct hwrm_cfa_flow_free_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_action_data (size:960b/120B) */
+struct hwrm_cfa_flow_action_data {
+ uint16_t action_flags;
+ /* Setting of this flag indicates accept action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FWD \
+ UINT32_C(0x1)
+ /* Setting of this flag indicates recycle action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_RECYCLE \
+ UINT32_C(0x2)
+ /* Setting of this flag indicates drop action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DROP \
+ UINT32_C(0x4)
+ /* Setting of this flag indicates meter action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_METER \
+ UINT32_C(0x8)
+ /* Setting of this flag indicates tunnel action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \
+ UINT32_C(0x10)
+ /*
+ * If set to 1 and flow direction is TX, it indicates decap of L2 header
+ * and encap of tunnel header. If set to 1 and flow direction is RX, it
+ * indicates decap of tunnel header and encap L2 header.
+ */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \
+ UINT32_C(0x20)
+ /* Setting of this flag indicates ttl decrement action. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TTL_DECREMENT \
+ UINT32_C(0x40)
+ /* If set to 1, flow aging is enabled for this flow. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_FLOW_AGING_ENABLED \
+ UINT32_C(0x80)
+ /* Setting of this flag indicates encap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_ENCAP \
+ UINT32_C(0x100)
+ /* Setting of this flag indicates decap action.. */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_DECAP \
+ UINT32_C(0x200)
+ /* Meter id. */
+ uint16_t act_meter_id;
+ /* VNIC id. */
+ uint16_t vnic_id;
+ /* vport number. */
+ uint16_t vport_id;
+ /* The NAT source/destination. */
+ uint16_t nat_port;
+ uint16_t unused_0[3];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ /* Encapsulation Type. */
+ uint8_t encap_type;
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_NVGRE UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) after inside Ethernet payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2GRE UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPIP UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_GENEVE UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_MPLS UINT32_C(0x6)
+ /* VLAN */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VLAN UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4 UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1 UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)
+ #define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \
+ HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6
+ uint8_t unused[7];
+ /* This value is encap data for the associated encap type. */
+ uint32_t encap_data[20];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_tunnel_hdr_data (size:64b/8B) */
+struct hwrm_cfa_flow_tunnel_hdr_data {
+ /* Tunnel Type. */
+ uint8_t tunnel_type;
+ /* Non-tunnel */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NONTUNNEL \
+ UINT32_C(0x0)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN \
+ UINT32_C(0x1)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_NVGRE \
+ UINT32_C(0x2)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2GRE \
+ UINT32_C(0x3)
+ /* IP in IP */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPIP \
+ UINT32_C(0x4)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_GENEVE \
+ UINT32_C(0x5)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_MPLS \
+ UINT32_C(0x6)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_STT \
+ UINT32_C(0x7)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE \
+ UINT32_C(0x8)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \
+ UINT32_C(0x9)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \
+ UINT32_C(0xa)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \
+ UINT32_C(0xb)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \
+ UINT32_C(0xc)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL \
+ UINT32_C(0xff)
+ #define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_LAST \
+ HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_ANYTUNNEL
+ uint8_t unused[3];
+ /*
+ * Tunnel identifier.
+ * Virtual Network Identifier (VNI).
+ */
+ uint32_t tunnel_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l4_key_data (size:64b/8B) */
+struct hwrm_cfa_flow_l4_key_data {
+ /* The value of source port. */
+ uint16_t l4_src_port;
+ /* The value of destination port. */
+ uint16_t l4_dst_port;
+ uint32_t unused;
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l3_key_data (size:512b/64B) */
+struct hwrm_cfa_flow_l3_key_data {
+ /* The value of ip protocol. */
+ uint8_t ip_protocol;
+ uint8_t unused_0[7];
+ /* The value of destination IPv4/IPv6 address. */
+ uint32_t ip_dst[4];
+ /* The source IPv4/IPv6 address. */
+ uint32_t ip_src[4];
+ /* NAT IPv4/IPv6 address. */
+ uint32_t nat_ip_address[4];
+ uint32_t unused[2];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_l2_key_data (size:448b/56B) */
+struct hwrm_cfa_flow_l2_key_data {
+ /* Destination MAC address. */
+ uint16_t dmac[3];
+ uint16_t unused_0;
+ /* Source MAC address. */
+ uint16_t smac[3];
+ uint16_t unused_1;
+ /* L2 header re-write Destination MAC address. */
+ uint16_t l2_rewrite_dmac[3];
+ uint16_t unused_2;
+ /* L2 header re-write Source MAC address. */
+ uint16_t l2_rewrite_smac[3];
+ /* Ethertype. */
+ uint16_t ethertype;
+ /* Number of VLAN tags. */
+ uint16_t num_vlan_tags;
+ /* VLAN tpid. */
+ uint16_t l2_rewrite_vlan_tpid;
+ /* VLAN tci. */
+ uint16_t l2_rewrite_vlan_tci;
+ uint8_t unused_3[2];
+ /* Outer VLAN TPID. */
+ uint16_t ovlan_tpid;
+ /* Outer VLAN TCI. */
+ uint16_t ovlan_tci;
+ /* Inner VLAN TPID. */
+ uint16_t ivlan_tpid;
+ /* Inner VLAN TCI. */
+ uint16_t ivlan_tci;
+ uint8_t unused[8];
+} __attribute__((packed));
+
+/* hwrm_cfa_flow_key_data (size:4160b/520B) */
+struct hwrm_cfa_flow_key_data {
+ /* Flow associated tunnel L2 header key info. */
+ uint32_t t_l2_key_data[14];
+ /* Flow associated tunnel L2 header mask info. */
+ uint32_t t_l2_key_mask[14];
+ /* Flow associated tunnel L3 header key info. */
+ uint32_t t_l3_key_data[16];
+ /* Flow associated tunnel L3 header mask info. */
+ uint32_t t_l3_key_mask[16];
+ /* Flow associated tunnel L4 header key info. */
+ uint32_t t_l4_key_data[2];
+ /* Flow associated tunnel L4 header mask info. */
+ uint32_t t_l4_key_mask[2];
+ /* Flow associated tunnel header info. */
+ uint32_t tunnel_hdr[2];
+ /* Flow associated L2 header key info. */
+ uint32_t l2_key_data[14];
+ /* Flow associated L2 header mask info. */
+ uint32_t l2_key_mask[14];
+ /* Flow associated L3 header key info. */
+ uint32_t l3_key_data[16];
+ /* Flow associated L3 header mask info. */
+ uint32_t l3_key_mask[16];
+ /* Flow associated L4 header key info. */
+ uint32_t l4_key_data[2];
+ /* Flow associated L4 header mask info. */
+ uint32_t l4_key_mask[2];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_info *
**********************/
@@ -25703,7 +27344,7 @@ struct hwrm_cfa_flow_info_input {
uint64_t ext_flow_handle;
} __attribute__((packed));
-/* hwrm_cfa_flow_info_output (size:448b/56B) */
+/* hwrm_cfa_flow_info_output (size:5632b/704B) */
struct hwrm_cfa_flow_info_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -25713,8 +27354,11 @@ struct hwrm_cfa_flow_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* flags is 8 b */
uint8_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_FLOW_INFO_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
/* profile is 8 b */
uint8_t profile;
/* src_fid is 16 b */
@@ -25737,7 +27381,12 @@ struct hwrm_cfa_flow_info_output {
uint32_t tunnel_handle;
/* The flow aging timer for the flow, the unit is 100 milliseconds */
uint16_t flow_timer;
- uint8_t unused_0[5];
+ uint8_t unused_0[6];
+ /* Flow associated L2, L3 and L4 headers info. */
+ uint32_t flow_key_data[130];
+ /* Flow associated action record info. */
+ uint32_t flow_action_info[30];
+ uint8_t unused_1[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -25753,7 +27402,7 @@ struct hwrm_cfa_flow_info_output {
***********************/
-/* hwrm_cfa_flow_flush_input (size:192b/24B) */
+/* hwrm_cfa_flow_flush_input (size:256b/32B) */
struct hwrm_cfa_flow_flush_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -25782,8 +27431,73 @@ struct hwrm_cfa_flow_flush_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
+ /* flags is 32 b */
uint32_t flags;
- uint8_t unused_0[4];
+ /*
+ * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr
+ * fields are valid. The flow flush operation should only flush the flows from the
+ * flow table specified. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \
+ UINT32_C(0x1)
+ /*
+ * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA
+ * context memory tables..etc. This flag is set to 0 by older driver. For older firmware,
+ * setting this flag has no effect.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
+ UINT32_C(0x2)
+ /*
+ * This specifies the size of flow handle entries provided by the driver
+ * in the flow table specified below. Only two flow handle size enums are defined.
+ */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \
+ UINT32_C(0xc0000000)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_SFT \
+ 30
+ /* The flow handle is 16bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_16BIT \
+ (UINT32_C(0x0) << 30)
+ /* The flow handle is 64bit */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_FLOW_HND_64BIT
+ /* Specify page size of the flow table memory. */
+ uint8_t page_size;
+ /* The page size is 4K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* The page size is 8K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* The page size is 64K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* The page size is 256K */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* The page size is 1M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* The page size is 2M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* The page size is 4M */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* The page size is 1G */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_SIZE_1G
+ /* FLow table memory indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2
+ /* number of flows in the flow table */
+ uint16_t num_flows;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
} __attribute__((packed));
/* hwrm_cfa_flow_flush_output (size:128b/16B) */
@@ -25983,7 +27697,12 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint8_t unused_0[2];
+ /*
+ * New flow timer value for the flow specified in the ext_flow_handle.
+ * The flow timer unit is 100ms.
+ */
+ uint32_t flow_timer;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -26244,13 +27963,13 @@ struct hwrm_cfa_flow_aging_qcaps_output {
uint8_t valid;
} __attribute__((packed));
-/**********************
- * hwrm_cfa_pair_info *
- **********************/
+/**********************************
+ * hwrm_cfa_tcp_flag_process_qcfg *
+ **********************************/
-/* hwrm_cfa_pair_info_input (size:448b/56B) */
-struct hwrm_cfa_pair_info_input {
+/* hwrm_cfa_tcp_flag_process_qcfg_input (size:128b/16B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26278,23 +27997,10 @@ struct hwrm_cfa_pair_info_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- uint32_t flags;
- /* If this flag is set, lookup by name else lookup by index. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
- /* If this flag is set, lookup by PF id and VF id. */
- #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
- /* Pair table index. */
- uint16_t pair_index;
- /* Pair pf index. */
- uint8_t pair_pfid;
- /* Pair vf index. */
- uint8_t pair_vfid;
- /* Pair name (32 byte string). */
- char pair_name[32];
} __attribute__((packed));
-/* hwrm_cfa_pair_info_output (size:576b/72B) */
-struct hwrm_cfa_pair_info_output {
+/* hwrm_cfa_tcp_flag_process_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_tcp_flag_process_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26303,22 +28009,100 @@ struct hwrm_cfa_pair_info_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Pair table index. */
- uint16_t next_pair_index;
- /* Pair member a's fid. */
- uint16_t a_fid;
- /* Logical host number. */
- uint8_t host_a_index;
- /* Logical PF number. */
- uint8_t pf_a_index;
- /* Pair member a's Linux logical VF number. */
- uint16_t vf_a_index;
- /* Rx CFA code. */
- uint16_t rx_cfa_code_a;
- /* Tx CFA action. */
- uint16_t tx_cfa_action_a;
- /* Pair member b's fid. */
- uint16_t b_fid;
+ /* The port 0 RX mirror action record ID. */
+ uint16_t rx_ar_id_port0;
+ /* The port 1 RX mirror action record ID. */
+ uint16_t rx_ar_id_port1;
+ /* The port 0 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port0;
+ /* The port 1 RX action record ID for TX TCP flag packets from loopback path. */
+ uint16_t tx_ar_id_port1;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_pair_info *
+ **********************/
+
+
+/* hwrm_cfa_pair_info_input (size:448b/56B) */
+struct hwrm_cfa_pair_info_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /* If this flag is set, lookup by name else lookup by index. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_TYPE UINT32_C(0x1)
+ /* If this flag is set, lookup by PF id and VF id. */
+ #define HWRM_CFA_PAIR_INFO_INPUT_FLAGS_LOOKUP_REPRE UINT32_C(0x2)
+ /* Pair table index. */
+ uint16_t pair_index;
+ /* Pair pf index. */
+ uint8_t pair_pfid;
+ /* Pair vf index. */
+ uint8_t pair_vfid;
+ /* Pair name (32 byte string). */
+ char pair_name[32];
+} __attribute__((packed));
+
+/* hwrm_cfa_pair_info_output (size:576b/72B) */
+struct hwrm_cfa_pair_info_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Pair table index. */
+ uint16_t next_pair_index;
+ /* Pair member a's fid. */
+ uint16_t a_fid;
+ /* Logical host number. */
+ uint8_t host_a_index;
+ /* Logical PF number. */
+ uint8_t pf_a_index;
+ /* Pair member a's Linux logical VF number. */
+ uint16_t vf_a_index;
+ /* Rx CFA code. */
+ uint16_t rx_cfa_code_a;
+ /* Tx CFA action. */
+ uint16_t tx_cfa_action_a;
+ /* Pair member b's fid. */
+ uint16_t b_fid;
/* Logical host number. */
uint8_t host_b_index;
/* Logical PF number. */
@@ -26364,13 +28148,645 @@ struct hwrm_cfa_pair_info_output {
uint8_t valid;
} __attribute__((packed));
-/***************************************
- * hwrm_cfa_redirect_query_tunnel_type *
- ***************************************/
+/***************************************
+ * hwrm_cfa_redirect_query_tunnel_type *
+ ***************************************/
+
+
+/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
+struct hwrm_cfa_redirect_query_tunnel_type_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* The source function id. */
+ uint16_t src_fid;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
+struct hwrm_cfa_redirect_query_tunnel_type_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Tunnel Mask. */
+ uint32_t tunnel_mask;
+ /* Non-tunnel */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ UINT32_C(0x1)
+ /* Virtual eXtensible Local Area Network (VXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ UINT32_C(0x2)
+ /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ UINT32_C(0x4)
+ /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ UINT32_C(0x8)
+ /* IP in IP */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ UINT32_C(0x10)
+ /* Generic Network Virtualization Encapsulation (Geneve) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ UINT32_C(0x20)
+ /* Multi-Protocol Lable Switching (MPLS) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ UINT32_C(0x40)
+ /* Stateless Transport Tunnel (STT) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
+ UINT32_C(0x80)
+ /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
+ UINT32_C(0x100)
+ /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
+ UINT32_C(0x200)
+ /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
+ UINT32_C(0x400)
+ /* Any tunneled traffic */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
+ UINT32_C(0x800)
+ /* Use fixed layer 2 ether type of 0xFFFF */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
+ UINT32_C(0x1000)
+ /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
+ #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
+ UINT32_C(0x2000)
+ uint8_t unused_0[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_rgtr *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_rgtr_input (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_rgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_SIZE_1G
+ uint32_t unused_0;
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_rgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_rgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[5];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/***************************
+ * hwrm_cfa_ctx_mem_unrgtr *
+ ***************************/
+
+
+/* hwrm_cfa_ctx_mem_unrgtr_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_unrgtr_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_unrgtr_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_unrgtr_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*************************
+ * hwrm_cfa_ctx_mem_qctx *
+ *************************/
+
+
+/* hwrm_cfa_ctx_mem_qctx_input (size:192b/24B) */
+struct hwrm_cfa_ctx_mem_qctx_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /*
+ * Id/Handle to the recently register context memory. This handle is passed
+ * to the CFA feature.
+ */
+ uint16_t ctx_id;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qctx_output (size:256b/32B) */
+struct hwrm_cfa_ctx_mem_qctx_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint16_t flags;
+ /* Counter PBL indirect levels. */
+ uint8_t page_level;
+ /* PBL pointer is physical start address. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)
+ /* PBL pointer points to PTE table. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)
+ /* PBL pointer points to PDE table with each entry pointing to PTE tables. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2
+ /* Page size. */
+ uint8_t page_size;
+ /* 4KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4K UINT32_C(0x0)
+ /* 8KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_8K UINT32_C(0x1)
+ /* 64KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_64K UINT32_C(0x4)
+ /* 256KB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_256K UINT32_C(0x6)
+ /* 1MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1M UINT32_C(0x8)
+ /* 2MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_2M UINT32_C(0x9)
+ /* 4MB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_4M UINT32_C(0xa)
+ /* 1GB page size. */
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G UINT32_C(0x12)
+ #define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_LAST \
+ HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_SIZE_1G
+ uint8_t unused_0[4];
+ /* Pointer to the PBL, or PDL depending on number of levels */
+ uint64_t page_dir;
+ uint8_t unused_1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/**************************
+ * hwrm_cfa_ctx_mem_qcaps *
+ **************************/
+
+
+/* hwrm_cfa_ctx_mem_qcaps_input (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+} __attribute__((packed));
+
+/* hwrm_cfa_ctx_mem_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_ctx_mem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Indicates the maximum number of context memory which can be registered. */
+ uint16_t max_entries;
+ uint8_t unused_0[6];
+} __attribute__((packed));
+
+/**********************
+ * hwrm_cfa_eem_qcaps *
+ **********************/
+
+
+/* hwrm_cfa_eem_qcaps_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_qcaps_output (size:256b/32B) */
+struct hwrm_cfa_eem_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
+ uint32_t supported;
+ /*
+ * If set to 1, then EEM KEY0 table is supported using crc32 hash.
+ * If set to 0 EEM KEY0 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY0_TABLE \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, then EEM KEY1 table is supported using lookup3 hash.
+ * If set to 0 EEM KEY1 table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_KEY1_TABLE \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, then EEM External Record table is supported.
+ * If set to 0 EEM External Record table is not supported.
+ * (This table includes action record, EFC pointers, encap pointers)
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_RECORD_TABLE \
+ UINT32_C(0x4)
+ /*
+ * If set to 1, then EEM External Flow Counters table is supported.
+ * If set to 0 EEM External Flow Counters table is not supported.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \
+ UINT32_C(0x8)
+ /*
+ * The maximum number of entries supported by EEM. When configuring the host memory
+ * the number of numbers of entries that can supported are -
+ * 32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.
+ * Any value that are not these values, the FW will round down to the closest support
+ * number of entries.
+ */
+ uint32_t max_entries_supported;
+ /* The entry size in bytes of each entry in the KEY0/KEY1 EEM tables. */
+ uint16_t key_entry_size;
+ /* The entry size in bytes of each entry in the RECORD EEM tables. */
+ uint16_t record_entry_size;
+ /* The entry size in bytes of each entry in the EFC EEM tables. */
+ uint16_t efc_entry_size;
+ uint8_t unused_1;
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************
+ * hwrm_cfa_eem_cfg *
+ ********************/
+
+
+/* hwrm_cfa_eem_cfg_input (size:320b/40B) */
+struct hwrm_cfa_eem_cfg_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the configuration will apply to TX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the configuration will apply to RX flows
+ * which are to be offloaded.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
+ UINT32_C(0x4)
+ uint32_t unused_0;
+ /*
+ * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
+ * RECORD, EFC all have the same number of entries and all tables will be configured
+ * using this value. Current minimum value is 32k. Current maximum value is 128M.
+ */
+ uint32_t num_entries;
+ uint32_t unused_1;
+ /* Configured EEM with the given context if for KEY0 table. */
+ uint16_t key0_ctx_id;
+ /* Configured EEM with the given context if for KEY1 table. */
+ uint16_t key1_ctx_id;
+ /* Configured EEM with the given context if for RECORD table. */
+ uint16_t record_ctx_id;
+ /* Configured EEM with the given context if for EFC table. */
+ uint16_t efc_ctx_id;
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_cfg_output (size:128b/16B) */
+struct hwrm_cfa_eem_cfg_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*********************
+ * hwrm_cfa_eem_qcfg *
+ *********************/
-/* hwrm_cfa_redirect_query_tunnel_type_input (size:192b/24B) */
-struct hwrm_cfa_redirect_query_tunnel_type_input {
+/* hwrm_cfa_eem_qcfg_input (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_input {
/* The HWRM command request type. */
uint16_t req_type;
/*
@@ -26398,13 +28814,16 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* The source function id. */
- uint16_t src_fid;
- uint8_t unused_0[6];
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint32_t unused_0;
} __attribute__((packed));
-/* hwrm_cfa_redirect_query_tunnel_type_output (size:128b/16B) */
-struct hwrm_cfa_redirect_query_tunnel_type_output {
+/* hwrm_cfa_eem_qcfg_output (size:192b/24B) */
+struct hwrm_cfa_eem_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
/* The HWRM command request type. */
@@ -26413,50 +28832,219 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {
uint16_t seq_id;
/* The length of the response data in number of bytes. */
uint16_t resp_len;
- /* Tunnel Mask. */
- uint32_t tunnel_mask;
- /* Non-tunnel */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NONTUNNEL \
+ uint32_t flags;
+ /* When set to 1, indicates the configuration is the TX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_TX \
UINT32_C(0x1)
- /* Virtual eXtensible Local Area Network (VXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN \
+ /* When set to 1, indicates the configuration is the RX flow. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PATH_RX \
UINT32_C(0x2)
- /* Network Virtualization Generic Routing Encapsulation (NVGRE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_NVGRE \
+ /* When set to 1, all offloaded flows will be sent to EEM. */
+ #define HWRM_CFA_EEM_QCFG_OUTPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- /* Generic Routing Encapsulation (GRE) inside Ethernet payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2GRE \
+ /* The number of entries the FW has configured for EEM. */
+ uint32_t num_entries;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/*******************
+ * hwrm_cfa_eem_op *
+ *******************/
+
+
+/* hwrm_cfa_eem_op_input (size:192b/24B) */
+struct hwrm_cfa_eem_op_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t flags;
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the TX flow offload function specified in fid.
+ * Note if this bit is set then the path_rx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ /*
+ * When set to 1, indicates the host memory which is passed will be
+ * used for the RX flow offload function specified in fid.
+ * Note if this bit is set then the path_tx bit can't be set.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ uint16_t unused_0;
+ /* The number of EEM key table entries to be configured. */
+ uint16_t op;
+ /* This value is reserved and should not be used. */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_RESERVED UINT32_C(0x0)
+ /*
+ * To properly stop EEM and ensure there are no DMA's, the caller
+ * must disable EEM for the given PF, using this call. This will
+ * safely disable EEM and ensure that all DMA'ed to the
+ * keys/records/efc have been completed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_DISABLE UINT32_C(0x1)
+ /*
+ * Once the EEM host memory has been configured, EEM options have
+ * been configured. Then the caller should enable EEM for the given
+ * PF. Note once this call has been made, then the EEM mechanism
+ * will be active and DMA's will occur as packets are processed.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_ENABLE UINT32_C(0x2)
+ /*
+ * Clear EEM settings for the given PF so that the register values
+ * are reset back to there initial state.
+ */
+ #define HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP UINT32_C(0x3)
+ #define HWRM_CFA_EEM_OP_INPUT_OP_LAST \
+ HWRM_CFA_EEM_OP_INPUT_OP_EEM_CLEANUP
+} __attribute__((packed));
+
+/* hwrm_cfa_eem_op_output (size:128b/16B) */
+struct hwrm_cfa_eem_op_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint8_t unused_0[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
+/********************************
+ * hwrm_cfa_adv_flow_mgnt_qcaps *
+ ********************************/
+
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_input (size:256b/32B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ uint32_t unused_0[4];
+} __attribute__((packed));
+
+/* hwrm_cfa_adv_flow_mgnt_qcaps_output (size:128b/16B) */
+struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ uint32_t flags;
+ /*
+ * Value of 1 to indicate firmware support 16-bit flow handle.
+ * Value of 0 to indicate firmware not support 16-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_16BIT_SUPPORTED \
+ UINT32_C(0x1)
+ /*
+ * Value of 1 to indicate firmware support 64-bit flow handle.
+ * Value of 0 to indicate firmware not support 64-bit flow handle.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \
+ UINT32_C(0x2)
+ /*
+ * Value of 1 to indicate firmware support flow batch delete operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 to indicate that the firmware does not support flow batch delete
+ * operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * Value of 1 to indicate that the firmware support flow reset all operation through
+ * HWRM_CFA_FLOW_FLUSH command.
+ * Value of 0 indicates firmware does not support flow reset all operation.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \
UINT32_C(0x8)
- /* IP in IP */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPIP \
+ /*
+ * Value of 1 to indicate that firmware supports use of FID as dest_id in
+ * HWRM_CFA_NTUPLE_ALLOC/CFG commands.
+ * Value of 0 indicates firmware does not support use of FID as dest_id.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \
UINT32_C(0x10)
- /* Generic Network Virtualization Encapsulation (Geneve) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_GENEVE \
+ /*
+ * Value of 1 to indicate that firmware supports TX EEM flows.
+ * Value of 0 indicates firmware does not support TX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TX_EEM_FLOW_SUPPORTED \
UINT32_C(0x20)
- /* Multi-Protocol Lable Switching (MPLS) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_MPLS \
+ /*
+ * Value of 1 to indicate that firmware supports RX EEM flows.
+ * Value of 0 indicates firmware does not support RX EEM flows.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
- /* Stateless Transport Tunnel (STT) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_STT \
- UINT32_C(0x80)
- /* Generic Routing Encapsulation (GRE) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE \
- UINT32_C(0x100)
- /* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \
- UINT32_C(0x200)
- /* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \
- UINT32_C(0x400)
- /* Any tunneled traffic */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_ANYTUNNEL \
- UINT32_C(0x800)
- /* Use fixed layer 2 ether type of 0xFFFF */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \
- UINT32_C(0x1000)
- /* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */
- #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \
- UINT32_C(0x2000)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -26874,7 +29462,11 @@ struct hwrm_stat_ctx_alloc_input {
* point to a physically contiguous block of memory.
*/
uint64_t resp_addr;
- /* This is the address for statistic block. */
+ /*
+ * This is the address for statistic block.
+ * > For new versions of the chip, this address should be 128B
+ * > aligned.
+ */
uint64_t stats_dma_addr;
/*
* The statistic block update period in ms.
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* [dpdk-dev] [PATCH v5 8/8] net/bnxt: update HWRM API to version 1.10.0.74
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
` (6 preceding siblings ...)
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 7/8] net/bnxt: update HWRM API to version 1.10.0.48 Lance Richardson
@ 2019-05-29 21:02 ` Lance Richardson
2019-06-04 16:07 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Ferruh Yigit
8 siblings, 0 replies; 75+ messages in thread
From: Lance Richardson @ 2019-05-29 21:02 UTC (permalink / raw)
To: dev
Cc: ajit.khaparde, ferruh.yigit, maxime.coquelin, ktraynor, Lance Richardson
From: Ajit Khaparde <ajit.khaparde@broadcom.com>
Update HWRM API to version 1.10.0.74
Signed-off-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: Lance Richardson <lance.richardson@broadcom.com>
Signed-off-by: Lance Richardson <lance.richardson@broadcom.com>
---
v3:
* Fixed headline in commit log.
doc/guides/rel_notes/release_19_08.rst | 1 +
drivers/net/bnxt/hsi_struct_def_dpdk.h | 1399 ++++++++++++++++++++----
2 files changed, 1169 insertions(+), 231 deletions(-)
diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 7e5ca3c34..ea8fbcdfd 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -59,6 +59,7 @@ New Features
Updated the bnxt PMD. The major enhancements include:
* Performance optimizations in non-vector Tx path
* Added support for SSE vector mode
+ * Updated HWRM API to version 1.10.0.74
Removed Items
-------------
diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h
index 00a8ff87e..305ee09bc 100644
--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h
+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright (c) 2014-2019 Broadcom Limited
+ * Copyright (c) 2014-2019 Broadcom Inc.
* All rights reserved.
*
* DO NOT MODIFY!!! This file is automatically generated.
@@ -27,7 +27,8 @@ struct hwrm_cmd_hdr {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -221,8 +222,14 @@ struct hwrm_short_input {
#define HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD UINT32_C(0x4321)
#define HWRM_SHORT_INPUT_SIGNATURE_LAST \
HWRM_SHORT_INPUT_SIGNATURE_SHORT_CMD
- /* Reserved for future use. */
- uint16_t unused_0;
+ /* The target ID of the command */
+ uint16_t target_id;
+ /* Default target_id (0x0) to maintain compatibility with old driver */
+ #define HWRM_SHORT_INPUT_TARGET_ID_DEFAULT UINT32_C(0x0)
+ /* Reserved for user-space HWRM interface */
+ #define HWRM_SHORT_INPUT_TARGET_ID_TOOLS UINT32_C(0xfffd)
+ #define HWRM_SHORT_INPUT_TARGET_ID_LAST \
+ HWRM_SHORT_INPUT_TARGET_ID_TOOLS
/* This value indicates the length of the request. */
uint16_t size;
/*
@@ -394,6 +401,8 @@ struct cmd_nums {
#define HWRM_FWD_RESP UINT32_C(0xd2)
#define HWRM_FWD_ASYNC_EVENT_CMPL UINT32_C(0xd3)
#define HWRM_OEM_CMD UINT32_C(0xd4)
+ /* Tells the fw to run PRBS test on a given port and lane. */
+ #define HWRM_PORT_PRBS_TEST UINT32_C(0xd5)
#define HWRM_TEMP_MONITOR_QUERY UINT32_C(0xe0)
#define HWRM_WOL_FILTER_ALLOC UINT32_C(0xf0)
#define HWRM_WOL_FILTER_FREE UINT32_C(0xf1)
@@ -486,6 +495,8 @@ struct cmd_nums {
#define HWRM_CFA_EEM_OP UINT32_C(0x123)
/* Experimental */
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS UINT32_C(0x124)
+ /* Experimental */
+ #define HWRM_CFA_TFLIB UINT32_C(0x125)
/* Engine CKV - Ping the device and SRT firmware to get the public key. */
#define HWRM_ENGINE_CKV_HELLO UINT32_C(0x12d)
/* Engine CKV - Get the current allocation status of keys provisioned in the key vault. */
@@ -506,6 +517,8 @@ struct cmd_nums {
#define HWRM_ENGINE_CKV_KEY_GEN UINT32_C(0x135)
/* Engine CKV - Configure a label index with a label value. */
#define HWRM_ENGINE_CKV_KEY_LABEL_CFG UINT32_C(0x136)
+ /* Engine CKV - Query a label */
+ #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG UINT32_C(0x137)
/* Engine - Query the available queue groups configuration. */
#define HWRM_ENGINE_QG_CONFIG_QUERY UINT32_C(0x13c)
/* Engine - Query the queue groups assigned to a function. */
@@ -587,6 +600,19 @@ struct cmd_nums {
/* Experimental */
#define HWRM_PCIE_QSTATS UINT32_C(0x204)
/* Experimental */
+ #define HWRM_MFG_FRU_WRITE_CONTROL UINT32_C(0x205)
+ /* Returns the current value of a free running counter from the device. */
+ #define HWRM_MFG_TIMERS_QUERY UINT32_C(0x206)
+ /* Experimental */
+ #define HWRM_MFG_OTP_CFG UINT32_C(0x207)
+ /* Experimental */
+ #define HWRM_MFG_OTP_QCFG UINT32_C(0x208)
+ /*
+ * Tells the fw to run the DMA read from the host and DMA write
+ * to the host test.
+ */
+ #define HWRM_MFG_HDMA_TEST UINT32_C(0x209)
+ /* Experimental */
#define HWRM_DBG_READ_DIRECT UINT32_C(0xff10)
/* Experimental */
#define HWRM_DBG_READ_INDIRECT UINT32_C(0xff11)
@@ -643,67 +669,85 @@ struct cmd_nums {
struct ret_codes {
uint16_t error_code;
/* Request was successfully executed by the HWRM. */
- #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
+ #define HWRM_ERR_CODE_SUCCESS UINT32_C(0x0)
/* The HWRM failed to execute the request. */
- #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
+ #define HWRM_ERR_CODE_FAIL UINT32_C(0x1)
/*
* The request contains invalid argument(s) or input
* parameters.
*/
- #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
+ #define HWRM_ERR_CODE_INVALID_PARAMS UINT32_C(0x2)
/*
* The requester is not allowed to access the requested
* resource. This error code shall be provided in a
* response to a request to query or modify an existing
* resource that is not accessible by the requester.
*/
- #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
+ #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED UINT32_C(0x3)
/*
* The HWRM is unable to allocate the requested resource.
* This code only applies to requests for HWRM resource
* allocations.
*/
- #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
+ #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR UINT32_C(0x4)
/*
* Invalid combination of flags is specified in the
* request.
*/
- #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
+ #define HWRM_ERR_CODE_INVALID_FLAGS UINT32_C(0x5)
/*
* Invalid combination of enables fields is specified in
* the request.
*/
- #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
+ #define HWRM_ERR_CODE_INVALID_ENABLES UINT32_C(0x6)
/*
* Request contains a required TLV that is not supported by
* the installed version of firmware.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
+ #define HWRM_ERR_CODE_UNSUPPORTED_TLV UINT32_C(0x7)
/*
* No firmware buffer available to accept the request. Driver
* should retry the request.
*/
- #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
+ #define HWRM_ERR_CODE_NO_BUFFER UINT32_C(0x8)
/*
* This error code is only reported by firmware when some
* sub-option of a supported HWRM command is unsupported.
*/
- #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
+ #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR UINT32_C(0x9)
/*
* This error code is only reported by firmware when the specific
* request is not able to process when the HOT reset in progress.
*/
- #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
+ #define HWRM_ERR_CODE_HOT_RESET_PROGRESS UINT32_C(0xa)
/*
* This error code is only reported by firmware when the registered
* driver instances are not capable of hot reset.
*/
- #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ #define HWRM_ERR_CODE_HOT_RESET_FAIL UINT32_C(0xb)
+ /*
+ * This error code is only reported by the firmware when during
+ * flow allocation when a requeest for a flow counter fails because
+ * the number of flow counters are exhausted.
+ */
+ #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC UINT32_C(0xc)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the requested key's hash collides with the installed keys.
+ */
+ #define HWRM_ERR_CODE_KEY_HASH_COLLISION UINT32_C(0xd)
+ /*
+ * This error code is only reported by firmware when the registered
+ * driver instances requested to offloaded a flow but was unable to because
+ * the same key has already been installed.
+ */
+ #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS UINT32_C(0xe)
/*
* Generic HWRM execution error that represents an
* internal error.
*/
- #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
+ #define HWRM_ERR_CODE_HWRM_ERROR UINT32_C(0xf)
/*
* This value indicates that the HWRM response is in TLV format and
* should be interpreted as one or more TLVs starting with the
@@ -711,11 +755,11 @@ struct ret_codes {
* by itself, just an indicatation that the response should be parsed
* as TLV and the actual error code will be in the hwrm_resp_hdr TLV.
*/
- #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
+ #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE UINT32_C(0x8000)
/* Unknown error */
- #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
+ #define HWRM_ERR_CODE_UNKNOWN_ERR UINT32_C(0xfffe)
/* Unsupported or invalid command */
- #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
+ #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED UINT32_C(0xffff)
#define HWRM_ERR_CODE_LAST \
HWRM_ERR_CODE_CMD_NOT_SUPPORTED
uint16_t unused_0[3];
@@ -774,12 +818,25 @@ struct hwrm_err_output {
#define HW_HASH_KEY_SIZE 40
/* valid key for HWRM response */
#define HWRM_RESP_VALID_KEY 1
+/* Reserved for BONO processor */
+#define HWRM_TARGET_ID_BONO 0xFFF8
+/* Reserved for KONG processor */
+#define HWRM_TARGET_ID_KONG 0xFFF9
+/* Reserved for APE processor */
+#define HWRM_TARGET_ID_APE 0xFFFA
+/*
+ * This value will be used by tools for User-space HWRM Interface.
+ * When tool execute any HWRM command with this target_id, firmware
+ * will copy the response and/or data payload via register space instead
+ * of DMAing it.
+ */
+#define HWRM_TARGET_ID_TOOLS 0xFFFD
#define HWRM_VERSION_MAJOR 1
#define HWRM_VERSION_MINOR 10
#define HWRM_VERSION_UPDATE 0
/* non-zero means beta version */
-#define HWRM_VERSION_RSVD 48
-#define HWRM_VERSION_STR "1.10.0.48"
+#define HWRM_VERSION_RSVD 74
+#define HWRM_VERSION_STR "1.10.0.74"
/****************
* hwrm_ver_get *
@@ -804,7 +861,8 @@ struct hwrm_ver_get_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -1062,6 +1120,13 @@ struct hwrm_ver_get_output {
*/
#define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED \
UINT32_C(0x1000)
+ /*
+ * If set to 1, the firmware is able to support TFLIB features.
+ * If set to 0, then the firmware doesn’t support TFLIB features.
+ * By default, this flag should be 0 for older version of core firmware.
+ */
+ #define HWRM_VER_GET_OUTPUT_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED \
+ UINT32_C(0x2000)
/*
* This field represents the major version of RoCE firmware.
* A change in major version represents a major release.
@@ -1099,12 +1164,8 @@ struct hwrm_ver_get_output {
* firmware (ASCII chars with NULL at the end).
*/
char netctrl_fw_name[16];
- /*
- * This field is reserved for future use.
- * The responder should set it to 0.
- * The requester should ignore this field.
- */
- uint8_t reserved2[16];
+ /* This field represents the active board package name. */
+ char active_pkg_name[16];
/*
* This field represents the name of RoCE FW (ASCII chars
* with NULL at the end).
@@ -3845,6 +3906,12 @@ struct hwrm_async_event_cmpl {
*/
#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE \
UINT32_C(0x3c)
+ /* TFLIB unique default VNIC Configuration Change */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE \
+ UINT32_C(0x3d)
+ /* TFLIB unique link status changed */
+ #define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE \
+ UINT32_C(0x3e)
/*
* A trace log message. This contains firmware trace logs string
* embedded in the asynchronous message. This is an experimental
@@ -5859,7 +5926,8 @@ struct hwrm_func_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -5962,7 +6030,8 @@ struct hwrm_func_getfid_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6038,7 +6107,8 @@ struct hwrm_func_vf_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6110,7 +6180,8 @@ struct hwrm_func_vf_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6183,7 +6254,8 @@ struct hwrm_func_vf_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6446,7 +6518,8 @@ struct hwrm_func_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -6663,6 +6736,13 @@ struct hwrm_func_qcaps_output {
*/
#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_ERROR_RECOVERY_CAPABLE \
UINT32_C(0x800000)
+ /*
+ * If the query is for a VF, then this flag shall be ignored.
+ * If this query is for a PF and this flag is set to 1, then
+ * the PF has the capability to support extended stats.
+ */
+ #define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_STATS_SUPPORTED \
+ UINT32_C(0x1000000)
/*
* This value is current MAC address configured for this
* function. A value of 00-00-00-00-00-00 indicates no
@@ -6807,7 +6887,8 @@ struct hwrm_func_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7247,7 +7328,8 @@ struct hwrm_func_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -7889,7 +7971,8 @@ struct hwrm_func_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8014,7 +8097,8 @@ struct hwrm_func_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8078,7 +8162,8 @@ struct hwrm_func_vf_resc_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8141,7 +8226,8 @@ struct hwrm_func_drv_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8382,7 +8468,8 @@ struct hwrm_func_drv_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8447,7 +8534,8 @@ struct hwrm_func_buf_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8581,7 +8669,8 @@ struct hwrm_func_buf_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8650,7 +8739,8 @@ struct hwrm_func_drv_qver_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8757,7 +8847,8 @@ struct hwrm_func_resource_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8886,7 +8977,8 @@ struct hwrm_func_backing_store_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -8973,7 +9065,10 @@ struct hwrm_func_backing_store_qcaps_output {
* the backing store.
*/
uint32_t tqm_max_entries_per_ring;
- /* Maximum number of MR/AV context entries supported for this function. */
+ /*
+ * Maximum number of MR plus AV context entries supported for this
+ * function.
+ */
uint32_t mrav_max_entries;
/* Number of bytes that must be allocated for each context entry. */
uint16_t mrav_entry_size;
@@ -8981,7 +9076,22 @@ struct hwrm_func_backing_store_qcaps_output {
uint16_t tim_entry_size;
/* Maximum number of Timer context entries supported for this function. */
uint32_t tim_max_entries;
- uint8_t unused_0[2];
+ /*
+ * When this field is zero, the 32b `mrav_num_entries` field in the
+ * `backing_store_cfg` and `backing_store_qcfg` commands represents
+ * the total number of MR plus AV entries allowed in the MR/AV backing
+ * store PBL.
+ *
+ * When this field is non-zero, the 32b `mrav_num_entries` field in
+ * the `backing_store_cfg` and `backing_store_qcfg` commands is
+ * logically divided into two 16b fields. Bits `[31:16]` represents
+ * the `mr_num_entries` and bits `[15:0]` represents `av_num_entries`.
+ * Both of these values are represented in a unit granularity
+ * specified by this field. For example, if this field is 16 and
+ * `mrav_num_entries` is `0x02000100`, then the number of MR entries
+ * is 8192 and the number of AV entries is 4096.
+ */
+ uint16_t mrav_num_entries_units;
/*
* The number of entries specified for any TQM ring must be a
* multiple of this value to prevent any resource allocation
@@ -9021,7 +9131,8 @@ struct hwrm_func_backing_store_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -9041,6 +9152,12 @@ struct hwrm_func_backing_store_cfg_input {
*/
#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_CFG_INPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint32_t enables;
/*
* This bit must be '1' for the qp fields to be
@@ -9958,7 +10075,20 @@ struct hwrm_func_backing_store_cfg_input {
* the backing store.
*/
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10036,7 +10166,8 @@ struct hwrm_func_backing_store_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -10068,6 +10199,12 @@ struct hwrm_func_backing_store_qcfg_output {
*/
#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_PREBOOT_MODE \
UINT32_C(0x1)
+ /*
+ * When set, the 32b `mrav_num_entries` field is logically divided
+ * into two 16b fields, `mr_num_entries` and `av_num_entries`.
+ */
+ #define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \
+ UINT32_C(0x2)
uint8_t unused_0[4];
/*
* This bit must be '1' for the qp fields to be
@@ -10891,7 +11028,20 @@ struct hwrm_func_backing_store_qcfg_output {
uint32_t tqm_ring6_num_entries;
/* Number of TQM ring 7 entries. */
uint32_t tqm_ring7_num_entries;
- /* Number of MR/AV entries. */
+ /*
+ * If the MR/AV split reservation flag is not set, then this field
+ * represents the total number of MR plus AV entries. For versions
+ * of firmware that support the split reservation, when it is not
+ * specified half of the entries will be reserved for MRs and the
+ * other half for AVs.
+ *
+ * If the MR/AV split reservation flag is set, then this
+ * field is logically divided into two 16b fields. Bits `[31:16]`
+ * represents the `mr_num_entries` and bits `[15:0]` represents
+ * `av_num_entries`. The granularity of these values is defined by
+ * the `mrav_num_entries_unit` field returned by the
+ * `backing_store_qcaps` command.
+ */
uint32_t mrav_num_entries;
/* Number of Timer entries. */
uint32_t tim_num_entries;
@@ -10930,7 +11080,8 @@ struct hwrm_error_recovery_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11296,7 +11447,8 @@ struct hwrm_func_vlan_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11386,7 +11538,8 @@ struct hwrm_func_vlan_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11507,7 +11660,8 @@ struct hwrm_func_vf_vnic_ids_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11580,7 +11734,8 @@ struct hwrm_func_vf_bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11704,7 +11859,8 @@ struct hwrm_func_vf_bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11841,7 +11997,8 @@ struct hwrm_func_drv_if_change_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -11929,7 +12086,8 @@ struct hwrm_port_phy_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -12520,7 +12678,8 @@ struct hwrm_port_phy_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13389,7 +13548,7 @@ struct hwrm_port_phy_qcfg_output {
*********************/
-/* hwrm_port_mac_cfg_input (size:320b/40B) */
+/* hwrm_port_mac_cfg_input (size:384b/48B) */
struct hwrm_port_mac_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -13407,7 +13566,8 @@ struct hwrm_port_mac_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -13527,6 +13687,13 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_FLAGS_IP_DSCP2COS_DISABLE \
UINT32_C(0x1000)
+ /*
+ * When this bit is set to '1', and the ptp_tx_ts_capture_enable
+ * bit is set, then the device uses one step Tx timestamping.
+ * This bit is temporary and used for experimental purposes.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_FLAGS_PTP_ONE_STEP_TX_TS \
+ UINT32_C(0x2000)
uint32_t enables;
/*
* This bit must be '1' for the ipg field to be
@@ -13576,6 +13743,12 @@ struct hwrm_port_mac_cfg_input {
*/
#define HWRM_PORT_MAC_CFG_INPUT_ENABLES_COS_FIELD_CFG \
UINT32_C(0x100)
+ /*
+ * This bit must be '1' for the ptp_freq_adj_ppb field to be
+ * configured.
+ */
+ #define HWRM_PORT_MAC_CFG_INPUT_ENABLES_PTP_FREQ_ADJ_PPB \
+ UINT32_C(0x200)
/* Port ID of port that is to be configured. */
uint16_t port_id;
/*
@@ -13763,6 +13936,12 @@ struct hwrm_port_mac_cfg_input {
#define HWRM_PORT_MAC_CFG_INPUT_COS_FIELD_CFG_DEFAULT_COS_SFT \
5
uint8_t unused_0[3];
+ /*
+ * This signed field specifies by how much to adjust the frequency
+ * of sync timer updates (measured in parts per billion).
+ */
+ int32_t ptp_freq_adj_ppb;
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_port_mac_cfg_output (size:128b/16B) */
@@ -13842,7 +14021,8 @@ struct hwrm_port_mac_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14131,7 +14311,8 @@ struct hwrm_port_mac_ptp_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14174,6 +14355,12 @@ struct hwrm_port_mac_ptp_qcfg_output {
*/
#define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_HWRM_ACCESS \
UINT32_C(0x2)
+ /*
+ * When this bit is set to '1', the device supports one-step
+ * Tx timestamping.
+ */
+ #define HWRM_PORT_MAC_PTP_QCFG_OUTPUT_FLAGS_ONE_STEP_TX_TS \
+ UINT32_C(0x4)
uint8_t unused_0[3];
/* Offset of the PTP register for the lower 32 bits of timestamp for RX. */
uint32_t rx_ts_reg_off_lower;
@@ -14595,7 +14782,8 @@ struct hwrm_port_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14716,7 +14904,7 @@ struct tx_port_stats_ext {
} __attribute__((packed));
/* Port Rx Statistics extended Formats */
-/* rx_port_stats_ext (size:2368b/296B) */
+/* rx_port_stats_ext (size:3648b/456B) */
struct rx_port_stats_ext {
/* Number of times link state changed to down */
uint64_t link_down_events;
@@ -14792,6 +14980,49 @@ struct rx_port_stats_ext {
uint64_t pfc_pri7_rx_duration_us;
/* Number of times, a XON -> XOFF and XOFF -> XON transitions occur for priority 7 */
uint64_t pfc_pri7_rx_transitions;
+ /* Total number of received bits */
+ uint64_t rx_bits;
+ /* The number of events where the port receive buffer was over 85% full */
+ uint64_t rx_buffer_passed_threshold;
+ /*
+ * The number of symbol errors that wasn't corrected by FEC correction
+ * alogirithm
+ */
+ uint64_t rx_pcs_symbol_err;
+ /* The number of corrected bits on the port according to active FEC */
+ uint64_t rx_corrected_bits;
+ /* Total number of rx discard bytes count on cos queue 0 */
+ uint64_t rx_discard_bytes_cos0;
+ /* Total number of rx discard bytes count on cos queue 1 */
+ uint64_t rx_discard_bytes_cos1;
+ /* Total number of rx discard bytes count on cos queue 2 */
+ uint64_t rx_discard_bytes_cos2;
+ /* Total number of rx discard bytes count on cos queue 3 */
+ uint64_t rx_discard_bytes_cos3;
+ /* Total number of rx discard bytes count on cos queue 4 */
+ uint64_t rx_discard_bytes_cos4;
+ /* Total number of rx discard bytes count on cos queue 5 */
+ uint64_t rx_discard_bytes_cos5;
+ /* Total number of rx discard bytes count on cos queue 6 */
+ uint64_t rx_discard_bytes_cos6;
+ /* Total number of rx discard bytes count on cos queue 7 */
+ uint64_t rx_discard_bytes_cos7;
+ /* Total number of rx discard packets count on cos queue 0 */
+ uint64_t rx_discard_packets_cos0;
+ /* Total number of rx discard packets count on cos queue 1 */
+ uint64_t rx_discard_packets_cos1;
+ /* Total number of rx discard packets count on cos queue 2 */
+ uint64_t rx_discard_packets_cos2;
+ /* Total number of rx discard packets count on cos queue 3 */
+ uint64_t rx_discard_packets_cos3;
+ /* Total number of rx discard packets count on cos queue 4 */
+ uint64_t rx_discard_packets_cos4;
+ /* Total number of rx discard packets count on cos queue 5 */
+ uint64_t rx_discard_packets_cos5;
+ /* Total number of rx discard packets count on cos queue 6 */
+ uint64_t rx_discard_packets_cos6;
+ /* Total number of rx discard packets count on cos queue 7 */
+ uint64_t rx_discard_packets_cos7;
} __attribute__((packed));
/************************
@@ -14817,7 +15048,8 @@ struct hwrm_port_qstats_ext_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14909,7 +15141,8 @@ struct hwrm_port_lpbk_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -14986,7 +15219,8 @@ struct hwrm_port_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15057,7 +15291,8 @@ struct hwrm_port_phy_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15311,7 +15546,8 @@ struct hwrm_port_phy_mdio_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15387,7 +15623,8 @@ struct hwrm_port_phy_mdio_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15463,7 +15700,8 @@ struct hwrm_port_led_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -15886,7 +16124,8 @@ struct hwrm_port_led_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16191,7 +16430,8 @@ struct hwrm_port_led_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16519,6 +16759,137 @@ struct hwrm_port_led_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/***********************
+ * hwrm_port_prbs_test *
+ ***********************/
+
+
+/* hwrm_port_prbs_test_input (size:384b/48B) */
+struct hwrm_port_prbs_test_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* Host address data is to DMA'd to. */
+ uint64_t resp_data_addr;
+ /*
+ * Size of the buffer pointed to by resp_data_addr. The firmware may
+ * use this entire buffer or less than the entire buffer, but never more.
+ */
+ uint16_t data_len;
+ uint16_t unused_0;
+ uint32_t unused_1;
+ /* Port ID of port where PRBS test to be run. */
+ uint16_t port_id;
+ /* Polynomial selection for PRBS test. */
+ uint16_t poly;
+ /* PRBS7 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS7 UINT32_C(0x0)
+ /* PRBS9 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS9 UINT32_C(0x1)
+ /* PRBS11 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS11 UINT32_C(0x2)
+ /* PRBS15 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS15 UINT32_C(0x3)
+ /* PRBS23 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS23 UINT32_C(0x4)
+ /* PRBS31 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS31 UINT32_C(0x5)
+ /* PRBS58 */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_PRBS58 UINT32_C(0x6)
+ /* Invalid */
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID UINT32_C(0xff)
+ #define HWRM_PORT_PRBS_TEST_INPUT_POLY_LAST \
+ HWRM_PORT_PRBS_TEST_INPUT_POLY_INVALID
+ /*
+ * Configuration bits for PRBS test.
+ * Use enable bit to start/stop test.
+ * Use tx/rx lane map bits to run test on specific lanes,
+ * if set to 0 test will be run on all lanes.
+ */
+ uint16_t prbs_config;
+ /*
+ * Set 0 to stop test currently in progress
+ * Set 1 to start test with configuration provided.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_START_STOP \
+ UINT32_C(0x1)
+ /*
+ * If set to 1, tx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_TX_LANE_MAP_VALID \
+ UINT32_C(0x2)
+ /*
+ * If set to 1, rx_lane_map bitmap should have lane bits set.
+ * If set to 0, test will be run on all lanes for this port.
+ */
+ #define HWRM_PORT_PRBS_TEST_INPUT_PRBS_CONFIG_RX_LANE_MAP_VALID \
+ UINT32_C(0x4)
+ /* Duration in seconds to run the PRBS test. */
+ uint16_t timeout;
+ /*
+ * If tx_lane_map_valid is set to 1, this field is a bitmap
+ * of tx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t tx_lane_map;
+ /*
+ * If rx_lane_map_valid is set to 1, this field is a bitmap
+ * of rx lanes to run PRBS test. bit0 = lane0,
+ * bit1 = lane1 ..bit31 = lane31
+ */
+ uint32_t rx_lane_map;
+} __attribute__((packed));
+
+/* hwrm_port_prbs_test_output (size:128b/16B) */
+struct hwrm_port_prbs_test_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* Total length of stored data. */
+ uint16_t total_data_len;
+ uint16_t unused_0;
+ uint8_t unused_1[3];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/***********************
* hwrm_queue_qportcfg *
***********************/
@@ -16542,7 +16913,8 @@ struct hwrm_queue_qportcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -16994,7 +17366,8 @@ struct hwrm_queue_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17091,7 +17464,8 @@ struct hwrm_queue_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17194,7 +17568,8 @@ struct hwrm_queue_pfcenable_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17283,7 +17658,8 @@ struct hwrm_queue_pfcenable_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17372,7 +17748,8 @@ struct hwrm_queue_pri2cos_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17522,7 +17899,8 @@ struct hwrm_queue_pri2cos_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -17698,7 +18076,8 @@ struct hwrm_queue_cos2bw_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -18740,7 +19119,8 @@ struct hwrm_queue_cos2bw_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19831,7 +20211,8 @@ struct hwrm_vnic_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19897,7 +20278,8 @@ struct hwrm_vnic_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -19957,7 +20339,8 @@ struct hwrm_vnic_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20172,7 +20555,8 @@ struct hwrm_vnic_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20327,7 +20711,8 @@ struct hwrm_vnic_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20419,7 +20804,13 @@ struct hwrm_vnic_qcaps_output {
*/
#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_OUTERMOST_RSS_CAP \
UINT32_C(0x80)
- uint8_t unused_1[7];
+ /*
+ * This field advertises the maximum concurrent TPA aggregations
+ * supported by the VNIC on new devices that support TPA v2.
+ * '0' means that TPA v2 is not supported.
+ */
+ uint16_t max_aggs_supported;
+ uint8_t unused_1[5];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -20453,7 +20844,8 @@ struct hwrm_vnic_tpa_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20529,6 +20921,15 @@ struct hwrm_vnic_tpa_cfg_input {
*/
#define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_GRO_TTL_CHECK \
UINT32_C(0x80)
+ /*
+ * When this bit is '1' and the GRO mode is enabled,
+ * the VNIC shall DMA payload data using GRO rules.
+ * When this bit is '0', the VNIC shall DMA payload data
+ * using the more efficient LRO rules of filling all
+ * aggregation buffers.
+ */
+ #define HWRM_VNIC_TPA_CFG_INPUT_FLAGS_AGG_PACK_AS_GRO \
+ UINT32_C(0x100)
uint32_t enables;
/*
* This bit must be '1' for the max_agg_segs field to be
@@ -20545,16 +20946,15 @@ struct hwrm_vnic_tpa_cfg_input {
* configured.
*/
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MAX_AGG_TIMER UINT32_C(0x4)
- /*
- * This bit must be '1' for the min_agg_len field to be
- * configured.
- */
+ /* deprecated bit. Do not use!!! */
#define HWRM_VNIC_TPA_CFG_INPUT_ENABLES_MIN_AGG_LEN UINT32_C(0x8)
/* Logical vnic ID */
uint16_t vnic_id;
/*
* This is the maximum number of TCP segments that can
- * be aggregated (unit is Log2). Max value is 31.
+ * be aggregated (unit is Log2). Max value is 31. On new
+ * devices supporting TPA v2, the unit is multiples of 4 and
+ * valid values are > 0 and <= 63.
*/
uint16_t max_agg_segs;
/* 1 segment */
@@ -20571,7 +20971,10 @@ struct hwrm_vnic_tpa_cfg_input {
HWRM_VNIC_TPA_CFG_INPUT_MAX_AGG_SEGS_MAX
/*
* This is the maximum number of aggregations this VNIC is
- * allowed (unit is Log2). Max value is 7
+ * allowed (unit is Log2). Max value is 7. On new devices
+ * supporting TPA v2, this is in unit of 1 and must be > 0
+ * and <= max_aggs_supported in the hwrm_vnic_qcaps response
+ * to enable TPA v2.
*/
uint16_t max_aggs;
/* 1 aggregation */
@@ -20596,7 +20999,9 @@ struct hwrm_vnic_tpa_cfg_input {
uint32_t max_agg_timer;
/*
* This is the minimum amount of payload length required to
- * start an aggregation context.
+ * start an aggregation context. This field is deprecated and
+ * should be set to 0. The minimum length is set by firmware
+ * and can be queried using hwrm_vnic_tpa_qcfg.
*/
uint32_t min_agg_len;
} __attribute__((packed));
@@ -20645,7 +21050,8 @@ struct hwrm_vnic_rss_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20795,7 +21201,8 @@ struct hwrm_vnic_rss_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -20937,7 +21344,8 @@ struct hwrm_vnic_plcmodes_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21100,7 +21508,8 @@ struct hwrm_vnic_plcmodes_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21228,7 +21637,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21287,7 +21697,8 @@ struct hwrm_vnic_rss_cos_lb_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21347,7 +21758,8 @@ struct hwrm_ring_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21687,7 +22099,8 @@ struct hwrm_ring_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21764,7 +22177,8 @@ struct hwrm_ring_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21839,7 +22253,8 @@ struct hwrm_ring_aggint_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -21988,7 +22403,8 @@ struct hwrm_ring_cmpl_ring_qaggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22094,7 +22510,8 @@ struct hwrm_ring_cmpl_ring_cfg_aggint_params_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22250,7 +22667,8 @@ struct hwrm_ring_grp_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22334,7 +22752,8 @@ struct hwrm_ring_grp_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22414,7 +22833,8 @@ struct hwrm_cfa_l2_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22476,6 +22896,22 @@ struct hwrm_cfa_l2_filter_alloc_input {
(UINT32_C(0x2) << 4)
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_LAST \
HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_TRAFFIC_ROCE
+ /*
+ * Setting of this flag indicates that no XDP filter is created with
+ * L2 filter.
+ * 0 - legacy behavior, XDP filter is created with L2 filter
+ * 1 - XDP filter won't be created with L2 filter
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_XDP_DISABLE \
+ UINT32_C(0x40)
+ /*
+ * Setting this flag to 1 indicate the L2 fields in this command
+ * pertain to source fields. Setting this flag to 0 indicate the
+ * L2 fields in this command pertain to the destination fields
+ * and this is the default/legacy behavior.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_SOURCE_VALID \
+ UINT32_C(0x80)
uint32_t enables;
/*
* This bit must be '1' for the l2_addr field to be
@@ -22579,13 +23015,31 @@ struct hwrm_cfa_l2_filter_alloc_input {
*/
#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_MIRROR_VNIC_ID \
UINT32_C(0x10000)
+ /*
+ * This bit must be '1' for the num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_NUM_VLANS \
+ UINT32_C(0x20000)
+ /*
+ * This bit must be '1' for the t_num_vlans field to be
+ * configured.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_T_NUM_VLANS \
+ UINT32_C(0x40000)
/*
* This value sets the match value for the L2 MAC address.
* Destination MAC address for RX path.
* Source MAC address for TX path.
*/
uint8_t l2_addr[6];
- uint8_t unused_0[2];
+ /* This value sets the match value for the number of VLANs. */
+ uint8_t num_vlans;
+ /*
+ * This value sets the match value for the number of VLANs
+ * in the tunnel headers.
+ */
+ uint8_t t_num_vlans;
/*
* This value sets the mask value for the L2 address.
* A value of 0 will mask the corresponding bit from
@@ -22784,13 +23238,45 @@ struct hwrm_cfa_l2_filter_alloc_output {
*/
uint64_t l2_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_L2_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -22825,7 +23311,8 @@ struct hwrm_cfa_l2_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -22887,7 +23374,8 @@ struct hwrm_cfa_l2_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23014,7 +23502,8 @@ struct hwrm_cfa_l2_set_rx_mask_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23213,7 +23702,8 @@ struct hwrm_cfa_vlan_antispoof_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23287,7 +23777,8 @@ struct hwrm_cfa_vlan_antispoof_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23366,7 +23857,8 @@ struct hwrm_cfa_tunnel_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23602,13 +24094,45 @@ struct hwrm_cfa_tunnel_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t tunnel_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_TUNNEL_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -23643,7 +24167,8 @@ struct hwrm_cfa_tunnel_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23702,7 +24227,8 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23813,7 +24339,8 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -23919,7 +24446,8 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24134,7 +24662,8 @@ struct hwrm_cfa_encap_record_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24247,7 +24776,8 @@ struct hwrm_cfa_encap_record_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24289,7 +24819,7 @@ struct hwrm_cfa_encap_record_free_output {
********************************/
-/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */
+/* hwrm_cfa_ntuple_filter_alloc_input (size:1088b/136B) */
struct hwrm_cfa_ntuple_filter_alloc_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -24307,7 +24837,8 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24456,6 +24987,12 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
*/
#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_DST_MACADDR \
UINT32_C(0x40000)
+ /*
+ * This bit must be '1' for the rfs_ring_tbl_idx field to be
+ * configured.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_RFS_RING_TBL_IDX \
+ UINT32_C(0x80000)
/*
* This value identifies a set of CFA data structures used for an L2
* context.
@@ -24639,6 +25176,13 @@ struct hwrm_cfa_ntuple_filter_alloc_input {
* the pri_hint.
*/
uint64_t ntuple_filter_id_hint;
+ /*
+ * The value of rfs_ring_tbl_idx to be used for RFS for this filter.
+ * This index is used in lieu of the RSS hash when selecting the
+ * index into the RSS table to determine the rx ring.
+ */
+ uint16_t rfs_ring_tbl_idx;
+ uint8_t unused_0[6];
} __attribute__((packed));
/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */
@@ -24654,13 +25198,45 @@ struct hwrm_cfa_ntuple_filter_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t ntuple_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_NTUPLE_FILTER_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -24713,7 +25289,8 @@ struct hwrm_cfa_ntuple_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24772,7 +25349,8 @@ struct hwrm_cfa_ntuple_filter_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -24884,7 +25462,8 @@ struct hwrm_cfa_em_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25216,13 +25795,45 @@ struct hwrm_cfa_em_flow_alloc_output {
/* This value is an opaque id into CFA data structures. */
uint64_t em_filter_id;
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_EM_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -25257,7 +25868,8 @@ struct hwrm_cfa_em_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25316,7 +25928,8 @@ struct hwrm_cfa_meter_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25428,7 +26041,8 @@ struct hwrm_cfa_meter_profile_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25705,7 +26319,8 @@ struct hwrm_cfa_meter_profile_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -25789,7 +26404,8 @@ struct hwrm_cfa_meter_profile_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26059,7 +26675,8 @@ struct hwrm_cfa_meter_instance_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26154,7 +26771,8 @@ struct hwrm_cfa_meter_instance_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26246,7 +26864,8 @@ struct hwrm_cfa_meter_instance_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26330,7 +26949,8 @@ struct hwrm_cfa_decap_filter_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26654,7 +27274,8 @@ struct hwrm_cfa_decap_filter_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26714,7 +27335,8 @@ struct hwrm_cfa_flow_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -26847,6 +27469,15 @@ struct hwrm_cfa_flow_alloc_input {
*/
#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \
UINT32_C(0x1000)
+ /*
+ * If set to 1 there will be no attempt to allocate an on-chip try to
+ * offload this flow. If set to 0, which will keep compatibility with the
+ * older drivers, will cause the FW to attempt to allocate an on-chip flow
+ * counter for the newly created flow. This will keep the existing behavior
+ * with EM flows which always had an associated flow counter.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \
+ UINT32_C(0x2000)
/*
* Tx Flow: pf or vf fid.
* Rx Flow: vf fid.
@@ -26977,13 +27608,45 @@ struct hwrm_cfa_flow_alloc_output {
uint16_t flow_handle;
uint8_t unused_0[2];
/*
- * This is the ID of the flow associated with this
- * filter.
- * This value shall be used to match and associate the
- * flow identifier returned in completion records.
- * A value of 0xFFFFFFFF shall indicate no flow id.
+ * The flow id value in bit 0-29 is the actual ID of the flow
+ * associated with this filter and it shall be used to match
+ * and associate the flow identifier returned in completion
+ * records. A value of 0xFFFFFFFF in the 32-bit flow_id field
+ * shall indicate no valid flow id.
*/
uint32_t flow_id;
+ /* Indicate the flow id value. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_MASK \
+ UINT32_C(0x3fffffff)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_VALUE_SFT 0
+ /* Indicate type of the flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE \
+ UINT32_C(0x40000000)
+ /*
+ * If this bit set to 0, then it indicates that the flow is
+ * internal flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_INT \
+ (UINT32_C(0x0) << 30)
+ /*
+ * If this bit is set to 1, then it indicates that the flow is
+ * external flow.
+ */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT \
+ (UINT32_C(0x1) << 30)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_TYPE_EXT
+ /* Indicate the flow direction. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR \
+ UINT32_C(0x80000000)
+ /* If this bit set to 0, then it indicates rx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_RX \
+ (UINT32_C(0x0) << 31)
+ /* If this bit is set to 1, then it indicates that tx flow. */
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX \
+ (UINT32_C(0x1) << 31)
+ #define HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_LAST \
+ HWRM_CFA_FLOW_ALLOC_OUTPUT_FLOW_ID_DIR_TX
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
uint32_t flow_counter_id;
@@ -26998,6 +27661,34 @@ struct hwrm_cfa_flow_alloc_output {
uint8_t valid;
} __attribute__((packed));
+/* hwrm_cfa_flow_alloc_cmd_err (size:64b/8B) */
+struct hwrm_cfa_flow_alloc_cmd_err {
+ /*
+ * command specific error codes that goes to
+ * the cmd_err field in Common HWRM Error Response.
+ */
+ uint8_t code;
+ /* Unknown error */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_UNKNOWN UINT32_C(0x0)
+ /* No more L2 Context TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_L2_CONTEXT_TCAM UINT32_C(0x1)
+ /* No more action records */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_ACTION_RECORD UINT32_C(0x2)
+ /* No more flow counters */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_COUNTER UINT32_C(0x3)
+ /* No more wild-card TCAM */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_WILD_CARD_TCAM UINT32_C(0x4)
+ /* Hash collsion in exact match tables */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_HASH_COLLISION UINT32_C(0x5)
+ /* Key is already installed */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_KEY_EXISTS UINT32_C(0x6)
+ /* Flow Context DB is out of resource */
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB UINT32_C(0x7)
+ #define HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_LAST \
+ HWRM_CFA_FLOW_ALLOC_CMD_ERR_CODE_FLOW_CTXT_DB
+ uint8_t unused_0[7];
+} __attribute__((packed));
+
/**********************
* hwrm_cfa_flow_free *
**********************/
@@ -27021,7 +27712,8 @@ struct hwrm_cfa_flow_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27034,7 +27726,9 @@ struct hwrm_cfa_flow_free_input {
uint64_t resp_addr;
/* Flow record index. */
uint16_t flow_handle;
- uint8_t unused_0[6];
+ uint16_t unused_0;
+ /* Flow counter id to be freed. */
+ uint32_t flow_counter_id;
/* This value identifies a set of CFA data structures used for a flow. */
uint64_t ext_flow_handle;
} __attribute__((packed));
@@ -27310,7 +28004,8 @@ struct hwrm_cfa_flow_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27420,7 +28115,8 @@ struct hwrm_cfa_flow_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27448,6 +28144,9 @@ struct hwrm_cfa_flow_flush_input {
*/
#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \
UINT32_C(0x2)
+ /* Set to 1 to indicate the flow counter IDs are included in the flow table. */
+ #define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \
+ UINT32_C(0x8000000)
/*
* This specifies the size of flow handle entries provided by the driver
* in the flow table specified below. Only two flow handle size enums are defined.
@@ -27544,7 +28243,8 @@ struct hwrm_cfa_flow_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27684,7 +28384,8 @@ struct hwrm_cfa_flow_aging_timer_reset_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27733,7 +28434,7 @@ struct hwrm_cfa_flow_aging_timer_reset_output {
***************************/
-/* hwrm_cfa_flow_aging_cfg_input (size:256b/32B) */
+/* hwrm_cfa_flow_aging_cfg_input (size:384b/48B) */
struct hwrm_cfa_flow_aging_cfg_input {
/* The HWRM command request type. */
uint16_t req_type;
@@ -27751,7 +28452,8 @@ struct hwrm_cfa_flow_aging_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27773,16 +28475,40 @@ struct hwrm_cfa_flow_aging_cfg_input {
/* This bit must be '1' for the udp flow timer field to be configured */
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \
UINT32_C(0x4)
- /* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */
+ /* This bit must be '1' for the eem dma interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \
+ UINT32_C(0x8)
+ /* This bit must be '1' for the eem notice interval field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \
+ UINT32_C(0x10)
+ /* This bit must be '1' for the eem context memory maximum entries field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \
+ UINT32_C(0x20)
+ /* This bit must be '1' for the eem context memory ID field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \
+ UINT32_C(0x40)
+ /* This bit must be '1' for the eem context memory type field to be configured */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \
+ UINT32_C(0x80)
uint8_t flags;
/* Enumeration denoting the RX, TX type of the resource. */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH UINT32_C(0x1)
/* tx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_TX UINT32_C(0x0)
/* rx path */
- #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX UINT32_C(0x1)
#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \
HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX
+ /* Enumeration denoting the enable, disable eem flow aging configuration. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM UINT32_C(0x2)
+ /* tx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \
+ (UINT32_C(0x0) << 1)
+ /* rx path */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE \
+ (UINT32_C(0x1) << 1)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE
uint8_t unused_0;
/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */
uint32_t tcp_flow_timer;
@@ -27790,6 +28516,21 @@ struct hwrm_cfa_flow_aging_cfg_input {
uint32_t tcp_fin_timer;
/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */
uint32_t udp_flow_timer;
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ uint16_t eem_ctx_mem_type;
+ /* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \
+ UINT32_C(0x0)
+ #define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \
+ HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA
+ uint8_t unused_1[4];
} __attribute__((packed));
/* hwrm_cfa_flow_aging_cfg_output (size:128b/16B) */
@@ -27836,7 +28577,8 @@ struct hwrm_cfa_flow_aging_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27860,7 +28602,7 @@ struct hwrm_cfa_flow_aging_qcfg_input {
uint8_t unused_0[7];
} __attribute__((packed));
-/* hwrm_cfa_flow_aging_qcfg_output (size:192b/24B) */
+/* hwrm_cfa_flow_aging_qcfg_output (size:320b/40B) */
struct hwrm_cfa_flow_aging_qcfg_output {
/* The specific error status for the command. */
uint16_t error_code;
@@ -27876,7 +28618,17 @@ struct hwrm_cfa_flow_aging_qcfg_output {
uint32_t tcp_fin_timer;
/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */
uint32_t udp_flow_timer;
- uint8_t unused_0[3];
+ /* The interval to dma eem ejection data to host memory, the unit is milliseconds. */
+ uint16_t eem_dma_interval;
+ /* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */
+ uint16_t eem_notice_interval;
+ /* The maximum entries number in the eem context memory. */
+ uint32_t eem_ctx_max_entries;
+ /* The context memory ID for eem flow aging. */
+ uint16_t eem_ctx_id;
+ /* The context memory type for eem flow aging. */
+ uint16_t eem_ctx_mem_type;
+ uint8_t unused_0[7];
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -27910,7 +28662,8 @@ struct hwrm_cfa_flow_aging_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -27986,7 +28739,8 @@ struct hwrm_cfa_tcp_flag_process_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28051,7 +28805,8 @@ struct hwrm_cfa_pair_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28171,7 +28926,8 @@ struct hwrm_cfa_redirect_query_tunnel_type_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28275,7 +29031,8 @@ struct hwrm_cfa_ctx_mem_rgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28371,7 +29128,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28434,7 +29192,8 @@ struct hwrm_cfa_ctx_mem_qctx_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28531,7 +29290,8 @@ struct hwrm_cfa_ctx_mem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28582,7 +29342,8 @@ struct hwrm_cfa_eem_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28630,13 +29391,31 @@ struct hwrm_cfa_eem_qcaps_output {
* which are to be offloaded.
* Note if this bit is set then the path_rx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX UINT32_C(0x1)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_TX \
+ UINT32_C(0x1)
/*
* When set to 1, indicates the configuration will apply to RX flows
* which are to be offloaded.
* Note if this bit is set then the path_tx bit can't be set.
*/
- #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX UINT32_C(0x2)
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \
+ UINT32_C(0x2)
+ /*
+ * When set to 1, indicates the the FW supports the Centralized
+ * Memory Model. The concept designates one entity for the
+ * memory allocation while all others ‘subscribe’ to it.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x4)
+ /*
+ * When set to 1, indicates the the FW supports the Detached
+ * Centralized Memory Model. The memory is allocated and managed
+ * as a separate entity. All PFs and VFs will be granted direct
+ * or semi-direct access to the allocated memory while none of
+ * which can interfere with the management of the memory.
+ */
+ #define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_DETACHED_CENTRALIZED_MEMORY_MODEL_SUPPORTED \
+ UINT32_C(0x8)
uint32_t unused_0;
uint32_t supported;
/*
@@ -28712,7 +29491,8 @@ struct hwrm_cfa_eem_cfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28741,7 +29521,15 @@ struct hwrm_cfa_eem_cfg_input {
/* When set to 1, all offloaded flows will be sent to EEM. */
#define HWRM_CFA_EEM_CFG_INPUT_FLAGS_PREFERRED_OFFLOAD \
UINT32_C(0x4)
- uint32_t unused_0;
+ /* When set to 1, secondary, 0 means primary. */
+ #define HWRM_CFA_EEM_CFG_INPUT_FLAGS_SECONDARY_PF \
+ UINT32_C(0x8)
+ /*
+ * Group_id which used by Firmware to identify memory pools belonging
+ * to certain group.
+ */
+ uint16_t group_id;
+ uint16_t unused_0;
/*
* Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,
* RECORD, EFC all have the same number of entries and all tables will be configured
@@ -28803,7 +29591,8 @@ struct hwrm_cfa_eem_qcfg_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28878,7 +29667,8 @@ struct hwrm_cfa_eem_op_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -28974,7 +29764,8 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29045,6 +29836,42 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
*/
#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \
UINT32_C(0x40)
+ /*
+ * Value of 1 to indicate that firmware supports the dynamic allocation of an
+ * on-chip flow counter which can be used for EEM flows.
+ * Value of 0 indicates firmware does not support the dynamic allocation of an
+ * on-chip flow counter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \
+ UINT32_C(0x80)
+ /*
+ * Value of 1 to indicate that firmware supports setting of
+ * rfs_ring_tbl_idx in HWRM_CFA_NTUPLE_ALLOC command.
+ * Value of 0 indicates firmware does not support rfs_ring_tbl_idx.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RFS_RING_TBL_IDX_SUPPORTED \
+ UINT32_C(0x100)
+ /*
+ * Value of 1 to indicate that firmware supports untagged matching
+ * criteria on HWRM_CFA_L2_FILTER_ALLOC command. Value of 0
+ * indicates firmware does not support untagged matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_UNTAGGED_VLAN_SUPPORTED \
+ UINT32_C(0x200)
+ /*
+ * Value of 1 to indicate that firmware supports XDP filter. Value
+ * of 0 indicates firmware does not support XDP filter.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_XDP_SUPPORTED \
+ UINT32_C(0x400)
+ /*
+ * Value of 1 to indicate that the firmware support L2 header source
+ * fields matching criteria on HWRM_CFA_L2_FILTER_ALLOC command.
+ * Value of 0 indicates firmware does not support L2 header source
+ * fields matching.
+ */
+ #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED \
+ UINT32_C(0x800)
uint8_t unused_0[3];
/*
* This field is used in Output records to indicate that the output
@@ -29056,6 +29883,81 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {
uint8_t valid;
} __attribute__((packed));
+/******************
+ * hwrm_cfa_tflib *
+ ******************/
+
+
+/* hwrm_cfa_tflib_input (size:1024b/128B) */
+struct hwrm_cfa_tflib_input {
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /*
+ * The completion ring to send the completion event on. This should
+ * be the NQ ID returned from the `nq_alloc` HWRM command.
+ */
+ uint16_t cmpl_ring;
+ /*
+ * The sequence ID is used by the driver for tracking multiple
+ * commands. This ID is treated as opaque data by the firmware and
+ * the value is returned in the `hwrm_resp_hdr` upon completion.
+ */
+ uint16_t seq_id;
+ /*
+ * The target ID of the command:
+ * * 0x0-0xFFF8 - The function ID
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
+ * * 0xFFFF - HWRM
+ */
+ uint16_t target_id;
+ /*
+ * A physical address pointer pointing to a host buffer that the
+ * command's response data will be written. This can be either a host
+ * physical address (HPA) or a guest physical address (GPA) and must
+ * point to a physically contiguous block of memory.
+ */
+ uint64_t resp_addr;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* unused. */
+ uint8_t unused0[4];
+ /* TFLIB request data. */
+ uint32_t tf_req[26];
+} __attribute__((packed));
+
+/* hwrm_cfa_tflib_output (size:5632b/704B) */
+struct hwrm_cfa_tflib_output {
+ /* The specific error status for the command. */
+ uint16_t error_code;
+ /* The HWRM command request type. */
+ uint16_t req_type;
+ /* The sequence ID from the original command. */
+ uint16_t seq_id;
+ /* The length of the response data in number of bytes. */
+ uint16_t resp_len;
+ /* TFLIB message type. */
+ uint16_t tf_type;
+ /* TFLIB message subtype. */
+ uint16_t tf_subtype;
+ /* TFLIB response code */
+ uint32_t tf_resp_code;
+ /* TFLIB response data. */
+ uint32_t tf_resp[170];
+ /* unused. */
+ uint8_t unused1[7];
+ /*
+ * This field is used in Output records to indicate that the output
+ * is completely written to RAM. This field should be read as '1'
+ * to indicate that the output has been completely written.
+ * When writing a command completion or response to an internal processor,
+ * the order of writes has to be such that this field is written last.
+ */
+ uint8_t valid;
+} __attribute__((packed));
+
/******************************
* hwrm_tunnel_dst_port_query *
******************************/
@@ -29079,7 +29981,8 @@ struct hwrm_tunnel_dst_port_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29177,7 +30080,8 @@ struct hwrm_tunnel_dst_port_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29274,7 +30178,8 @@ struct hwrm_tunnel_dst_port_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29451,7 +30356,8 @@ struct hwrm_stat_ctx_alloc_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29540,7 +30446,8 @@ struct hwrm_stat_ctx_free_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29602,7 +30509,8 @@ struct hwrm_stat_ctx_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29702,7 +30610,8 @@ struct hwrm_stat_ctx_eng_query_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29803,7 +30712,8 @@ struct hwrm_stat_ctx_clr_stats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29863,7 +30773,8 @@ struct hwrm_pcie_qstats_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -29970,7 +30881,8 @@ struct hwrm_exec_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30043,7 +30955,8 @@ struct hwrm_reject_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30116,7 +31029,8 @@ struct hwrm_fwd_resp_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30204,7 +31118,8 @@ struct hwrm_fwd_async_event_cmpl_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30273,7 +31188,8 @@ struct hwrm_nvm_raw_write_blk_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30342,7 +31258,8 @@ struct hwrm_nvm_read_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30412,7 +31329,8 @@ struct hwrm_nvm_raw_dump_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30478,7 +31396,8 @@ struct hwrm_nvm_get_dir_entries_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30540,7 +31459,8 @@ struct hwrm_nvm_get_dir_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30601,7 +31521,8 @@ struct hwrm_nvm_write_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30722,7 +31643,8 @@ struct hwrm_nvm_modify_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30795,7 +31717,8 @@ struct hwrm_nvm_find_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30897,7 +31820,8 @@ struct hwrm_nvm_erase_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30957,7 +31881,8 @@ struct hwrm_nvm_get_dev_info_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -30991,7 +31916,12 @@ struct hwrm_nvm_get_dev_info_output {
uint32_t reserved_size;
/* Available size that can be used, in bytes. Available size is the NVRAM size take away the used size and reserved size. */
uint32_t available_size;
- uint8_t unused_0[3];
+ /* This field represents the major version of NVM cfg */
+ uint8_t nvm_cfg_ver_maj;
+ /* This field represents the minor version of NVM cfg */
+ uint8_t nvm_cfg_ver_min;
+ /* This field represents the update version of NVM cfg */
+ uint8_t nvm_cfg_ver_upd;
/*
* This field is used in Output records to indicate that the output
* is completely written to RAM. This field should be read as '1'
@@ -31025,7 +31955,8 @@ struct hwrm_nvm_mod_dir_entry_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31104,7 +32035,8 @@ struct hwrm_nvm_verify_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31177,7 +32109,8 @@ struct hwrm_nvm_install_update_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31340,7 +32273,8 @@ struct hwrm_nvm_flush_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31413,7 +32347,8 @@ struct hwrm_nvm_get_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31548,7 +32483,8 @@ struct hwrm_nvm_set_variable_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
@@ -31678,7 +32614,8 @@ struct hwrm_nvm_validate_option_input {
/*
* The target ID of the command:
* * 0x0-0xFFF8 - The function ID
- * * 0xFFF8-0xFFFE - Reserved for internal processors
+ * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
+ * * 0xFFFD - Reserved for user-space HWRM interface
* * 0xFFFF - HWRM
*/
uint16_t target_id;
--
2.17.1
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v5 0/8] bnxt patchset
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Lance Richardson
` (7 preceding siblings ...)
2019-05-29 21:02 ` [dpdk-dev] [PATCH v5 8/8] net/bnxt: update HWRM API to version 1.10.0.74 Lance Richardson
@ 2019-06-04 16:07 ` Ferruh Yigit
2019-06-14 15:34 ` Ferruh Yigit
8 siblings, 1 reply; 75+ messages in thread
From: Ferruh Yigit @ 2019-06-04 16:07 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin, ktraynor
On 5/29/2019 10:02 PM, Lance Richardson wrote:
> This patchset adds the following:
> 1) Support for vector mode TX and RX.
> 2) HWRM API update (split into multiple patches).
> 3) Fixes for RSS reta update and query.
>
> It also updates the release notes.
>
> v2:
> * Squashed patches 3 and 4 from v1 patchset.
> * Added Meson build support for vector mode PMD.
> * Dropped two unnecessary code style changes from patch 3.
>
> v3:
> * Squashed three RSS RETA fix patches into one.
> * Eliminated RTE_LIBRTE_BNXT_INC_VECTOR configuration flag.
> * Addressed commit log issues from check-git-log.sh.
> * Made subject line consistent for HWRM API update patches.
> * Separated release notes updates to keep update with associated
> patch (except for the first update for which the associated patch
> has already been applied).
>
> v4:
> * The change squashed from patch 4 into patch 3 from the v1
> patchset should have been squashed into patch 2; fixed in v4.
>
> v5:
> * Corrected commit IDs and added Fixes: tags to patch 01.
>
> Ajit Khaparde (5):
> net/bnxt: update release notes for bnxt
> net/bnxt: fix RSS RETA indirection table ops
> net/bnxt: update HWRM API to version 1.10.0.19
> net/bnxt: update HWRM API to version 1.10.0.48
> net/bnxt: update HWRM API to version 1.10.0.74
>
> Lance Richardson (3):
> net/bnxt: move Tx bd checking to header file
> net/bnxt: compute and store scattered Rx status
> net/bnxt: implement vector mode driver
Series applied to dpdk-next-net/master, thanks.
^ permalink raw reply [flat|nested] 75+ messages in thread* Re: [dpdk-dev] [PATCH v5 0/8] bnxt patchset
2019-06-04 16:07 ` [dpdk-dev] [PATCH v5 0/8] bnxt patchset Ferruh Yigit
@ 2019-06-14 15:34 ` Ferruh Yigit
0 siblings, 0 replies; 75+ messages in thread
From: Ferruh Yigit @ 2019-06-14 15:34 UTC (permalink / raw)
To: Lance Richardson, dev; +Cc: ajit.khaparde, maxime.coquelin, ktraynor
On 6/4/2019 5:07 PM, Ferruh Yigit wrote:
> On 5/29/2019 10:02 PM, Lance Richardson wrote:
>> This patchset adds the following:
>> 1) Support for vector mode TX and RX.
>> 2) HWRM API update (split into multiple patches).
>> 3) Fixes for RSS reta update and query.
>>
>> It also updates the release notes.
>>
>> v2:
>> * Squashed patches 3 and 4 from v1 patchset.
>> * Added Meson build support for vector mode PMD.
>> * Dropped two unnecessary code style changes from patch 3.
>>
>> v3:
>> * Squashed three RSS RETA fix patches into one.
>> * Eliminated RTE_LIBRTE_BNXT_INC_VECTOR configuration flag.
>> * Addressed commit log issues from check-git-log.sh.
>> * Made subject line consistent for HWRM API update patches.
>> * Separated release notes updates to keep update with associated
>> patch (except for the first update for which the associated patch
>> has already been applied).
>>
>> v4:
>> * The change squashed from patch 4 into patch 3 from the v1
>> patchset should have been squashed into patch 2; fixed in v4.
>>
>> v5:
>> * Corrected commit IDs and added Fixes: tags to patch 01.
>>
>> Ajit Khaparde (5):
>> net/bnxt: update release notes for bnxt
>> net/bnxt: fix RSS RETA indirection table ops
>> net/bnxt: update HWRM API to version 1.10.0.19
>> net/bnxt: update HWRM API to version 1.10.0.48
>> net/bnxt: update HWRM API to version 1.10.0.74
>>
>> Lance Richardson (3):
>> net/bnxt: move Tx bd checking to header file
>> net/bnxt: compute and store scattered Rx status
>> net/bnxt: implement vector mode driver
>
> Series applied to dpdk-next-net/master, thanks.
>
There were some checkpatch typo warnings, fixed them in next-net before merged
into the master, FYI. Please double check the final commits, changes:
net/bnxt: update HWRM API to version 1.10.0.19
WARNING:TYPO_SPELLING: 'preceed' may be misspelled - perhaps 'precede'?
WARNING:TYPO_SPELLING: 'occured' may be misspelled - perhaps 'occurred'?
WARNING:TYPO_SPELLING: 'auxillary' may be misspelled - perhaps 'auxiliary'?
net/bnxt: update HWRM API to version 1.10.0.48
WARNING:TYPO_SPELLING: 'occured' may be misspelled - perhaps 'occurred'?
^ permalink raw reply [flat|nested] 75+ messages in thread