From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id 9A974A0096 for ; Sun, 2 Jun 2019 17:25:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 254641B96E; Sun, 2 Jun 2019 17:24:58 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 5833E1B959 for ; Sun, 2 Jun 2019 17:24:56 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x52FK4Yd020248; Sun, 2 Jun 2019 08:24:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=+Es6M4aJdEAZ1hkzT31eRqMshpppTbpqeyuAwH75Kv8=; b=XhLiRlI6b8RebDivJMwcKgXFQUYGcjIace3NU43XNTgSeA8DGj0VKsW18ONTuSGtf9+k oDt9ZAuNymHYM/uUpu4ODjd9BUaQzHHQbML8iYQn9rsEjefECd8Q+aEzLLFBBH8bTv3x 0QPlrEifITK9YOXV1bHdzQFij7skUJi/nbj/+MC0waFbVeeROBCgej8joq7iMyYk+nC/ N45Jx27E9MfV/q5RAf18+hpwBt5hPn9O2fGJPybMNvQB0hYljznkWSfOnrhYKrPhQlyR m1lgglKoDgVESF8b4gDUA6N7SOWw+Ch2d10UJoD5EzZImrUQWOhVHnz180+UjcFa/2L1 +w== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2survk491a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 02 Jun 2019 08:24:55 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 2 Jun 2019 08:24:54 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 2 Jun 2019 08:24:54 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 228413F703F; Sun, 2 Jun 2019 08:24:51 -0700 (PDT) From: To: , John McNamara , Marko Kovacevic , Jerin Jacob , "Nithin Dabilpuram" , Kiran Kumar K CC: , Vamsi Attunuru , "Harman Kalra" Date: Sun, 2 Jun 2019 20:53:42 +0530 Message-ID: <20190602152434.23996-7-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190602152434.23996-1-jerinj@marvell.com> References: <20190602152434.23996-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-02_09:, , signatures=0 Subject: [dpdk-dev] [PATCH v1 06/58] net/octeontx2: add info get operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Add device information get operation. Signed-off-by: Jerin Jacob Signed-off-by: Vamsi Attunuru Signed-off-by: Harman Kalra --- doc/guides/nics/features/octeontx2.ini | 4 ++ doc/guides/nics/features/octeontx2_vec.ini | 4 ++ doc/guides/nics/features/octeontx2_vf.ini | 3 + drivers/net/octeontx2/Makefile | 1 + drivers/net/octeontx2/meson.build | 1 + drivers/net/octeontx2/otx2_ethdev.c | 7 +++ drivers/net/octeontx2/otx2_ethdev.h | 27 +++++++++ drivers/net/octeontx2/otx2_ethdev_ops.c | 64 ++++++++++++++++++++++ 8 files changed, 111 insertions(+) create mode 100644 drivers/net/octeontx2/otx2_ethdev_ops.c diff --git a/doc/guides/nics/features/octeontx2.ini b/doc/guides/nics/features/octeontx2.ini index 0ec3b6983..1f0148669 100644 --- a/doc/guides/nics/features/octeontx2.ini +++ b/doc/guides/nics/features/octeontx2.ini @@ -4,5 +4,9 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y Linux VFIO = Y ARMv8 = Y +Lock-free Tx queue = Y +SR-IOV = Y +Multiprocess aware = Y diff --git a/doc/guides/nics/features/octeontx2_vec.ini b/doc/guides/nics/features/octeontx2_vec.ini index 774f136c1..2b0644ee5 100644 --- a/doc/guides/nics/features/octeontx2_vec.ini +++ b/doc/guides/nics/features/octeontx2_vec.ini @@ -4,5 +4,9 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y Linux VFIO = Y ARMv8 = Y +Lock-free Tx queue = Y +SR-IOV = Y +Multiprocess aware = Y diff --git a/doc/guides/nics/features/octeontx2_vf.ini b/doc/guides/nics/features/octeontx2_vf.ini index 36642354e..80f0d5c95 100644 --- a/doc/guides/nics/features/octeontx2_vf.ini +++ b/doc/guides/nics/features/octeontx2_vf.ini @@ -4,5 +4,8 @@ ; Refer to default.ini for the full list of available PMD features. ; [Features] +Speed capabilities = Y Linux VFIO = Y ARMv8 = Y +Lock-free Tx queue = Y +Multiprocess aware = Y diff --git a/drivers/net/octeontx2/Makefile b/drivers/net/octeontx2/Makefile index a56143dcd..820202eb2 100644 --- a/drivers/net/octeontx2/Makefile +++ b/drivers/net/octeontx2/Makefile @@ -33,6 +33,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_PMD) += \ otx2_mac.c \ otx2_ethdev.c \ otx2_ethdev_irq.c \ + otx2_ethdev_ops.c \ otx2_ethdev_devargs.c LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_common_octeontx2 -lm diff --git a/drivers/net/octeontx2/meson.build b/drivers/net/octeontx2/meson.build index c49e1cb80..a2dc983e3 100644 --- a/drivers/net/octeontx2/meson.build +++ b/drivers/net/octeontx2/meson.build @@ -6,6 +6,7 @@ sources = files( 'otx2_mac.c', 'otx2_ethdev.c', 'otx2_ethdev_irq.c', + 'otx2_ethdev_ops.c', 'otx2_ethdev_devargs.c' ) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 67a7ebb36..6e3c70559 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -64,6 +64,11 @@ nix_lf_free(struct otx2_eth_dev *dev) return otx2_mbox_process(mbox); } +/* Initialize and register driver with DPDK Application */ +static const struct eth_dev_ops otx2_eth_dev_ops = { + .dev_infos_get = otx2_nix_info_get, +}; + static inline int nix_lf_attach(struct otx2_eth_dev *dev) { @@ -120,6 +125,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) struct rte_pci_device *pci_dev; int rc, max_entries; + eth_dev->dev_ops = &otx2_eth_dev_ops; + /* For secondary processes, the primary has done all the work */ if (rte_eal_process_type() != RTE_PROC_PRIMARY) { /* Setup callbacks for secondary process */ diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 670d1ff0b..00baabaac 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -33,7 +33,30 @@ /* Used for struct otx2_eth_dev::flags */ #define OTX2_LINK_CFG_IN_PROGRESS_F BIT_ULL(0) +#define VLAN_TAG_SIZE 4 +#define NIX_HW_L2_OVERHEAD 22 +/* ETH_HLEN+2*VLAN_HLEN */ +#define NIX_MAX_HW_MTU 9190 +#define NIX_MAX_HW_FRS (NIX_MAX_HW_MTU + NIX_HW_L2_OVERHEAD) +#define NIX_MIN_HW_FRS 60 +#define NIX_HASH_KEY_SIZE 48 /* 352 Bits */ #define NIX_RSS_RETA_SIZE 64 +#define NIX_RX_MIN_DESC 16 +#define NIX_RX_MIN_DESC_ALIGN 16 +#define NIX_RX_NB_SEG_MAX 6 + +/* If PTP is enabled additional SEND MEM DESC is required which + * takes 2 words, hence max 7 iova address are possible + */ +#if defined(RTE_LIBRTE_IEEE1588) +#define NIX_TX_NB_SEG_MAX 7 +#else +#define NIX_TX_NB_SEG_MAX 9 +#endif + +#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\ + ETH_RSS_TCP | ETH_RSS_SCTP | \ + ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD) #define NIX_TX_OFFLOAD_CAPA ( \ DEV_TX_OFFLOAD_MBUF_FAST_FREE | \ @@ -102,6 +125,10 @@ otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev) return eth_dev->data->dev_private; } +/* Ops */ +void otx2_nix_info_get(struct rte_eth_dev *eth_dev, + struct rte_eth_dev_info *dev_info); + /* IRQ */ int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev); void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev); diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c new file mode 100644 index 000000000..9f86635d4 --- /dev/null +++ b/drivers/net/octeontx2/otx2_ethdev_ops.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include "otx2_ethdev.h" + +void +otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + + devinfo->min_rx_bufsize = NIX_MIN_HW_FRS; + devinfo->max_rx_pktlen = NIX_MAX_HW_FRS; + devinfo->max_rx_queues = RTE_MAX_QUEUES_PER_PORT; + devinfo->max_tx_queues = RTE_MAX_QUEUES_PER_PORT; + devinfo->max_mac_addrs = dev->max_mac_entries; + devinfo->max_vfs = pci_dev->max_vfs; + devinfo->max_mtu = devinfo->max_rx_pktlen - NIX_HW_L2_OVERHEAD; + devinfo->min_mtu = devinfo->min_rx_bufsize - NIX_HW_L2_OVERHEAD; + + devinfo->rx_offload_capa = dev->rx_offload_capa; + devinfo->tx_offload_capa = dev->tx_offload_capa; + devinfo->rx_queue_offload_capa = 0; + devinfo->tx_queue_offload_capa = 0; + + devinfo->reta_size = dev->rss_info.rss_size; + devinfo->hash_key_size = NIX_HASH_KEY_SIZE; + devinfo->flow_type_rss_offloads = NIX_RSS_OFFLOAD; + + devinfo->default_rxconf = (struct rte_eth_rxconf) { + .rx_drop_en = 0, + .offloads = 0, + }; + + devinfo->default_txconf = (struct rte_eth_txconf) { + .offloads = 0, + }; + + devinfo->rx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = UINT16_MAX, + .nb_min = NIX_RX_MIN_DESC, + .nb_align = NIX_RX_MIN_DESC_ALIGN, + .nb_seg_max = NIX_RX_NB_SEG_MAX, + .nb_mtu_seg_max = NIX_RX_NB_SEG_MAX, + }; + devinfo->rx_desc_lim.nb_max = + RTE_ALIGN_MUL_FLOOR(devinfo->rx_desc_lim.nb_max, + NIX_RX_MIN_DESC_ALIGN); + + devinfo->tx_desc_lim = (struct rte_eth_desc_lim) { + .nb_max = UINT16_MAX, + .nb_min = 1, + .nb_align = 1, + .nb_seg_max = NIX_TX_NB_SEG_MAX, + .nb_mtu_seg_max = NIX_TX_NB_SEG_MAX, + }; + + /* Auto negotiation disabled */ + devinfo->speed_capa = ETH_LINK_SPEED_FIXED; + devinfo->speed_capa |= ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G | + ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G | + ETH_LINK_SPEED_50G | ETH_LINK_SPEED_100G; +} -- 2.21.0