From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by dpdk.space (Postfix) with ESMTP id AC580A0471 for ; Sat, 22 Jun 2019 15:28:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8EBDE1C5DB; Sat, 22 Jun 2019 15:26:27 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 401831C61B for ; Sat, 22 Jun 2019 15:25:39 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5MDOdZT028280 for ; Sat, 22 Jun 2019 06:25:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=GWCHk9BPrzpW+EEHNrh4WIrPaZC3CiMeCAHF02iIDss=; b=SJwUreJ8ySkM+w3jyxgoZ2mFLCLMJn4kYF98UpYFZNzmpcA/pTRntRpLfEZFUfLWmM+4 ZZ7ZEPXKk//23hC9pC62nK4iKxEDo6tl9GOAJJUqramhp19pPCBF6tNhOBIk/MDn3iQp xEJLrrRUAGzKzmmmBnnky72iAdFUJJyUW/Tne+vkNj4JSxhad1W29Em648v0IScWEqRF hJXeYTZ3HFuRnGTYPUX1fAOKQC2d80k8SZTlAlQartjZKWZwR58inuOb3NQ9eJD7j7TT yhgJNNLp5xzKwcsfAVp6IaihGqellUYo9kaJTQ3la3ppBIq/PRpBoVtzA/OjSFWMVIpO lA== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 2t9hpnrgh3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sat, 22 Jun 2019 06:25:38 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sat, 22 Jun 2019 06:25:37 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sat, 22 Jun 2019 06:25:37 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id 1A7733F703F; Sat, 22 Jun 2019 06:25:35 -0700 (PDT) From: To: Jerin Jacob , Nithin Dabilpuram , Vamsi Attunuru CC: Date: Sat, 22 Jun 2019 18:54:13 +0530 Message-ID: <20190622132417.32694-24-jerinj@marvell.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190622132417.32694-1-jerinj@marvell.com> References: <20190617155537.36144-1-jerinj@marvell.com> <20190622132417.32694-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-22_09:, , signatures=0 Subject: [dpdk-dev] [PATCH v4 23/27] mempool/octeontx2: add remaining slow path ops X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Add remaining get_count(), calc_mem_size() and populate() slow path mempool operations. Signed-off-by: Jerin Jacob Signed-off-by: Vamsi Attunuru --- drivers/mempool/octeontx2/otx2_mempool.c | 17 ++++++ drivers/mempool/octeontx2/otx2_mempool.h | 15 ++++- drivers/mempool/octeontx2/otx2_mempool_ops.c | 62 ++++++++++++++++++++ 3 files changed, 92 insertions(+), 2 deletions(-) diff --git a/drivers/mempool/octeontx2/otx2_mempool.c b/drivers/mempool/octeontx2/otx2_mempool.c index 1bcb86cf4..c47f95fb0 100644 --- a/drivers/mempool/octeontx2/otx2_mempool.c +++ b/drivers/mempool/octeontx2/otx2_mempool.c @@ -105,8 +105,24 @@ npa_lf_init(struct otx2_npa_lf *lf, uintptr_t base, uint8_t aura_sz, goto bmap_free; } + /* Allocate memory for nap_aura_lim memory */ + lf->aura_lim = rte_zmalloc("npa_aura_lim_mem", + sizeof(struct npa_aura_lim) * nr_pools, 0); + if (lf->aura_lim == NULL) { + rc = -ENOMEM; + goto qint_free; + } + + /* Init aura start & end limits */ + for (i = 0; i < nr_pools; i++) { + lf->aura_lim[i].ptr_start = UINT64_MAX; + lf->aura_lim[i].ptr_end = 0x0ull; + } + return 0; +qint_free: + rte_free(lf->npa_qint_mem); bmap_free: rte_bitmap_free(lf->npa_bmp); bmap_mem_free: @@ -123,6 +139,7 @@ npa_lf_fini(struct otx2_npa_lf *lf) if (!lf) return NPA_LF_ERR_PARAM; + rte_free(lf->aura_lim); rte_free(lf->npa_qint_mem); rte_bitmap_free(lf->npa_bmp); rte_free(lf->npa_bmp_mem); diff --git a/drivers/mempool/octeontx2/otx2_mempool.h b/drivers/mempool/octeontx2/otx2_mempool.h index efaa308b3..adcc0db24 100644 --- a/drivers/mempool/octeontx2/otx2_mempool.h +++ b/drivers/mempool/octeontx2/otx2_mempool.h @@ -29,6 +29,11 @@ struct otx2_npa_qint { uint8_t qintx; }; +struct npa_aura_lim { + uint64_t ptr_start; + uint64_t ptr_end; +}; + struct otx2_npa_lf { uint16_t qints; uintptr_t base; @@ -42,6 +47,7 @@ struct otx2_npa_lf { uint32_t stack_pg_ptrs; uint32_t stack_pg_bytes; struct rte_bitmap *npa_bmp; + struct npa_aura_lim *aura_lim; struct rte_pci_device *pci_dev; struct rte_intr_handle *intr_handle; }; @@ -185,11 +191,16 @@ npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova, uint64_t end_iova) { uint64_t reg = npa_lf_aura_handle_to_aura(aura_handle); + struct otx2_npa_lf *lf = otx2_npa_lf_obj_get(); + struct npa_aura_lim *lim = lf->aura_lim; - otx2_store_pair(start_iova, reg, + lim[reg].ptr_start = RTE_MIN(lim[reg].ptr_start, start_iova); + lim[reg].ptr_end = RTE_MAX(lim[reg].ptr_end, end_iova); + + otx2_store_pair(lim[reg].ptr_start, reg, npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_POOL_OP_PTR_START0); - otx2_store_pair(end_iova, reg, + otx2_store_pair(lim[reg].ptr_end, reg, npa_lf_aura_handle_to_base(aura_handle) + NPA_LF_POOL_OP_PTR_END0); } diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c b/drivers/mempool/octeontx2/otx2_mempool_ops.c index 94570319a..966b7d7f1 100644 --- a/drivers/mempool/octeontx2/otx2_mempool_ops.c +++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c @@ -7,6 +7,12 @@ #include "otx2_mempool.h" +static unsigned int +otx2_npa_get_count(const struct rte_mempool *mp) +{ + return (unsigned int)npa_lf_aura_op_available(mp->pool_id); +} + static int npa_lf_aura_pool_init(struct otx2_mbox *mbox, uint32_t aura_id, struct npa_aura_s *aura, struct npa_pool_s *pool) @@ -341,10 +347,66 @@ otx2_npa_free(struct rte_mempool *mp) otx2_npa_lf_fini(); } +static ssize_t +otx2_npa_calc_mem_size(const struct rte_mempool *mp, uint32_t obj_num, + uint32_t pg_shift, size_t *min_chunk_size, size_t *align) +{ + ssize_t mem_size; + + /* + * Simply need space for one more object to be able to + * fulfill alignment requirements. + */ + mem_size = rte_mempool_op_calc_mem_size_default(mp, obj_num + 1, + pg_shift, + min_chunk_size, align); + if (mem_size >= 0) { + /* + * Memory area which contains objects must be physically + * contiguous. + */ + *min_chunk_size = mem_size; + } + + return mem_size; +} + +static int +otx2_npa_populate(struct rte_mempool *mp, unsigned int max_objs, void *vaddr, + rte_iova_t iova, size_t len, + rte_mempool_populate_obj_cb_t *obj_cb, void *obj_cb_arg) +{ + size_t total_elt_sz; + size_t off; + + if (iova == RTE_BAD_IOVA) + return -EINVAL; + + total_elt_sz = mp->header_size + mp->elt_size + mp->trailer_size; + + /* Align object start address to a multiple of total_elt_sz */ + off = total_elt_sz - ((uintptr_t)vaddr % total_elt_sz); + + if (len < off) + return -EINVAL; + + vaddr = (char *)vaddr + off; + iova += off; + len -= off; + + npa_lf_aura_op_range_set(mp->pool_id, iova, iova + len); + + return rte_mempool_op_populate_default(mp, max_objs, vaddr, iova, len, + obj_cb, obj_cb_arg); +} + static struct rte_mempool_ops otx2_npa_ops = { .name = "octeontx2_npa", .alloc = otx2_npa_alloc, .free = otx2_npa_free, + .get_count = otx2_npa_get_count, + .calc_mem_size = otx2_npa_calc_mem_size, + .populate = otx2_npa_populate, }; MEMPOOL_REGISTER_OPS(otx2_npa_ops); -- 2.21.0