From: <jerinj@marvell.com>
To: <dev@dpdk.org>, Jerin Jacob <jerinj@marvell.com>,
Nithin Dabilpuram <ndabilpuram@marvell.com>,
Kiran Kumar K <kirankumark@marvell.com>
Cc: Pavan Nikhilesh <pbhagavatula@marvell.com>
Subject: [dpdk-dev] [PATCH v2 53/57] net/octeontx2: add Tx vector version
Date: Sun, 30 Jun 2019 23:36:05 +0530 [thread overview]
Message-ID: <20190630180609.36705-54-jerinj@marvell.com> (raw)
In-Reply-To: <20190630180609.36705-1-jerinj@marvell.com>
From: Nithin Dabilpuram <ndabilpuram@marvell.com>
Add vector version of packet transmit function.
Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
drivers/net/octeontx2/otx2_tx.c | 883 +++++++++++++++++++++++++++++++-
1 file changed, 882 insertions(+), 1 deletion(-)
diff --git a/drivers/net/octeontx2/otx2_tx.c b/drivers/net/octeontx2/otx2_tx.c
index 0ac5ea652..6bce55112 100644
--- a/drivers/net/octeontx2/otx2_tx.c
+++ b/drivers/net/octeontx2/otx2_tx.c
@@ -80,6 +80,859 @@ nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,
return pkts;
}
+#if defined(RTE_ARCH_ARM64)
+
+#define NIX_DESCS_PER_LOOP 4
+static __rte_always_inline uint16_t
+nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t pkts, const uint16_t flags)
+{
+ uint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;
+ uint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;
+ uint64_t *mbuf0, *mbuf1, *mbuf2, *mbuf3;
+ uint64x2_t senddesc01_w0, senddesc23_w0;
+ uint64x2_t senddesc01_w1, senddesc23_w1;
+ uint64x2_t sgdesc01_w0, sgdesc23_w0;
+ uint64x2_t sgdesc01_w1, sgdesc23_w1;
+ struct otx2_eth_txq *txq = tx_queue;
+ uint64_t *lmt_addr = txq->lmt_addr;
+ rte_iova_t io_addr = txq->io_addr;
+ uint64x2_t ltypes01, ltypes23;
+ uint64x2_t xtmp128, ytmp128;
+ uint64x2_t xmask01, xmask23;
+ uint64x2_t mbuf01, mbuf23;
+ uint64x2_t cmd00, cmd01;
+ uint64x2_t cmd10, cmd11;
+ uint64x2_t cmd20, cmd21;
+ uint64x2_t cmd30, cmd31;
+ uint64_t lmt_status, i;
+
+ pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);
+
+ NIX_XMIT_FC_OR_RETURN(txq, pkts);
+
+ /* Reduce the cached count */
+ txq->fc_cache_pkts -= pkts;
+
+ /* Lets commit any changes in the packet */
+ rte_cio_wmb();
+
+ senddesc01_w0 = vld1q_dup_u64(&txq->cmd[0]);
+ senddesc23_w0 = senddesc01_w0;
+ senddesc01_w1 = vdupq_n_u64(0);
+ senddesc23_w1 = senddesc01_w1;
+ sgdesc01_w0 = vld1q_dup_u64(&txq->cmd[2]);
+ sgdesc23_w0 = sgdesc01_w0;
+
+ for (i = 0; i < pkts; i += NIX_DESCS_PER_LOOP) {
+ mbuf01 = vld1q_u64((uint64_t *)tx_pkts);
+ mbuf23 = vld1q_u64((uint64_t *)(tx_pkts + 2));
+
+ /* Clear lower 32bit of SEND_HDR_W0 and SEND_SG_W0 */
+ senddesc01_w0 = vbicq_u64(senddesc01_w0,
+ vdupq_n_u64(0xFFFFFFFF));
+ sgdesc01_w0 = vbicq_u64(sgdesc01_w0,
+ vdupq_n_u64(0xFFFFFFFF));
+
+ senddesc23_w0 = senddesc01_w0;
+ sgdesc23_w0 = sgdesc01_w0;
+
+ tx_pkts = tx_pkts + NIX_DESCS_PER_LOOP;
+
+ /* Move mbufs to iova */
+ mbuf0 = (uint64_t *)vgetq_lane_u64(mbuf01, 0);
+ mbuf1 = (uint64_t *)vgetq_lane_u64(mbuf01, 1);
+ mbuf2 = (uint64_t *)vgetq_lane_u64(mbuf23, 0);
+ mbuf3 = (uint64_t *)vgetq_lane_u64(mbuf23, 1);
+
+ mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+ offsetof(struct rte_mbuf, buf_iova));
+ mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+ offsetof(struct rte_mbuf, buf_iova));
+ mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+ offsetof(struct rte_mbuf, buf_iova));
+ mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+ offsetof(struct rte_mbuf, buf_iova));
+ /*
+ * Get mbuf's, olflags, iova, pktlen, dataoff
+ * dataoff_iovaX.D[0] = iova,
+ * dataoff_iovaX.D[1](15:0) = mbuf->dataoff
+ * len_olflagsX.D[0] = ol_flags,
+ * len_olflagsX.D[1](63:32) = mbuf->pkt_len
+ */
+ dataoff_iova0 = vld1q_u64(mbuf0);
+ len_olflags0 = vld1q_u64(mbuf0 + 2);
+ dataoff_iova1 = vld1q_u64(mbuf1);
+ len_olflags1 = vld1q_u64(mbuf1 + 2);
+ dataoff_iova2 = vld1q_u64(mbuf2);
+ len_olflags2 = vld1q_u64(mbuf2 + 2);
+ dataoff_iova3 = vld1q_u64(mbuf3);
+ len_olflags3 = vld1q_u64(mbuf3 + 2);
+
+ if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
+ struct rte_mbuf *mbuf;
+ /* Set don't free bit if reference count > 1 */
+ xmask01 = vdupq_n_u64(0);
+ xmask23 = xmask01;
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf0 -
+ offsetof(struct rte_mbuf, buf_iova));
+
+ if (rte_pktmbuf_prefree_seg(mbuf) == NULL)
+ vsetq_lane_u64(0x80000, xmask01, 0);
+ else
+ __mempool_check_cookies(mbuf->pool,
+ (void **)&mbuf,
+ 1, 0);
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf1 -
+ offsetof(struct rte_mbuf, buf_iova));
+ if (rte_pktmbuf_prefree_seg(mbuf) == NULL)
+ vsetq_lane_u64(0x80000, xmask01, 1);
+ else
+ __mempool_check_cookies(mbuf->pool,
+ (void **)&mbuf,
+ 1, 0);
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf2 -
+ offsetof(struct rte_mbuf, buf_iova));
+ if (rte_pktmbuf_prefree_seg(mbuf) == NULL)
+ vsetq_lane_u64(0x80000, xmask23, 0);
+ else
+ __mempool_check_cookies(mbuf->pool,
+ (void **)&mbuf,
+ 1, 0);
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf3 -
+ offsetof(struct rte_mbuf, buf_iova));
+ if (rte_pktmbuf_prefree_seg(mbuf) == NULL)
+ vsetq_lane_u64(0x80000, xmask23, 1);
+ else
+ __mempool_check_cookies(mbuf->pool,
+ (void **)&mbuf,
+ 1, 0);
+ senddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);
+ senddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);
+ } else {
+ struct rte_mbuf *mbuf;
+ /* Mark mempool object as "put" since
+ * it is freed by NIX
+ */
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf0 -
+ offsetof(struct rte_mbuf, buf_iova));
+ __mempool_check_cookies(mbuf->pool, (void **)&mbuf,
+ 1, 0);
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf1 -
+ offsetof(struct rte_mbuf, buf_iova));
+ __mempool_check_cookies(mbuf->pool, (void **)&mbuf,
+ 1, 0);
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf2 -
+ offsetof(struct rte_mbuf, buf_iova));
+ __mempool_check_cookies(mbuf->pool, (void **)&mbuf,
+ 1, 0);
+
+ mbuf = (struct rte_mbuf *)((uintptr_t)mbuf3 -
+ offsetof(struct rte_mbuf, buf_iova));
+ __mempool_check_cookies(mbuf->pool, (void **)&mbuf,
+ 1, 0);
+ RTE_SET_USED(mbuf);
+ }
+
+ /* Move mbufs to point pool */
+ mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+ offsetof(struct rte_mbuf, pool) -
+ offsetof(struct rte_mbuf, buf_iova));
+ mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+ offsetof(struct rte_mbuf, pool) -
+ offsetof(struct rte_mbuf, buf_iova));
+ mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+ offsetof(struct rte_mbuf, pool) -
+ offsetof(struct rte_mbuf, buf_iova));
+ mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+ offsetof(struct rte_mbuf, pool) -
+ offsetof(struct rte_mbuf, buf_iova));
+
+ if (flags &
+ (NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
+ NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {
+ /* Get tx_offload for ol2, ol3, l2, l3 lengths */
+ /*
+ * E(8):OL2_LEN(7):OL3_LEN(9):E(24):L3_LEN(9):L2_LEN(7)
+ * E(8):OL2_LEN(7):OL3_LEN(9):E(24):L3_LEN(9):L2_LEN(7)
+ */
+
+ asm volatile ("LD1 {%[a].D}[0],[%[in]]\n\t" :
+ [a]"+w"(senddesc01_w1) :
+ [in]"r"(mbuf0 + 2) : "memory");
+
+ asm volatile ("LD1 {%[a].D}[1],[%[in]]\n\t" :
+ [a]"+w"(senddesc01_w1) :
+ [in]"r"(mbuf1 + 2) : "memory");
+
+ asm volatile ("LD1 {%[b].D}[0],[%[in]]\n\t" :
+ [b]"+w"(senddesc23_w1) :
+ [in]"r"(mbuf2 + 2) : "memory");
+
+ asm volatile ("LD1 {%[b].D}[1],[%[in]]\n\t" :
+ [b]"+w"(senddesc23_w1) :
+ [in]"r"(mbuf3 + 2) : "memory");
+
+ /* Get pool pointer alone */
+ mbuf0 = (uint64_t *)*mbuf0;
+ mbuf1 = (uint64_t *)*mbuf1;
+ mbuf2 = (uint64_t *)*mbuf2;
+ mbuf3 = (uint64_t *)*mbuf3;
+ } else {
+ /* Get pool pointer alone */
+ mbuf0 = (uint64_t *)*mbuf0;
+ mbuf1 = (uint64_t *)*mbuf1;
+ mbuf2 = (uint64_t *)*mbuf2;
+ mbuf3 = (uint64_t *)*mbuf3;
+ }
+
+ const uint8x16_t shuf_mask2 = {
+ 0x4, 0x5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xc, 0xd, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ };
+ xtmp128 = vzip2q_u64(len_olflags0, len_olflags1);
+ ytmp128 = vzip2q_u64(len_olflags2, len_olflags3);
+
+ /* Clear dataoff_iovaX.D[1] bits other than dataoff(15:0) */
+ const uint64x2_t and_mask0 = {
+ 0xFFFFFFFFFFFFFFFF,
+ 0x000000000000FFFF,
+ };
+
+ dataoff_iova0 = vandq_u64(dataoff_iova0, and_mask0);
+ dataoff_iova1 = vandq_u64(dataoff_iova1, and_mask0);
+ dataoff_iova2 = vandq_u64(dataoff_iova2, and_mask0);
+ dataoff_iova3 = vandq_u64(dataoff_iova3, and_mask0);
+
+ /*
+ * Pick only 16 bits of pktlen preset at bits 63:32
+ * and place them at bits 15:0.
+ */
+ xtmp128 = vqtbl1q_u8(xtmp128, shuf_mask2);
+ ytmp128 = vqtbl1q_u8(ytmp128, shuf_mask2);
+
+ /* Add pairwise to get dataoff + iova in sgdesc_w1 */
+ sgdesc01_w1 = vpaddq_u64(dataoff_iova0, dataoff_iova1);
+ sgdesc23_w1 = vpaddq_u64(dataoff_iova2, dataoff_iova3);
+
+ /* Orr both sgdesc_w0 and senddesc_w0 with 16 bits of
+ * pktlen at 15:0 position.
+ */
+ sgdesc01_w0 = vorrq_u64(sgdesc01_w0, xtmp128);
+ sgdesc23_w0 = vorrq_u64(sgdesc23_w0, ytmp128);
+ senddesc01_w0 = vorrq_u64(senddesc01_w0, xtmp128);
+ senddesc23_w0 = vorrq_u64(senddesc23_w0, ytmp128);
+
+ if ((flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&
+ !(flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {
+ /*
+ * Lookup table to translate ol_flags to
+ * il3/il4 types. But we still use ol3/ol4 types in
+ * senddesc_w1 as only one header processing is enabled.
+ */
+ const uint8x16_t tbl = {
+ /* [0-15] = il4type:il3type */
+ 0x04, /* none (IPv6 assumed) */
+ 0x14, /* PKT_TX_TCP_CKSUM (IPv6 assumed) */
+ 0x24, /* PKT_TX_SCTP_CKSUM (IPv6 assumed) */
+ 0x34, /* PKT_TX_UDP_CKSUM (IPv6 assumed) */
+ 0x03, /* PKT_TX_IP_CKSUM */
+ 0x13, /* PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM */
+ 0x23, /* PKT_TX_IP_CKSUM | PKT_TX_SCTP_CKSUM */
+ 0x33, /* PKT_TX_IP_CKSUM | PKT_TX_UDP_CKSUM */
+ 0x02, /* PKT_TX_IPV4 */
+ 0x12, /* PKT_TX_IPV4 | PKT_TX_TCP_CKSUM */
+ 0x22, /* PKT_TX_IPV4 | PKT_TX_SCTP_CKSUM */
+ 0x32, /* PKT_TX_IPV4 | PKT_TX_UDP_CKSUM */
+ 0x03, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM */
+ 0x13, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+ * PKT_TX_TCP_CKSUM
+ */
+ 0x23, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+ * PKT_TX_SCTP_CKSUM
+ */
+ 0x33, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+ * PKT_TX_UDP_CKSUM
+ */
+ };
+
+ /* Extract olflags to translate to iltypes */
+ xtmp128 = vzip1q_u64(len_olflags0, len_olflags1);
+ ytmp128 = vzip1q_u64(len_olflags2, len_olflags3);
+
+ /*
+ * E(47):L3_LEN(9):L2_LEN(7+z)
+ * E(47):L3_LEN(9):L2_LEN(7+z)
+ */
+ senddesc01_w1 = vshlq_n_u64(senddesc01_w1, 1);
+ senddesc23_w1 = vshlq_n_u64(senddesc23_w1, 1);
+
+ /* Move OLFLAGS bits 55:52 to 51:48
+ * with zeros preprended on the byte and rest
+ * don't care
+ */
+ xtmp128 = vshrq_n_u8(xtmp128, 4);
+ ytmp128 = vshrq_n_u8(ytmp128, 4);
+ /*
+ * E(48):L3_LEN(8):L2_LEN(z+7)
+ * E(48):L3_LEN(8):L2_LEN(z+7)
+ */
+ const int8x16_t tshft3 = {
+ -1, 0, 8, 8, 8, 8, 8, 8,
+ -1, 0, 8, 8, 8, 8, 8, 8,
+ };
+
+ senddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);
+ senddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);
+
+ /* Do the lookup */
+ ltypes01 = vqtbl1q_u8(tbl, xtmp128);
+ ltypes23 = vqtbl1q_u8(tbl, ytmp128);
+
+ /* Just use ld1q to retrieve aura
+ * when we don't need tx_offload
+ */
+ mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+ offsetof(struct rte_mempool, pool_id));
+
+ /* Pick only relevant fields i.e Bit 48:55 of iltype
+ * and place it in ol3/ol4type of senddesc_w1
+ */
+ const uint8x16_t shuf_mask0 = {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x6, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xE, 0xFF, 0xFF, 0xFF,
+ };
+
+ ltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);
+ ltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);
+
+ /* Prepare ol4ptr, ol3ptr from ol3len, ol2len.
+ * a [E(32):E(16):OL3(8):OL2(8)]
+ * a = a + (a << 8)
+ * a [E(32):E(16):(OL3+OL2):OL2]
+ * => E(32):E(16)::OL4PTR(8):OL3PTR(8)
+ */
+ senddesc01_w1 = vaddq_u8(senddesc01_w1,
+ vshlq_n_u16(senddesc01_w1, 8));
+ senddesc23_w1 = vaddq_u8(senddesc23_w1,
+ vshlq_n_u16(senddesc23_w1, 8));
+
+ /* Create first half of 4W cmd for 4 mbufs (sgdesc) */
+ cmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);
+ cmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);
+
+ xmask01 = vdupq_n_u64(0);
+ xmask23 = xmask01;
+ asm volatile ("LD1 {%[a].H}[0],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf0) : "memory");
+
+ asm volatile ("LD1 {%[a].H}[4],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf1) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[0],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf2) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[4],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf3) : "memory");
+ xmask01 = vshlq_n_u64(xmask01, 20);
+ xmask23 = vshlq_n_u64(xmask23, 20);
+
+ senddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);
+ senddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);
+ /* Move ltypes to senddesc*_w1 */
+ senddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);
+ senddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);
+
+ /* Create first half of 4W cmd for 4 mbufs (sendhdr) */
+ cmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);
+ cmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);
+ cmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);
+ cmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);
+
+ } else if (!(flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&
+ (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {
+ /*
+ * Lookup table to translate ol_flags to
+ * ol3/ol4 types.
+ */
+
+ const uint8x16_t tbl = {
+ /* [0-15] = ol4type:ol3type */
+ 0x00, /* none */
+ 0x03, /* OUTER_IP_CKSUM */
+ 0x02, /* OUTER_IPV4 */
+ 0x03, /* OUTER_IPV4 | OUTER_IP_CKSUM */
+ 0x04, /* OUTER_IPV6 */
+ 0x00, /* OUTER_IPV6 | OUTER_IP_CKSUM */
+ 0x00, /* OUTER_IPV6 | OUTER_IPV4 */
+ 0x00, /* OUTER_IPV6 | OUTER_IPV4 |
+ * OUTER_IP_CKSUM
+ */
+ 0x00, /* OUTER_UDP_CKSUM */
+ 0x33, /* OUTER_UDP_CKSUM | OUTER_IP_CKSUM */
+ 0x32, /* OUTER_UDP_CKSUM | OUTER_IPV4 */
+ 0x33, /* OUTER_UDP_CKSUM | OUTER_IPV4 |
+ * OUTER_IP_CKSUM
+ */
+ 0x34, /* OUTER_UDP_CKSUM | OUTER_IPV6 */
+ 0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+ * OUTER_IP_CKSUM
+ */
+ 0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+ * OUTER_IPV4
+ */
+ 0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+ * OUTER_IPV4 | OUTER_IP_CKSUM
+ */
+ };
+
+ /* Extract olflags to translate to iltypes */
+ xtmp128 = vzip1q_u64(len_olflags0, len_olflags1);
+ ytmp128 = vzip1q_u64(len_olflags2, len_olflags3);
+
+ /*
+ * E(47):OL3_LEN(9):OL2_LEN(7+z)
+ * E(47):OL3_LEN(9):OL2_LEN(7+z)
+ */
+ const uint8x16_t shuf_mask5 = {
+ 0x6, 0x5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xE, 0xD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+ };
+ senddesc01_w1 = vqtbl1q_u8(senddesc01_w1, shuf_mask5);
+ senddesc23_w1 = vqtbl1q_u8(senddesc23_w1, shuf_mask5);
+
+ /* Extract outer ol flags only */
+ const uint64x2_t o_cksum_mask = {
+ 0x1C00020000000000,
+ 0x1C00020000000000,
+ };
+
+ xtmp128 = vandq_u64(xtmp128, o_cksum_mask);
+ ytmp128 = vandq_u64(ytmp128, o_cksum_mask);
+
+ /* Extract OUTER_UDP_CKSUM bit 41 and
+ * move it to bit 61
+ */
+
+ xtmp128 = xtmp128 | vshlq_n_u64(xtmp128, 20);
+ ytmp128 = ytmp128 | vshlq_n_u64(ytmp128, 20);
+
+ /* Shift oltype by 2 to start nibble from BIT(56)
+ * instead of BIT(58)
+ */
+ xtmp128 = vshrq_n_u8(xtmp128, 2);
+ ytmp128 = vshrq_n_u8(ytmp128, 2);
+ /*
+ * E(48):L3_LEN(8):L2_LEN(z+7)
+ * E(48):L3_LEN(8):L2_LEN(z+7)
+ */
+ const int8x16_t tshft3 = {
+ -1, 0, 8, 8, 8, 8, 8, 8,
+ -1, 0, 8, 8, 8, 8, 8, 8,
+ };
+
+ senddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);
+ senddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);
+
+ /* Do the lookup */
+ ltypes01 = vqtbl1q_u8(tbl, xtmp128);
+ ltypes23 = vqtbl1q_u8(tbl, ytmp128);
+
+ /* Just use ld1q to retrieve aura
+ * when we don't need tx_offload
+ */
+ mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+ offsetof(struct rte_mempool, pool_id));
+
+ /* Pick only relevant fields i.e Bit 56:63 of oltype
+ * and place it in ol3/ol4type of senddesc_w1
+ */
+ const uint8x16_t shuf_mask0 = {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x7, 0xFF, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xF, 0xFF, 0xFF, 0xFF,
+ };
+
+ ltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);
+ ltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);
+
+ /* Prepare ol4ptr, ol3ptr from ol3len, ol2len.
+ * a [E(32):E(16):OL3(8):OL2(8)]
+ * a = a + (a << 8)
+ * a [E(32):E(16):(OL3+OL2):OL2]
+ * => E(32):E(16)::OL4PTR(8):OL3PTR(8)
+ */
+ senddesc01_w1 = vaddq_u8(senddesc01_w1,
+ vshlq_n_u16(senddesc01_w1, 8));
+ senddesc23_w1 = vaddq_u8(senddesc23_w1,
+ vshlq_n_u16(senddesc23_w1, 8));
+
+ /* Create second half of 4W cmd for 4 mbufs (sgdesc) */
+ cmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);
+ cmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);
+
+ xmask01 = vdupq_n_u64(0);
+ xmask23 = xmask01;
+ asm volatile ("LD1 {%[a].H}[0],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf0) : "memory");
+
+ asm volatile ("LD1 {%[a].H}[4],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf1) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[0],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf2) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[4],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf3) : "memory");
+ xmask01 = vshlq_n_u64(xmask01, 20);
+ xmask23 = vshlq_n_u64(xmask23, 20);
+
+ senddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);
+ senddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);
+ /* Move ltypes to senddesc*_w1 */
+ senddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);
+ senddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);
+
+ /* Create first half of 4W cmd for 4 mbufs (sendhdr) */
+ cmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);
+ cmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);
+ cmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);
+ cmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);
+
+ } else if ((flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&
+ (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {
+ /* Lookup table to translate ol_flags to
+ * ol4type, ol3type, il4type, il3type of senddesc_w1
+ */
+ const uint8x16x2_t tbl = {
+ {
+ {
+ /* [0-15] = il4type:il3type */
+ 0x04, /* none (IPv6) */
+ 0x14, /* PKT_TX_TCP_CKSUM (IPv6) */
+ 0x24, /* PKT_TX_SCTP_CKSUM (IPv6) */
+ 0x34, /* PKT_TX_UDP_CKSUM (IPv6) */
+ 0x03, /* PKT_TX_IP_CKSUM */
+ 0x13, /* PKT_TX_IP_CKSUM |
+ * PKT_TX_TCP_CKSUM
+ */
+ 0x23, /* PKT_TX_IP_CKSUM |
+ * PKT_TX_SCTP_CKSUM
+ */
+ 0x33, /* PKT_TX_IP_CKSUM |
+ * PKT_TX_UDP_CKSUM
+ */
+ 0x02, /* PKT_TX_IPV4 */
+ 0x12, /* PKT_TX_IPV4 |
+ * PKT_TX_TCP_CKSUM
+ */
+ 0x22, /* PKT_TX_IPV4 |
+ * PKT_TX_SCTP_CKSUM
+ */
+ 0x32, /* PKT_TX_IPV4 |
+ * PKT_TX_UDP_CKSUM
+ */
+ 0x03, /* PKT_TX_IPV4 |
+ * PKT_TX_IP_CKSUM
+ */
+ 0x13, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+ * PKT_TX_TCP_CKSUM
+ */
+ 0x23, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+ * PKT_TX_SCTP_CKSUM
+ */
+ 0x33, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+ * PKT_TX_UDP_CKSUM
+ */
+ },
+
+ {
+ /* [16-31] = ol4type:ol3type */
+ 0x00, /* none */
+ 0x03, /* OUTER_IP_CKSUM */
+ 0x02, /* OUTER_IPV4 */
+ 0x03, /* OUTER_IPV4 | OUTER_IP_CKSUM */
+ 0x04, /* OUTER_IPV6 */
+ 0x00, /* OUTER_IPV6 | OUTER_IP_CKSUM */
+ 0x00, /* OUTER_IPV6 | OUTER_IPV4 */
+ 0x00, /* OUTER_IPV6 | OUTER_IPV4 |
+ * OUTER_IP_CKSUM
+ */
+ 0x00, /* OUTER_UDP_CKSUM */
+ 0x33, /* OUTER_UDP_CKSUM |
+ * OUTER_IP_CKSUM
+ */
+ 0x32, /* OUTER_UDP_CKSUM |
+ * OUTER_IPV4
+ */
+ 0x33, /* OUTER_UDP_CKSUM |
+ * OUTER_IPV4 | OUTER_IP_CKSUM
+ */
+ 0x34, /* OUTER_UDP_CKSUM |
+ * OUTER_IPV6
+ */
+ 0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+ * OUTER_IP_CKSUM
+ */
+ 0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+ * OUTER_IPV4
+ */
+ 0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+ * OUTER_IPV4 | OUTER_IP_CKSUM
+ */
+ },
+ }
+ };
+
+ /* Extract olflags to translate to oltype & iltype */
+ xtmp128 = vzip1q_u64(len_olflags0, len_olflags1);
+ ytmp128 = vzip1q_u64(len_olflags2, len_olflags3);
+
+ /*
+ * E(8):OL2_LN(7):OL3_LN(9):E(23):L3_LN(9):L2_LN(7+z)
+ * E(8):OL2_LN(7):OL3_LN(9):E(23):L3_LN(9):L2_LN(7+z)
+ */
+ const uint32x4_t tshft_4 = {
+ 1, 0,
+ 1, 0,
+ };
+ senddesc01_w1 = vshlq_u32(senddesc01_w1, tshft_4);
+ senddesc23_w1 = vshlq_u32(senddesc23_w1, tshft_4);
+
+ /*
+ * E(32):L3_LEN(8):L2_LEN(7+Z):OL3_LEN(8):OL2_LEN(7+Z)
+ * E(32):L3_LEN(8):L2_LEN(7+Z):OL3_LEN(8):OL2_LEN(7+Z)
+ */
+ const uint8x16_t shuf_mask5 = {
+ 0x6, 0x5, 0x0, 0x1, 0xFF, 0xFF, 0xFF, 0xFF,
+ 0xE, 0xD, 0x8, 0x9, 0xFF, 0xFF, 0xFF, 0xFF,
+ };
+ senddesc01_w1 = vqtbl1q_u8(senddesc01_w1, shuf_mask5);
+ senddesc23_w1 = vqtbl1q_u8(senddesc23_w1, shuf_mask5);
+
+ /* Extract outer and inner header ol_flags */
+ const uint64x2_t oi_cksum_mask = {
+ 0x1CF0020000000000,
+ 0x1CF0020000000000,
+ };
+
+ xtmp128 = vandq_u64(xtmp128, oi_cksum_mask);
+ ytmp128 = vandq_u64(ytmp128, oi_cksum_mask);
+
+ /* Extract OUTER_UDP_CKSUM bit 41 and
+ * move it to bit 61
+ */
+
+ xtmp128 = xtmp128 | vshlq_n_u64(xtmp128, 20);
+ ytmp128 = ytmp128 | vshlq_n_u64(ytmp128, 20);
+
+ /* Shift right oltype by 2 and iltype by 4
+ * to start oltype nibble from BIT(58)
+ * instead of BIT(56) and iltype nibble from BIT(48)
+ * instead of BIT(52).
+ */
+ const int8x16_t tshft5 = {
+ 8, 8, 8, 8, 8, 8, -4, -2,
+ 8, 8, 8, 8, 8, 8, -4, -2,
+ };
+
+ xtmp128 = vshlq_u8(xtmp128, tshft5);
+ ytmp128 = vshlq_u8(ytmp128, tshft5);
+ /*
+ * E(32):L3_LEN(8):L2_LEN(8):OL3_LEN(8):OL2_LEN(8)
+ * E(32):L3_LEN(8):L2_LEN(8):OL3_LEN(8):OL2_LEN(8)
+ */
+ const int8x16_t tshft3 = {
+ -1, 0, -1, 0, 0, 0, 0, 0,
+ -1, 0, -1, 0, 0, 0, 0, 0,
+ };
+
+ senddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);
+ senddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);
+
+ /* Mark Bit(4) of oltype */
+ const uint64x2_t oi_cksum_mask2 = {
+ 0x1000000000000000,
+ 0x1000000000000000,
+ };
+
+ xtmp128 = vorrq_u64(xtmp128, oi_cksum_mask2);
+ ytmp128 = vorrq_u64(ytmp128, oi_cksum_mask2);
+
+ /* Do the lookup */
+ ltypes01 = vqtbl2q_u8(tbl, xtmp128);
+ ltypes23 = vqtbl2q_u8(tbl, ytmp128);
+
+ /* Just use ld1q to retrieve aura
+ * when we don't need tx_offload
+ */
+ mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+ offsetof(struct rte_mempool, pool_id));
+
+ /* Pick only relevant fields i.e Bit 48:55 of iltype and
+ * Bit 56:63 of oltype and place it in corresponding
+ * place in senddesc_w1.
+ */
+ const uint8x16_t shuf_mask0 = {
+ 0xFF, 0xFF, 0xFF, 0xFF, 0x7, 0x6, 0xFF, 0xFF,
+ 0xFF, 0xFF, 0xFF, 0xFF, 0xF, 0xE, 0xFF, 0xFF,
+ };
+
+ ltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);
+ ltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);
+
+ /* Prepare l4ptr, l3ptr, ol4ptr, ol3ptr from
+ * l3len, l2len, ol3len, ol2len.
+ * a [E(32):L3(8):L2(8):OL3(8):OL2(8)]
+ * a = a + (a << 8)
+ * a [E:(L3+L2):(L2+OL3):(OL3+OL2):OL2]
+ * a = a + (a << 16)
+ * a [E:(L3+L2+OL3+OL2):(L2+OL3+OL2):(OL3+OL2):OL2]
+ * => E(32):IL4PTR(8):IL3PTR(8):OL4PTR(8):OL3PTR(8)
+ */
+ senddesc01_w1 = vaddq_u8(senddesc01_w1,
+ vshlq_n_u32(senddesc01_w1, 8));
+ senddesc23_w1 = vaddq_u8(senddesc23_w1,
+ vshlq_n_u32(senddesc23_w1, 8));
+
+ /* Create second half of 4W cmd for 4 mbufs (sgdesc) */
+ cmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);
+ cmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);
+
+ /* Continue preparing l4ptr, l3ptr, ol4ptr, ol3ptr */
+ senddesc01_w1 = vaddq_u8(senddesc01_w1,
+ vshlq_n_u32(senddesc01_w1, 16));
+ senddesc23_w1 = vaddq_u8(senddesc23_w1,
+ vshlq_n_u32(senddesc23_w1, 16));
+
+ xmask01 = vdupq_n_u64(0);
+ xmask23 = xmask01;
+ asm volatile ("LD1 {%[a].H}[0],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf0) : "memory");
+
+ asm volatile ("LD1 {%[a].H}[4],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf1) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[0],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf2) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[4],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf3) : "memory");
+ xmask01 = vshlq_n_u64(xmask01, 20);
+ xmask23 = vshlq_n_u64(xmask23, 20);
+
+ senddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);
+ senddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);
+ /* Move ltypes to senddesc*_w1 */
+ senddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);
+ senddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);
+
+ /* Create first half of 4W cmd for 4 mbufs (sendhdr) */
+ cmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);
+ cmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);
+ cmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);
+ cmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);
+ } else {
+ /* Just use ld1q to retrieve aura
+ * when we don't need tx_offload
+ */
+ mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+ offsetof(struct rte_mempool, pool_id));
+ mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+ offsetof(struct rte_mempool, pool_id));
+ xmask01 = vdupq_n_u64(0);
+ xmask23 = xmask01;
+ asm volatile ("LD1 {%[a].H}[0],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf0) : "memory");
+
+ asm volatile ("LD1 {%[a].H}[4],[%[in]]\n\t" :
+ [a]"+w"(xmask01) : [in]"r"(mbuf1) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[0],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf2) : "memory");
+
+ asm volatile ("LD1 {%[b].H}[4],[%[in]]\n\t" :
+ [b]"+w"(xmask23) : [in]"r"(mbuf3) : "memory");
+ xmask01 = vshlq_n_u64(xmask01, 20);
+ xmask23 = vshlq_n_u64(xmask23, 20);
+
+ senddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);
+ senddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);
+
+ /* Create 4W cmd for 4 mbufs (sendhdr, sgdesc) */
+ cmd00 = vzip1q_u64(senddesc01_w0, senddesc01_w1);
+ cmd01 = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd10 = vzip2q_u64(senddesc01_w0, senddesc01_w1);
+ cmd11 = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);
+ cmd20 = vzip1q_u64(senddesc23_w0, senddesc23_w1);
+ cmd21 = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);
+ cmd30 = vzip2q_u64(senddesc23_w0, senddesc23_w1);
+ cmd31 = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);
+ }
+
+ do {
+ vst1q_u64(lmt_addr, cmd00);
+ vst1q_u64(lmt_addr + 2, cmd01);
+ vst1q_u64(lmt_addr + 4, cmd10);
+ vst1q_u64(lmt_addr + 6, cmd11);
+ vst1q_u64(lmt_addr + 8, cmd20);
+ vst1q_u64(lmt_addr + 10, cmd21);
+ vst1q_u64(lmt_addr + 12, cmd30);
+ vst1q_u64(lmt_addr + 14, cmd31);
+ lmt_status = otx2_lmt_submit(io_addr);
+
+ } while (lmt_status == 0);
+ }
+
+ return pkts;
+}
+
+#else
+static __rte_always_inline uint16_t
+nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
+ uint16_t pkts, const uint16_t flags)
+{
+ RTE_SET_USED(tx_queue);
+ RTE_SET_USED(tx_pkts);
+ RTE_SET_USED(pkts);
+ RTE_SET_USED(flags);
+ return 0;
+}
+#endif
+
#define T(name, f4, f3, f2, f1, f0, sz, flags) \
static uint16_t __rte_noinline __hot \
otx2_nix_xmit_pkts_ ## name(void *tx_queue, \
@@ -107,6 +960,21 @@ otx2_nix_xmit_pkts_mseg_ ## name(void *tx_queue, \
NIX_TX_FASTPATH_MODES
#undef T
+#define T(name, f4, f3, f2, f1, f0, sz, flags) \
+static uint16_t __rte_noinline __hot \
+otx2_nix_xmit_pkts_vec_ ## name(void *tx_queue, \
+ struct rte_mbuf **tx_pkts, uint16_t pkts) \
+{ \
+ /* VLAN and TSTMP is not supported by vec */ \
+ if ((flags) & NIX_TX_OFFLOAD_VLAN_QINQ_F || \
+ (flags) & NIX_TX_OFFLOAD_TSTAMP_F) \
+ return 0; \
+ return nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, (flags)); \
+}
+
+NIX_TX_FASTPATH_MODES
+#undef T
+
static inline void
pick_tx_func(struct rte_eth_dev *eth_dev,
const eth_tx_burst_t tx_burst[2][2][2][2][2])
@@ -143,7 +1011,20 @@ NIX_TX_FASTPATH_MODES
#undef T
};
- pick_tx_func(eth_dev, nix_eth_tx_burst);
+ const eth_tx_burst_t nix_eth_tx_vec_burst[2][2][2][2][2] = {
+#define T(name, f4, f3, f2, f1, f0, sz, flags) \
+ [f4][f3][f2][f1][f0] = otx2_nix_xmit_pkts_vec_ ## name,
+
+NIX_TX_FASTPATH_MODES
+#undef T
+ };
+
+ if (dev->scalar_ena ||
+ (dev->tx_offload_flags &
+ (NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSTAMP_F)))
+ pick_tx_func(eth_dev, nix_eth_tx_burst);
+ else
+ pick_tx_func(eth_dev, nix_eth_tx_vec_burst);
if (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
pick_tx_func(eth_dev, nix_eth_tx_burst_mseg);
--
2.21.0
next prev parent reply other threads:[~2019-06-30 18:14 UTC|newest]
Thread overview: 196+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-02 15:23 [dpdk-dev] [PATCH v1 00/58] OCTEON TX2 Ethdev driver jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 01/58] net/octeontx2: add build infrastructure jerinj
2019-06-06 15:33 ` Ferruh Yigit
2019-06-06 16:40 ` [dpdk-dev] [EXT] " Jerin Jacob Kollanukkaran
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 02/58] net/octeontx2: add ethdev probe and remove jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 03/58] net/octeontx2: add device init and uninit jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 04/58] net/octeontx2: add devargs parsing functions jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 05/58] net/octeontx2: handle device error interrupts jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 06/58] net/octeontx2: add info get operation jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 07/58] net/octeontx2: add device configure operation jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 08/58] net/octeontx2: handle queue specific error interrupts jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 09/58] net/octeontx2: add context debug utils jerinj
2019-06-06 15:41 ` Ferruh Yigit
2019-06-06 16:04 ` [dpdk-dev] [EXT] " Jerin Jacob Kollanukkaran
2019-06-06 16:18 ` Ferruh Yigit
2019-06-06 16:27 ` Jerin Jacob Kollanukkaran
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 10/58] net/octeontx2: add register dump support jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 11/58] net/octeontx2: add link stats operations jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 12/58] net/octeontx2: add basic stats operation jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 13/58] net/octeontx2: add extended stats operations jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 14/58] net/octeontx2: add promiscuous and allmulticast mode jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 15/58] net/octeontx2: add unicast MAC filter jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 16/58] net/octeontx2: add RSS support jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 17/58] net/octeontx2: add Rx queue setup and release jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 18/58] net/octeontx2: add Tx " jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 19/58] net/octeontx2: handle port reconfigure jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 20/58] net/octeontx2: add queue start and stop operations jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 21/58] net/octeontx2: introduce traffic manager jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 22/58] net/octeontx2: alloc and free TM HW resources jerinj
2019-06-02 15:23 ` [dpdk-dev] [PATCH v1 23/58] net/octeontx2: configure " jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 24/58] net/octeontx2: enable Tx through traffic manager jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 25/58] net/octeontx2: add ptype support jerinj
2019-06-06 15:50 ` Ferruh Yigit
2019-06-06 15:59 ` Jerin Jacob Kollanukkaran
2019-06-06 16:20 ` Ferruh Yigit
2019-06-07 8:54 ` Jerin Jacob Kollanukkaran
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 26/58] net/octeontx2: add link status set operations jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 27/58] net/octeontx2: add queue info and pool supported operations jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 28/58] net/octeontx2: add Rx and Tx descriptor operations jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 29/58] net/octeontx2: add module EEPROM dump jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 30/58] net/octeontx2: add flow control support jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 31/58] net/octeontx2: add PTP base support jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 32/58] net/octeontx2: add remaining PTP operations jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 33/58] net/octeontx2: introducing flow driver jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 34/58] net/octeontx2: flow utility functions jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 35/58] net/octeontx2: flow mailbox utility jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 36/58] net/octeontx2: add flow MCAM utility functions jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 37/58] net/octeontx2: add flow parsing for outer layers jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 38/58] net/octeontx2: adding flow parsing for inner layers jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 39/58] net/octeontx2: add flow actions support jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 40/58] net/octeontx2: add flow operations jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 41/58] net/octeontx2: add additional " jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 42/58] net/octeontx2: add flow init and fini jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 43/58] net/octeontx2: connect flow API to ethdev ops jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 44/58] net/octeontx2: implement VLAN utility functions jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 45/58] net/octeontx2: support VLAN offloads jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 46/58] net/octeontx2: support VLAN filters jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 47/58] net/octeontx2: support VLAN TPID and PVID for Tx jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 48/58] net/octeontx2: add FW version get operation jerinj
2019-06-06 16:06 ` Ferruh Yigit
2019-06-07 5:51 ` [dpdk-dev] [EXT] " Vamsi Krishna Attunuru
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 49/58] net/octeontx2: add Rx burst support jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 50/58] net/octeontx2: add Rx multi segment version jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 51/58] net/octeontx2: add Rx vector version jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 52/58] net/octeontx2: add Tx burst support jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 53/58] net/octeontx2: add Tx multi segment version jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 54/58] net/octeontx2: add Tx vector version jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 55/58] net/octeontx2: add device start operation jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 56/58] net/octeontx2: add device stop and close operations jerinj
2019-06-06 16:23 ` Ferruh Yigit
2019-06-07 5:11 ` Nithin Dabilpuram
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 57/58] net/octeontx2: add MTU set operation jerinj
2019-06-02 15:24 ` [dpdk-dev] [PATCH v1 58/58] doc: add Marvell OCTEON TX2 ethdev documentation jerinj
2019-06-06 16:50 ` Ferruh Yigit
2019-06-07 3:42 ` Jerin Jacob Kollanukkaran
2019-06-06 15:23 ` [dpdk-dev] [PATCH v1 00/58] OCTEON TX2 Ethdev driver Ferruh Yigit
2019-06-10 9:54 ` [dpdk-dev] [EXT] " Jerin Jacob Kollanukkaran
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 00/57] " jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 01/57] net/octeontx2: add build and doc infrastructure jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 02/57] net/octeontx2: add ethdev probe and remove jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 03/57] net/octeontx2: add device init and uninit jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 04/57] net/octeontx2: add devargs parsing functions jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 05/57] net/octeontx2: handle device error interrupts jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 06/57] net/octeontx2: add info get operation jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 07/57] net/octeontx2: add device configure operation jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 08/57] net/octeontx2: handle queue specific error interrupts jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 09/57] net/octeontx2: add context debug utils jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 10/57] net/octeontx2: add register dump support jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 11/57] net/octeontx2: add link stats operations jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 12/57] net/octeontx2: add basic stats operation jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 13/57] net/octeontx2: add extended stats operations jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 14/57] net/octeontx2: add promiscuous and allmulticast mode jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 15/57] net/octeontx2: add unicast MAC filter jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 16/57] net/octeontx2: add RSS support jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 17/57] net/octeontx2: add Rx queue setup and release jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 18/57] net/octeontx2: add Tx " jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 19/57] net/octeontx2: handle port reconfigure jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 20/57] net/octeontx2: add queue start and stop operations jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 21/57] net/octeontx2: introduce traffic manager jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 22/57] net/octeontx2: alloc and free TM HW resources jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 23/57] net/octeontx2: configure " jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 24/57] net/octeontx2: enable Tx through traffic manager jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 25/57] net/octeontx2: add ptype support jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 26/57] net/octeontx2: add queue info and pool supported operations jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 27/57] net/octeontx2: add Rx and Tx descriptor operations jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 28/57] net/octeontx2: add module EEPROM dump jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 29/57] net/octeontx2: add flow control support jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 30/57] net/octeontx2: add PTP base support jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 31/57] net/octeontx2: add remaining PTP operations jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 32/57] net/octeontx2: introducing flow driver jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 33/57] net/octeontx2: add flow utility functions jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 34/57] net/octeontx2: add flow mbox " jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 35/57] net/octeontx2: add flow MCAM " jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 36/57] net/octeontx2: add flow parsing for outer layers jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 37/57] net/octeontx2: add flow actions support jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 38/57] net/octeontx2: add flow parse " jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 39/57] net/octeontx2: add flow operations jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 40/57] net/octeontx2: add flow destroy ops support jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 41/57] net/octeontx2: add flow init and fini jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 42/57] net/octeontx2: connect flow API to ethdev ops jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 43/57] net/octeontx2: implement VLAN utility functions jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 44/57] net/octeontx2: support VLAN offloads jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 45/57] net/octeontx2: support VLAN filters jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 46/57] net/octeontx2: support VLAN TPID and PVID for Tx jerinj
2019-06-30 18:05 ` [dpdk-dev] [PATCH v2 47/57] net/octeontx2: add FW version get operation jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 48/57] net/octeontx2: add Rx burst support jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 49/57] net/octeontx2: add Rx multi segment version jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 50/57] net/octeontx2: add Rx vector version jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 51/57] net/octeontx2: add Tx burst support jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 52/57] net/octeontx2: add Tx multi segment version jerinj
2019-06-30 18:06 ` jerinj [this message]
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 54/57] net/octeontx2: add device start operation jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 55/57] net/octeontx2: add device stop and close operations jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 56/57] net/octeontx2: add MTU set operation jerinj
2019-06-30 18:06 ` [dpdk-dev] [PATCH v2 57/57] net/octeontx2: add Rx interrupts support jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 00/58] OCTEON TX2 Ethdev driver jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 01/58] net/octeontx2: add build and doc infrastructure jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 02/58] net/octeontx2: add ethdev probe and remove jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 03/58] net/octeontx2: add device init and uninit jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 04/58] net/octeontx2: add devargs parsing functions jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 05/58] net/octeontx2: handle device error interrupts jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 06/58] net/octeontx2: add info get operation jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 07/58] net/octeontx2: add device configure operation jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 08/58] net/octeontx2: handle queue specific error interrupts jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 09/58] net/octeontx2: add context debug utils jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 10/58] net/octeontx2: add register dump support jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 11/58] net/octeontx2: add link stats operations jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 12/58] net/octeontx2: add basic stats operation jerinj
2019-07-03 8:41 ` [dpdk-dev] [PATCH v3 13/58] net/octeontx2: add extended stats operations jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 14/58] net/octeontx2: add promiscuous and allmulticast mode jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 15/58] net/octeontx2: add unicast MAC filter jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 16/58] net/octeontx2: add RSS support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 17/58] net/octeontx2: add Rx queue setup and release jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 18/58] net/octeontx2: add Tx " jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 19/58] net/octeontx2: handle port reconfigure jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 20/58] net/octeontx2: add queue start and stop operations jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 21/58] net/octeontx2: introduce traffic manager jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 22/58] net/octeontx2: alloc and free TM HW resources jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 23/58] net/octeontx2: configure " jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 24/58] net/octeontx2: enable Tx through traffic manager jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 25/58] net/octeontx2: add ptype support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 26/58] net/octeontx2: add queue info and pool supported operations jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 27/58] net/octeontx2: add Rx and Tx descriptor operations jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 28/58] net/octeontx2: add module EEPROM dump jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 29/58] net/octeontx2: add flow control support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 30/58] net/octeontx2: add PTP base support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 31/58] net/octeontx2: add remaining PTP operations jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 32/58] net/octeontx2: introducing flow driver jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 33/58] net/octeontx2: add flow utility functions jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 34/58] net/octeontx2: add flow mbox " jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 35/58] net/octeontx2: add flow MCAM " jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 36/58] net/octeontx2: add flow parsing for outer layers jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 37/58] net/octeontx2: add flow actions support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 38/58] net/octeontx2: add flow parse " jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 39/58] net/octeontx2: add flow operations jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 40/58] net/octeontx2: add flow destroy ops support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 41/58] net/octeontx2: add flow init and fini jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 42/58] net/octeontx2: connect flow API to ethdev ops jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 43/58] net/octeontx2: implement VLAN utility functions jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 44/58] net/octeontx2: support VLAN offloads jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 45/58] net/octeontx2: support VLAN filters jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 46/58] net/octeontx2: support VLAN TPID and PVID for Tx jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 47/58] net/octeontx2: add FW version get operation jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 48/58] net/octeontx2: add Rx burst support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 49/58] net/octeontx2: add Rx multi segment version jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 50/58] net/octeontx2: add Rx vector version jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 51/58] net/octeontx2: add Tx burst support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 52/58] net/octeontx2: add Tx multi segment version jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 53/58] net/octeontx2: add Tx vector version jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 54/58] net/octeontx2: add device start operation jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 55/58] net/octeontx2: add device stop and close operations jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 56/58] net/octeontx2: add MTU set operation jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 57/58] net/octeontx2: add Rx interrupts support jerinj
2019-07-03 8:42 ` [dpdk-dev] [PATCH v3 58/58] net/octeontx2: add link status set operations jerinj
2019-07-03 20:22 ` [dpdk-dev] [PATCH v3 00/58] OCTEON TX2 Ethdev driver Jerin Jacob Kollanukkaran
2019-07-04 18:11 ` Ferruh Yigit
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