[dpdk-dev] [PATCH 0/4] ethdev: add GRE key field to flow API

[dpdk-dev] [PATCH 0/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

[1] https://patches.dpdk.org/patch/53432/

Xiaoyu Min (4):
  ethdev: add GRE key field to flow API
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits
  app/testpmd: match GRE's key and present bits

 app/test-pmd/cmdline_flow.c                 | 33 +++++++++
 doc/guides/prog_guide/rte_flow.rst          |  9 +++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 ++
 drivers/net/mlx5/mlx5_flow.c                | 51 ++++++++++++-
 drivers/net/mlx5/mlx5_flow.h                |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 80 +++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h                 |  6 +-
 lib/librte_ethdev/rte_flow.c                |  1 +
 lib/librte_ethdev/rte_flow.h                | 27 +++++++
 9 files changed, 214 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

Add new rte_flow_item_gre_key in order to match the optional key field.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/prog_guide/rte_flow.rst |  9 +++++++++
 lib/librte_ethdev/rte_flow.c       |  1 +
 lib/librte_ethdev/rte_flow.h       | 27 +++++++++++++++++++++++++++
 3 files changed, 37 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index a34d012e55..e900a53e3c 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -980,6 +980,15 @@ Matches a GRE header.
 - ``protocol``: protocol type.
 - Default ``mask`` matches protocol only.
 
+Item: ``GRE_KEY``
+^^^^^^^^^^^^^^^^^
+
+Matches a GRE key field.
+This should be preceded by item ``GRE``
+
+- ``key``: key value.
+- Default ``mask`` matches key only.
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
index 3277be1edb..1cd5f4d263 100644
--- a/lib/librte_ethdev/rte_flow.c
+++ b/lib/librte_ethdev/rte_flow.c
@@ -55,6 +55,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
 	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
 	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
+	MK_FLOW_ITEM(GRE_KEY, sizeof(struct rte_flow_item_gre_key)),
 	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
 	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
 	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
index f3a8fb103f..a708ccd53b 100644
--- a/lib/librte_ethdev/rte_flow.h
+++ b/lib/librte_ethdev/rte_flow.h
@@ -289,6 +289,13 @@ enum rte_flow_item_type {
 	 */
 	RTE_FLOW_ITEM_TYPE_GRE,
 
+	/**
+	 * Matches a GRE optional key field.
+	 *
+	 * See struct rte_flow_item_gre_key.
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_KEY,
+
 	/**
 	 * [META]
 	 *
@@ -856,6 +863,26 @@ static const struct rte_flow_item_gre rte_flow_item_gre_mask = {
 };
 #endif
 
+/**
+ * RTE_FLOW_ITEM_GRE_KEY.
+ *
+ * Matches the presence of a GRE key.
+ *
+ * Normally preceding by:
+ *
+ * - RTE_FLOW_ITEM_TYPE_GRE
+ */
+struct rte_flow_item_gre_key {
+	rte_be32_t key; /**< Application specific key value (K bit). */
+};
+
+/** Default mask for RTE_FLOW_ITEM_TYPE_GRE_KEY. */
+#ifndef __cplusplus
+static const struct rte_flow_item_gre_key rte_flow_item_gre_key_mask = {
+	.key = RTE_BE32(UINT32_MAX),
+};
+#endif
+
 /**
  * RTE_FLOW_ITEM_TYPE_FUZZY
  *
-- 
2.21.0

[dpdk-dev] [PATCH 2/4] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index c03eb4c376..4cb04c32ff 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1612,6 +1612,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1619,6 +1620,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH 3/4] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c    | 49 +++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h    |  5 +++
 drivers/net/mlx5/mlx5_flow_dv.c | 80 +++++++++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h     |  6 ++-
 4 files changed, 138 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 4cb04c32ff..4f0583eead 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1564,6 +1564,49 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] target_protocol
+ *   The next protocol in the previous item.
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error)
+{
+	const struct rte_flow_item_gre_key *mask = item->mask;
+	int ret = 0;
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!mask)
+		mask = &rte_flow_item_gre_key_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&rte_flow_item_gre_key_mask,
+		 sizeof(struct rte_flow_item_gre_key), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1589,6 +1632,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1608,7 +1655,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index b6654200cb..0d83539cc9 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -50,6 +50,8 @@
 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
 
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -480,6 +482,9 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 933ad0b819..eca926d670 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2177,6 +2177,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 				return ret;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -2922,6 +2929,43 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const struct rte_flow_item_gre_key *key_m = item->mask;
+	const struct rte_flow_item_gre_key *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &rte_flow_item_gre_key_mask;
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(key_m->key) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32(key_v->key & key_m->key) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(key_m->key) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32(key_v->key & key_m->key) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -2945,6 +2989,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -2965,6 +3023,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -3995,6 +4070,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+							   match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1a199580c5..4022770b7b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -416,7 +416,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

[dpdk-dev] [PATCH 4/4] app/testpmd: match GRE's key and present bits

[Xiaoyu Min]

support matching on GRE key and present bits (C,K,S)

example testpmd command could be:
  testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
          gre crksv is 0x2000 crksv mask 0xb000 /
	  gre_key key is 0x12345678 / end
	  actions rss queues 1 0 end / mark id 196 / end

Which will match GRE packet with k present bit set and key value is
0x12345678.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 app/test-pmd/cmdline_flow.c                 | 33 +++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +++
 2 files changed, 37 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 201bd9de56..c8e0785a41 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -148,6 +148,9 @@ enum index {
 	ITEM_MPLS_LABEL,
 	ITEM_GRE,
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_GRE_KEY,
+	ITEM_GRE_KEY_KEY,
 	ITEM_FUZZY,
 	ITEM_FUZZY_THRESH,
 	ITEM_GTP,
@@ -595,6 +598,7 @@ static const enum index next_item[] = {
 	ITEM_NVGRE,
 	ITEM_MPLS,
 	ITEM_GRE,
+	ITEM_GRE_KEY,
 	ITEM_FUZZY,
 	ITEM_GTP,
 	ITEM_GTPC,
@@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
 
 static const enum index item_gre[] = {
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_NEXT,
+	ZERO,
+};
+
+static const enum index item_gre_key[] = {
+	ITEM_GRE_KEY_KEY,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -1898,6 +1909,28 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
 					     protocol)),
 	},
+	[ITEM_GRE_CRKSV] = {
+		.name = "crksv",
+		.help = "GRE's first word (bit0 - bit15)",
+		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
+					     c_rsvd0_ver)),
+	},
+	[ITEM_GRE_KEY] = {
+		.name = "gre_key",
+		.help = "match GRE Key",
+		.priv = PRIV_ITEM(GRE_KEY,
+				  sizeof(struct rte_flow_item_gre_key)),
+		.next = NEXT(item_gre_key),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_KEY_KEY] = {
+		.name = "key",
+		.help = "GRE key",
+		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre_key,
+					     key)),
+	},
 	[ITEM_FUZZY] = {
 		.name = "fuzzy",
 		.help = "fuzzy pattern match, expect faster than default",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index cb83a3ce8a..fc3ba8a009 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``protocol {unsigned}``: protocol type.
 
+- ``gre_key``: match GRE optional key field.
+
+  - ``key {unsigned}``: key value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
2.21.0

Re: [dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API

[Ori Kam]

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Xiaoyu Min
> Sent: Monday, June 24, 2019 6:40 PM
> To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; John McNamara
> <john.mcnamara@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Thomas Monjalon <thomas@monjalon.net>;
> Ferruh Yigit <ferruh.yigit@intel.com>; Andrew Rybchenko
> <arybchenko@solarflare.com>
> Cc: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API
> 
> Add new rte_flow_item_gre_key in order to match the optional key field.
> 
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> ---


Acked-by: Ori Kam <orika@mellanox.com>
Thanks,
Ori Kam

Re: [dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API

[Ori Kam]

Hi Jack,

I know I acked this patch, but after Dekel patch, 
https://patches.dpdk.org/patch/55667/

Where it was decided to remove structures for just one variable, 
and simply use the value. I wish if possible that you will also modify this
patch to match this new convention.


Thanks,
Ori Kam

> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Xiaoyu Min
> Sent: Monday, June 24, 2019 6:40 PM
> To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; John McNamara
> <john.mcnamara@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Thomas Monjalon <thomas@monjalon.net>;
> Ferruh Yigit <ferruh.yigit@intel.com>; Andrew Rybchenko
> <arybchenko@solarflare.com>
> Cc: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API
> 
> Add new rte_flow_item_gre_key in order to match the optional key field.
> 
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> ---
>  doc/guides/prog_guide/rte_flow.rst |  9 +++++++++
>  lib/librte_ethdev/rte_flow.c       |  1 +
>  lib/librte_ethdev/rte_flow.h       | 27 +++++++++++++++++++++++++++
>  3 files changed, 37 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/rte_flow.rst
> b/doc/guides/prog_guide/rte_flow.rst
> index a34d012e55..e900a53e3c 100644
> --- a/doc/guides/prog_guide/rte_flow.rst
> +++ b/doc/guides/prog_guide/rte_flow.rst
> @@ -980,6 +980,15 @@ Matches a GRE header.
>  - ``protocol``: protocol type.
>  - Default ``mask`` matches protocol only.
> 
> +Item: ``GRE_KEY``
> +^^^^^^^^^^^^^^^^^
> +
> +Matches a GRE key field.
> +This should be preceded by item ``GRE``
> +
> +- ``key``: key value.
> +- Default ``mask`` matches key only.
> +
>  Item: ``FUZZY``
>  ^^^^^^^^^^^^^^^
> 
> diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
> index 3277be1edb..1cd5f4d263 100644
> --- a/lib/librte_ethdev/rte_flow.c
> +++ b/lib/librte_ethdev/rte_flow.c
> @@ -55,6 +55,7 @@ static const struct rte_flow_desc_data
> rte_flow_desc_item[] = {
>  	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
>  	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
>  	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
> +	MK_FLOW_ITEM(GRE_KEY, sizeof(struct rte_flow_item_gre_key)),
>  	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
>  	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
>  	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
> diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
> index f3a8fb103f..a708ccd53b 100644
> --- a/lib/librte_ethdev/rte_flow.h
> +++ b/lib/librte_ethdev/rte_flow.h
> @@ -289,6 +289,13 @@ enum rte_flow_item_type {
>  	 */
>  	RTE_FLOW_ITEM_TYPE_GRE,
> 
> +	/**
> +	 * Matches a GRE optional key field.
> +	 *
> +	 * See struct rte_flow_item_gre_key.
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_KEY,
> +
>  	/**
>  	 * [META]
>  	 *
> @@ -856,6 +863,26 @@ static const struct rte_flow_item_gre
> rte_flow_item_gre_mask = {
>  };
>  #endif
> 
> +/**
> + * RTE_FLOW_ITEM_GRE_KEY.
> + *
> + * Matches the presence of a GRE key.
> + *
> + * Normally preceding by:
> + *
> + * - RTE_FLOW_ITEM_TYPE_GRE
> + */
> +struct rte_flow_item_gre_key {
> +	rte_be32_t key; /**< Application specific key value (K bit). */
> +};
> +
> +/** Default mask for RTE_FLOW_ITEM_TYPE_GRE_KEY. */
> +#ifndef __cplusplus
> +static const struct rte_flow_item_gre_key rte_flow_item_gre_key_mask = {
> +	.key = RTE_BE32(UINT32_MAX),
> +};
> +#endif
> +
>  /**
>   * RTE_FLOW_ITEM_TYPE_FUZZY
>   *
> --
> 2.21.0

Re: [dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API

[Jack Min]

On Mon, 19-07-01, 13:40, Ori Kam wrote:
> Hi Jack,
> 
> I know I acked this patch, but after Dekel patch, 
> https://patches.dpdk.org/patch/55667/
> 
> Where it was decided to remove structures for just one variable, 
> and simply use the value. I wish if possible that you will also modify this
> patch to match this new convention.
> 
> 
OK, I'll remove the struct in v2 patch for the new convention.

> Thanks,
> Ori Kam
> 
> > -----Original Message-----
> > From: dev <dev-bounces@dpdk.org> On Behalf Of Xiaoyu Min
> > Sent: Monday, June 24, 2019 6:40 PM
> > To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; John McNamara
> > <john.mcnamara@intel.com>; Marko Kovacevic
> > <marko.kovacevic@intel.com>; Thomas Monjalon <thomas@monjalon.net>;
> > Ferruh Yigit <ferruh.yigit@intel.com>; Andrew Rybchenko
> > <arybchenko@solarflare.com>
> > Cc: dev@dpdk.org
> > Subject: [dpdk-dev] [PATCH 1/4] ethdev: add GRE key field to flow API
> > 
> > Add new rte_flow_item_gre_key in order to match the optional key field.
> > 
> > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> > ---
> >  doc/guides/prog_guide/rte_flow.rst |  9 +++++++++
> >  lib/librte_ethdev/rte_flow.c       |  1 +
> >  lib/librte_ethdev/rte_flow.h       | 27 +++++++++++++++++++++++++++
> >  3 files changed, 37 insertions(+)
> > 
> > diff --git a/doc/guides/prog_guide/rte_flow.rst
> > b/doc/guides/prog_guide/rte_flow.rst
> > index a34d012e55..e900a53e3c 100644
> > --- a/doc/guides/prog_guide/rte_flow.rst
> > +++ b/doc/guides/prog_guide/rte_flow.rst
> > @@ -980,6 +980,15 @@ Matches a GRE header.
> >  - ``protocol``: protocol type.
> >  - Default ``mask`` matches protocol only.
> > 
> > +Item: ``GRE_KEY``
> > +^^^^^^^^^^^^^^^^^
> > +
> > +Matches a GRE key field.
> > +This should be preceded by item ``GRE``
> > +
> > +- ``key``: key value.
> > +- Default ``mask`` matches key only.
> > +
> >  Item: ``FUZZY``
> >  ^^^^^^^^^^^^^^^
> > 
> > diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
> > index 3277be1edb..1cd5f4d263 100644
> > --- a/lib/librte_ethdev/rte_flow.c
> > +++ b/lib/librte_ethdev/rte_flow.c
> > @@ -55,6 +55,7 @@ static const struct rte_flow_desc_data
> > rte_flow_desc_item[] = {
> >  	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
> >  	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
> >  	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
> > +	MK_FLOW_ITEM(GRE_KEY, sizeof(struct rte_flow_item_gre_key)),
> >  	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
> >  	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
> >  	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
> > diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
> > index f3a8fb103f..a708ccd53b 100644
> > --- a/lib/librte_ethdev/rte_flow.h
> > +++ b/lib/librte_ethdev/rte_flow.h
> > @@ -289,6 +289,13 @@ enum rte_flow_item_type {
> >  	 */
> >  	RTE_FLOW_ITEM_TYPE_GRE,
> > 
> > +	/**
> > +	 * Matches a GRE optional key field.
> > +	 *
> > +	 * See struct rte_flow_item_gre_key.
> > +	 */
> > +	RTE_FLOW_ITEM_TYPE_GRE_KEY,
> > +
> >  	/**
> >  	 * [META]
> >  	 *
> > @@ -856,6 +863,26 @@ static const struct rte_flow_item_gre
> > rte_flow_item_gre_mask = {
> >  };
> >  #endif
> > 
> > +/**
> > + * RTE_FLOW_ITEM_GRE_KEY.
> > + *
> > + * Matches the presence of a GRE key.
> > + *
> > + * Normally preceding by:
> > + *
> > + * - RTE_FLOW_ITEM_TYPE_GRE
> > + */
> > +struct rte_flow_item_gre_key {
> > +	rte_be32_t key; /**< Application specific key value (K bit). */
> > +};
> > +
> > +/** Default mask for RTE_FLOW_ITEM_TYPE_GRE_KEY. */
> > +#ifndef __cplusplus
> > +static const struct rte_flow_item_gre_key rte_flow_item_gre_key_mask = {
> > +	.key = RTE_BE32(UINT32_MAX),
> > +};
> > +#endif
> > +
> >  /**
> >   * RTE_FLOW_ITEM_TYPE_FUZZY
> >   *
> > --
> > 2.21.0
> 

[dpdk-dev] [PATCH v2 0/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

[1] https://patches.dpdk.org/patch/53432/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention

---
Xiaoyu Min (4):
  ethdev: add GRE key field to flow API
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits
  app/testpmd: match GRE's key and present bits

 app/test-pmd/cmdline_flow.c                 | 40 ++++++++++
 doc/guides/prog_guide/rte_flow.rst          |  8 ++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +
 drivers/net/mlx5/mlx5_flow.c                | 52 ++++++++++++-
 drivers/net/mlx5/mlx5_flow.h                |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 81 +++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h                 |  6 +-
 lib/librte_ethdev/rte_flow.c                |  1 +
 lib/librte_ethdev/rte_flow.h                |  7 ++
 9 files changed, 202 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v2 1/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

Add new rte_flow_item_gre_key in order to match the optional key field.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/prog_guide/rte_flow.rst | 8 ++++++++
 lib/librte_ethdev/rte_flow.c       | 1 +
 lib/librte_ethdev/rte_flow.h       | 7 +++++++
 3 files changed, 16 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index a34d012e55..f4b7baa3c3 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -980,6 +980,14 @@ Matches a GRE header.
 - ``protocol``: protocol type.
 - Default ``mask`` matches protocol only.
 
+Item: ``GRE_KEY``
+^^^^^^^^^^^^^^^^^
+
+Matches a GRE key field.
+This should be preceded by item ``GRE``
+
+- Value to be matched is a big-endian 32 bit integer
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
index 3277be1edb..f3e56d0bbe 100644
--- a/lib/librte_ethdev/rte_flow.c
+++ b/lib/librte_ethdev/rte_flow.c
@@ -55,6 +55,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
 	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
 	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
+	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
 	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
 	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
 	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
index f3a8fb103f..5d3702a44c 100644
--- a/lib/librte_ethdev/rte_flow.h
+++ b/lib/librte_ethdev/rte_flow.h
@@ -289,6 +289,13 @@ enum rte_flow_item_type {
 	 */
 	RTE_FLOW_ITEM_TYPE_GRE,
 
+	/**
+	 * Matches a GRE optional key field.
+	 *
+	 * The value should a big-endian 32bit integer.
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_KEY,
+
 	/**
 	 * [META]
 	 *
-- 
2.21.0

[dpdk-dev] [PATCH v2 2/4] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index c03eb4c376..4cb04c32ff 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1612,6 +1612,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1619,6 +1620,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v2 3/4] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c    | 50 +++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h    |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c | 81 +++++++++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h     |  6 ++-
 4 files changed, 140 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 4cb04c32ff..d8309af49e 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1564,6 +1564,50 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] target_protocol
+ *   The next protocol in the previous item.
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error)
+{
+	const struct rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!mask)
+		mask = (void *)&gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1589,6 +1633,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1608,7 +1656,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index b6654200cb..0d83539cc9 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -50,6 +50,8 @@
 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
 
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -480,6 +482,9 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 933ad0b819..8de39ef3fa 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2177,6 +2177,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 				return ret;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -2922,6 +2929,44 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -2945,6 +2990,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -2965,6 +3024,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -3995,6 +4071,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1a199580c5..4022770b7b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -416,7 +416,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

[dpdk-dev] [PATCH v2 4/4] app/testpmd: match GRE's key and present bits

[Xiaoyu Min]

support matching on GRE key and present bits (C,K,S)

example testpmd command could be:
  testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
          gre crksv is 0x2000 crksv mask 0xb000 /
	  gre_key key is 0x12345678 / end
	  actions rss queues 1 0 end / mark id 196 / end

Which will match GRE packet with k present bit set and key value is
0x12345678.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 app/test-pmd/cmdline_flow.c                 | 40 +++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +++
 2 files changed, 44 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 201bd9de56..9fd6452a72 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -148,6 +148,9 @@ enum index {
 	ITEM_MPLS_LABEL,
 	ITEM_GRE,
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_GRE_KEY,
+	ITEM_GRE_KEY_KEY,
 	ITEM_FUZZY,
 	ITEM_FUZZY_THRESH,
 	ITEM_GTP,
@@ -485,6 +488,14 @@ struct token {
 		.size = sizeof(((s *)0)->f), \
 	})
 
+/** Same as ARGS_ENTRY_HTON() for a single argument, without structure. */
+#define ARGS_ENTRY_HTON_VALUE(s) \
+	(&(const struct arg){ \
+		.hton = 1, \
+		.offset = 0, \
+		.size = sizeof(s), \
+	})
+
 /** Parser output buffer layout expected by cmd_flow_parsed(). */
 struct buffer {
 	enum index command; /**< Flow command. */
@@ -595,6 +606,7 @@ static const enum index next_item[] = {
 	ITEM_NVGRE,
 	ITEM_MPLS,
 	ITEM_GRE,
+	ITEM_GRE_KEY,
 	ITEM_FUZZY,
 	ITEM_GTP,
 	ITEM_GTPC,
@@ -755,6 +767,13 @@ static const enum index item_mpls[] = {
 
 static const enum index item_gre[] = {
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_NEXT,
+	ZERO,
+};
+
+static const enum index item_gre_key[] = {
+	ITEM_GRE_KEY_KEY,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -1898,6 +1917,27 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
 					     protocol)),
 	},
+	[ITEM_GRE_CRKSV] = {
+		.name = "crksv",
+		.help = "GRE's first word (bit0 - bit15)",
+		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
+					     c_rsvd0_ver)),
+	},
+	[ITEM_GRE_KEY] = {
+		.name = "gre_key",
+		.help = "match GRE Key",
+		.priv = PRIV_ITEM(GRE_KEY,
+				  sizeof(rte_be32_t)),
+		.next = NEXT(item_gre_key),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_KEY_KEY] = {
+		.name = "key",
+		.help = "GRE key",
+		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON_VALUE(rte_be32_t)),
+	},
 	[ITEM_FUZZY] = {
 		.name = "fuzzy",
 		.help = "fuzzy pattern match, expect faster than default",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index cb83a3ce8a..fc3ba8a009 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``protocol {unsigned}``: protocol type.
 
+- ``gre_key``: match GRE optional key field.
+
+  - ``key {unsigned}``: key value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
2.21.0

[dpdk-dev] [PATCH v3 0/4] match on GRE's key

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

Patch 4 is based on patch [2], which needs to be merged before this one.

[1] https://patches.dpdk.org/patch/53432/
[2] https://patches.dpdk.org/patch/55773/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention
v3:
  * updated release note
  * fixed one bug
---
Xiaoyu Min (4):
  ethdev: add GRE key field to flow API
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits
  app/testpmd: match GRE's key and present bits

 app/test-pmd/cmdline_flow.c                 | 32 ++++++++
 doc/guides/prog_guide/rte_flow.rst          |  8 ++
 doc/guides/rel_notes/release_19_08.rst      |  5 ++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +
 drivers/net/mlx5/mlx5_flow.c                | 52 ++++++++++++-
 drivers/net/mlx5/mlx5_flow.h                |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 81 +++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h                 |  6 +-
 lib/librte_ethdev/rte_flow.c                |  1 +
 lib/librte_ethdev/rte_flow.h                |  7 ++
 10 files changed, 199 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v3 1/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

Add new rte_flow_item_gre_key in order to match the optional key field.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/prog_guide/rte_flow.rst | 8 ++++++++
 lib/librte_ethdev/rte_flow.c       | 1 +
 lib/librte_ethdev/rte_flow.h       | 7 +++++++
 3 files changed, 16 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index a34d012e55..f4b7baa3c3 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -980,6 +980,14 @@ Matches a GRE header.
 - ``protocol``: protocol type.
 - Default ``mask`` matches protocol only.
 
+Item: ``GRE_KEY``
+^^^^^^^^^^^^^^^^^
+
+Matches a GRE key field.
+This should be preceded by item ``GRE``
+
+- Value to be matched is a big-endian 32 bit integer
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
index 3277be1edb..f3e56d0bbe 100644
--- a/lib/librte_ethdev/rte_flow.c
+++ b/lib/librte_ethdev/rte_flow.c
@@ -55,6 +55,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
 	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
 	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
+	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
 	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
 	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
 	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
index f3a8fb103f..5d3702a44c 100644
--- a/lib/librte_ethdev/rte_flow.h
+++ b/lib/librte_ethdev/rte_flow.h
@@ -289,6 +289,13 @@ enum rte_flow_item_type {
 	 */
 	RTE_FLOW_ITEM_TYPE_GRE,
 
+	/**
+	 * Matches a GRE optional key field.
+	 *
+	 * The value should a big-endian 32bit integer.
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_KEY,
+
 	/**
 	 * [META]
 	 *
-- 
2.21.0

[dpdk-dev] [PATCH v3 2/4] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index cd04c446b5..8c43c848c0 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1610,6 +1610,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1617,6 +1618,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v3 3/4] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/rel_notes/release_19_08.rst |  5 ++
 drivers/net/mlx5/mlx5_flow.c           | 50 +++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 81 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 145 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 57364afd8b..0fea9e14f6 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -126,6 +126,11 @@ New Features
   Added telemetry mode to l3fwd-power application to report
   application level busyness, empty and full polls of rte_eth_rx_burst().
 
+* **Updated Mellanox mlx5 driver.**
+
+   Updated Mellanox mlx5 driver with new features and improvements, including:
+
+   * Added support for matching on GRE's key and C,K,S present bits.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 8c43c848c0..b9e2768541 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1562,6 +1562,50 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] target_protocol
+ *   The next protocol in the previous item.
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error)
+{
+	const rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!mask)
+		mask = &gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1587,6 +1631,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1606,7 +1654,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 65cfdbda9f..d6f53a4d24 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -50,6 +50,8 @@
 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
 
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -462,6 +464,9 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 933ad0b819..8de39ef3fa 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2177,6 +2177,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 				return ret;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -2922,6 +2929,44 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -2945,6 +2990,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -2965,6 +3024,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -3995,6 +4071,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1a199580c5..4022770b7b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -416,7 +416,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

[dpdk-dev] [PATCH v3 4/4] app/testpmd: match GRE's key and present bits

[Xiaoyu Min]

support matching on GRE key and present bits (C,K,S)

example testpmd command could be:
  testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
          gre crksv is 0x2000 crksv mask 0xb000 /
	  gre_key key is 0x12345678 / end
	  actions rss queues 1 0 end / mark id 196 / end

Which will match GRE packet with k present bit set and key value is
0x12345678.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
** This patch is based on patch [1]

[1] https://patches.dpdk.org/patch/55773/
---
 app/test-pmd/cmdline_flow.c                 | 32 +++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +++
 2 files changed, 36 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 201bd9de56..8504cc8bc1 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -148,6 +148,9 @@ enum index {
 	ITEM_MPLS_LABEL,
 	ITEM_GRE,
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_GRE_KEY,
+	ITEM_GRE_KEY_KEY,
 	ITEM_FUZZY,
 	ITEM_FUZZY_THRESH,
 	ITEM_GTP,
@@ -595,6 +598,7 @@ static const enum index next_item[] = {
 	ITEM_NVGRE,
 	ITEM_MPLS,
 	ITEM_GRE,
+	ITEM_GRE_KEY,
 	ITEM_FUZZY,
 	ITEM_GTP,
 	ITEM_GTPC,
@@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
 
 static const enum index item_gre[] = {
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_NEXT,
+	ZERO,
+};
+
+static const enum index item_gre_key[] = {
+	ITEM_GRE_KEY_KEY,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -1898,6 +1909,27 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
 					     protocol)),
 	},
+	[ITEM_GRE_CRKSV] = {
+		.name = "crksv",
+		.help = "GRE's first word (bit0 - bit15)",
+		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
+					     c_rsvd0_ver)),
+	},
+	[ITEM_GRE_KEY] = {
+		.name = "gre_key",
+		.help = "match GRE Key",
+		.priv = PRIV_ITEM(GRE_KEY,
+				  sizeof(rte_be32_t)),
+		.next = NEXT(item_gre_key),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_KEY_KEY] = {
+		.name = "key",
+		.help = "GRE key",
+		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
+	},
 	[ITEM_FUZZY] = {
 		.name = "fuzzy",
 		.help = "fuzzy pattern match, expect faster than default",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index cb83a3ce8a..fc3ba8a009 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``protocol {unsigned}``: protocol type.
 
+- ``gre_key``: match GRE optional key field.
+
+  - ``key {unsigned}``: key value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
2.21.0

[dpdk-dev] [PATCH v4 0/4] match on GRE's key

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

Patch 4 is based on patch [2], which needs to be merged before this one.

[1] https://patches.dpdk.org/patch/53432/
[2] https://patches.dpdk.org/patch/55773/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention
v3:
  * updated release note
  * fixed one bug
v4:
  * resend patchs in thread mode
---
Xiaoyu Min (4):
  ethdev: add GRE key field to flow API
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits
  app/testpmd: match GRE's key and present bits

 app/test-pmd/cmdline_flow.c                 | 32 ++++++++
 doc/guides/prog_guide/rte_flow.rst          |  8 ++
 doc/guides/rel_notes/release_19_08.rst      |  5 ++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +
 drivers/net/mlx5/mlx5_flow.c                | 52 ++++++++++++-
 drivers/net/mlx5/mlx5_flow.h                |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 81 +++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h                 |  6 +-
 lib/librte_ethdev/rte_flow.c                |  1 +
 lib/librte_ethdev/rte_flow.h                |  7 ++
 10 files changed, 199 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v4 1/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

Add new rte_flow_item_gre_key in order to match the optional key field.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/prog_guide/rte_flow.rst | 8 ++++++++
 lib/librte_ethdev/rte_flow.c       | 1 +
 lib/librte_ethdev/rte_flow.h       | 7 +++++++
 3 files changed, 16 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index a34d012e55..f4b7baa3c3 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -980,6 +980,14 @@ Matches a GRE header.
 - ``protocol``: protocol type.
 - Default ``mask`` matches protocol only.
 
+Item: ``GRE_KEY``
+^^^^^^^^^^^^^^^^^
+
+Matches a GRE key field.
+This should be preceded by item ``GRE``
+
+- Value to be matched is a big-endian 32 bit integer
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
index 3277be1edb..f3e56d0bbe 100644
--- a/lib/librte_ethdev/rte_flow.c
+++ b/lib/librte_ethdev/rte_flow.c
@@ -55,6 +55,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
 	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
 	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
+	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
 	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
 	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
 	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
index f3a8fb103f..5d3702a44c 100644
--- a/lib/librte_ethdev/rte_flow.h
+++ b/lib/librte_ethdev/rte_flow.h
@@ -289,6 +289,13 @@ enum rte_flow_item_type {
 	 */
 	RTE_FLOW_ITEM_TYPE_GRE,
 
+	/**
+	 * Matches a GRE optional key field.
+	 *
+	 * The value should a big-endian 32bit integer.
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_KEY,
+
 	/**
 	 * [META]
 	 *
-- 
2.21.0

[dpdk-dev] [PATCH v4 2/4] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index cd04c446b5..8c43c848c0 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1610,6 +1610,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1617,6 +1618,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v4 3/4] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/rel_notes/release_19_08.rst |  5 ++
 drivers/net/mlx5/mlx5_flow.c           | 50 +++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 81 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 145 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 57364afd8b..0fea9e14f6 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -126,6 +126,11 @@ New Features
   Added telemetry mode to l3fwd-power application to report
   application level busyness, empty and full polls of rte_eth_rx_burst().
 
+* **Updated Mellanox mlx5 driver.**
+
+   Updated Mellanox mlx5 driver with new features and improvements, including:
+
+   * Added support for matching on GRE's key and C,K,S present bits.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 8c43c848c0..b9e2768541 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1562,6 +1562,50 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] target_protocol
+ *   The next protocol in the previous item.
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error)
+{
+	const rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!mask)
+		mask = &gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1587,6 +1631,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1606,7 +1654,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 65cfdbda9f..d6f53a4d24 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -50,6 +50,8 @@
 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
 
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -462,6 +464,9 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 933ad0b819..8de39ef3fa 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2177,6 +2177,13 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 				return ret;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -2922,6 +2929,44 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -2945,6 +2990,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -2965,6 +3024,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -3995,6 +4071,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1a199580c5..4022770b7b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -416,7 +416,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

[dpdk-dev] [PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Xiaoyu Min]

support matching on GRE key and present bits (C,K,S)

example testpmd command could be:
  testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
          gre crksv is 0x2000 crksv mask 0xb000 /
	  gre_key key is 0x12345678 / end
	  actions rss queues 1 0 end / mark id 196 / end

Which will match GRE packet with k present bit set and key value is
0x12345678.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
** This patch is based on patch [1]

[1] https://patches.dpdk.org/patch/55773/
---
 app/test-pmd/cmdline_flow.c                 | 32 +++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +++
 2 files changed, 36 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 201bd9de56..8504cc8bc1 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -148,6 +148,9 @@ enum index {
 	ITEM_MPLS_LABEL,
 	ITEM_GRE,
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_GRE_KEY,
+	ITEM_GRE_KEY_KEY,
 	ITEM_FUZZY,
 	ITEM_FUZZY_THRESH,
 	ITEM_GTP,
@@ -595,6 +598,7 @@ static const enum index next_item[] = {
 	ITEM_NVGRE,
 	ITEM_MPLS,
 	ITEM_GRE,
+	ITEM_GRE_KEY,
 	ITEM_FUZZY,
 	ITEM_GTP,
 	ITEM_GTPC,
@@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
 
 static const enum index item_gre[] = {
 	ITEM_GRE_PROTO,
+	ITEM_GRE_CRKSV,
+	ITEM_NEXT,
+	ZERO,
+};
+
+static const enum index item_gre_key[] = {
+	ITEM_GRE_KEY_KEY,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -1898,6 +1909,27 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
 					     protocol)),
 	},
+	[ITEM_GRE_CRKSV] = {
+		.name = "crksv",
+		.help = "GRE's first word (bit0 - bit15)",
+		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
+					     c_rsvd0_ver)),
+	},
+	[ITEM_GRE_KEY] = {
+		.name = "gre_key",
+		.help = "match GRE Key",
+		.priv = PRIV_ITEM(GRE_KEY,
+				  sizeof(rte_be32_t)),
+		.next = NEXT(item_gre_key),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_KEY_KEY] = {
+		.name = "key",
+		.help = "GRE key",
+		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
+	},
 	[ITEM_FUZZY] = {
 		.name = "fuzzy",
 		.help = "fuzzy pattern match, expect faster than default",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index cb83a3ce8a..fc3ba8a009 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``protocol {unsigned}``: protocol type.
 
+- ``gre_key``: match GRE optional key field.
+
+  - ``key {unsigned}``: key value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
2.21.0

Re: [dpdk-dev] [Suspected-Phishing][PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Ori Kam]

> -----Original Message-----
> From: Xiaoyu Min <jackmin@mellanox.com>
> Sent: Tuesday, July 2, 2019 12:46 PM
> To: Ori Kam <orika@mellanox.com>; Adrien Mazarguil
> <adrien.mazarguil@6wind.com>; Wenzhuo Lu <wenzhuo.lu@intel.com>;
> Jingjing Wu <jingjing.wu@intel.com>; Bernard Iremonger
> <bernard.iremonger@intel.com>; John McNamara
> <john.mcnamara@intel.com>; Marko Kovacevic <marko.kovacevic@intel.com>
> Cc: dev@dpdk.org
> Subject: [Suspected-Phishing][PATCH v4 4/4] app/testpmd: match GRE's key and
> present bits
> 
> support matching on GRE key and present bits (C,K,S)
> 
> example testpmd command could be:
>   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
>           gre crksv is 0x2000 crksv mask 0xb000 /
> 	  gre_key key is 0x12345678 / end
> 	  actions rss queues 1 0 end / mark id 196 / end
> 
> Which will match GRE packet with k present bit set and key value is
> 0x12345678.
> 
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> ---

Acked-by: Ori Kam <orika@mellanox.com>
Thanks,
Ori Kam

> ** This patch is based on patch [1]
> 
> [1]
> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatches.d
> pdk.org%2Fpatch%2F55773%2F&amp;data=02%7C01%7Corika%40mellanox.co
> m%7C1d141143694542013e2a08d6fed23185%7Ca652971c7d2e4d9ba6a4d149
> 256f461b%7C0%7C0%7C636976576061576503&amp;sdata=d3lj4YEdQn96zqvb
> U5VDWvIu40IUFSNAaug51eOSHns%3D&amp;reserved=0
> ---
>  app/test-pmd/cmdline_flow.c                 | 32 +++++++++++++++++++++
>  doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
> index 201bd9de56..8504cc8bc1 100644
> --- a/app/test-pmd/cmdline_flow.c
> +++ b/app/test-pmd/cmdline_flow.c
> @@ -148,6 +148,9 @@ enum index {
>  	ITEM_MPLS_LABEL,
>  	ITEM_GRE,
>  	ITEM_GRE_PROTO,
> +	ITEM_GRE_CRKSV,
> +	ITEM_GRE_KEY,
> +	ITEM_GRE_KEY_KEY,
>  	ITEM_FUZZY,
>  	ITEM_FUZZY_THRESH,
>  	ITEM_GTP,
> @@ -595,6 +598,7 @@ static const enum index next_item[] = {
>  	ITEM_NVGRE,
>  	ITEM_MPLS,
>  	ITEM_GRE,
> +	ITEM_GRE_KEY,
>  	ITEM_FUZZY,
>  	ITEM_GTP,
>  	ITEM_GTPC,
> @@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
> 
>  static const enum index item_gre[] = {
>  	ITEM_GRE_PROTO,
> +	ITEM_GRE_CRKSV,
> +	ITEM_NEXT,
> +	ZERO,
> +};
> +
> +static const enum index item_gre_key[] = {
> +	ITEM_GRE_KEY_KEY,
>  	ITEM_NEXT,
>  	ZERO,
>  };
> @@ -1898,6 +1909,27 @@ static const struct token token_list[] = {
>  		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
>  					     protocol)),
>  	},
> +	[ITEM_GRE_CRKSV] = {
> +		.name = "crksv",
> +		.help = "GRE's first word (bit0 - bit15)",
> +		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED),
> item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> +					     c_rsvd0_ver)),
> +	},
> +	[ITEM_GRE_KEY] = {
> +		.name = "gre_key",
> +		.help = "match GRE Key",
> +		.priv = PRIV_ITEM(GRE_KEY,
> +				  sizeof(rte_be32_t)),
> +		.next = NEXT(item_gre_key),
> +		.call = parse_vc,
> +	},
> +	[ITEM_GRE_KEY_KEY] = {
> +		.name = "key",
> +		.help = "GRE key",
> +		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED),
> item_param),
> +		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
> +	},
>  	[ITEM_FUZZY] = {
>  		.name = "fuzzy",
>  		.help = "fuzzy pattern match, expect faster than default",
> diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> index cb83a3ce8a..fc3ba8a009 100644
> --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> @@ -3804,6 +3804,10 @@ This section lists supported pattern items and their
> attributes, if any.
> 
>    - ``protocol {unsigned}``: protocol type.
> 
> +- ``gre_key``: match GRE optional key field.
> +
> +  - ``key {unsigned}``: key value.
> +
>  - ``fuzzy``: fuzzy pattern match, expect faster than default.
> 
>    - ``thresh {unsigned}``: accuracy threshold.
> --
> 2.21.0

Re: [dpdk-dev] [PATCH v4 1/4] ethdev: add GRE key field to flow API

[Thomas Monjalon]

02/07/2019 11:45, Xiaoyu Min:
> +	/**
> +	 * Matches a GRE optional key field.
> +	 *
> +	 * The value should a big-endian 32bit integer.
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_KEY,

We probably want to use the same format as in Dekel's patch
for doxygen documentation of the action value:

       /**
        * Increase sequence number in the outermost TCP header.
        *
        * Action configuration specifies the value to increase
        * TCP sequence number as a big-endian 32 bit integer.
        *
        * @p conf type:
        * @code rte_be32_t * @endcode
        *
        * Using this action on non-matching traffic will result in
        * undefined behavior.
        */
       RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ,

Re: [dpdk-dev] [PATCH v4 1/4] ethdev: add GRE key field to flow API

[Adrien Mazarguil]

On Tue, Jul 02, 2019 at 05:45:52PM +0800, Xiaoyu Min wrote:
> Add new rte_flow_item_gre_key in order to match the optional key field.
> 
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>

OK with adding this feature, however I still have a bunch of comments below.

> ---
>  doc/guides/prog_guide/rte_flow.rst | 8 ++++++++
>  lib/librte_ethdev/rte_flow.c       | 1 +
>  lib/librte_ethdev/rte_flow.h       | 7 +++++++
>  3 files changed, 16 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
> index a34d012e55..f4b7baa3c3 100644
> --- a/doc/guides/prog_guide/rte_flow.rst
> +++ b/doc/guides/prog_guide/rte_flow.rst
> @@ -980,6 +980,14 @@ Matches a GRE header.
>  - ``protocol``: protocol type.
>  - Default ``mask`` matches protocol only.
>  
> +Item: ``GRE_KEY``
> +^^^^^^^^^^^^^^^^^
> +
> +Matches a GRE key field.
> +This should be preceded by item ``GRE``

Nit: missing ending "."

> +
> +- Value to be matched is a big-endian 32 bit integer
> +
>  Item: ``FUZZY``
>  ^^^^^^^^^^^^^^^
>  
> diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
> index 3277be1edb..f3e56d0bbe 100644
> --- a/lib/librte_ethdev/rte_flow.c
> +++ b/lib/librte_ethdev/rte_flow.c
> @@ -55,6 +55,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
>  	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
>  	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
>  	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
> +	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),

Hmm? Adding a new item in the middle?

>  	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
>  	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
>  	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
> diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
> index f3a8fb103f..5d3702a44c 100644
> --- a/lib/librte_ethdev/rte_flow.h
> +++ b/lib/librte_ethdev/rte_flow.h
> @@ -289,6 +289,13 @@ enum rte_flow_item_type {
>  	 */
>  	RTE_FLOW_ITEM_TYPE_GRE,
>  
> +	/**
> +	 * Matches a GRE optional key field.
> +	 *
> +	 * The value should a big-endian 32bit integer.
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_KEY,
> +

Same comment. While I understand the intent to group GRE and GRE_KEY, doing
so causes ABI breakage by shifting the value of all subsequent pattern
items (see IPV6 and IPV6_EXT for instance).

We could later decide to sort them while knowingly breaking ABI on purpose,
however right now there's no choice but adding new pattern items and actions
at the end of their respective enums, please do that.

-- 
Adrien Mazarguil
6WIND

Re: [dpdk-dev] [PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Adrien Mazarguil]

On Tue, Jul 02, 2019 at 05:45:55PM +0800, Xiaoyu Min wrote:
> support matching on GRE key and present bits (C,K,S)
> 
> example testpmd command could be:
>   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
>           gre crksv is 0x2000 crksv mask 0xb000 /
> 	  gre_key key is 0x12345678 / end
> 	  actions rss queues 1 0 end / mark id 196 / end
> 
> Which will match GRE packet with k present bit set and key value is
> 0x12345678.
> 
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>

I'm wondering... Is matching the K bit mandatory if one explicitly matches
gre_key already or is this a specific hardware limitation in your case?

Perhaps we could document that the K bit is implicitly matched as "1" in the
default mask when a gre_key pattern item is present. If a user explicitly
spec/mask K as "0" and still provides gre_key, the PMD can safely ignore the
gre_key item.

I'm asking because I think most users won't bother with the K bit when
attempting to match some key and their rules may not behave as expected as a
result.

More below.

> ---
> ** This patch is based on patch [1]
> 
> [1] https://patches.dpdk.org/patch/55773/
> ---
>  app/test-pmd/cmdline_flow.c                 | 32 +++++++++++++++++++++
>  doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +++
>  2 files changed, 36 insertions(+)
> 
> diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
> index 201bd9de56..8504cc8bc1 100644
> --- a/app/test-pmd/cmdline_flow.c
> +++ b/app/test-pmd/cmdline_flow.c
> @@ -148,6 +148,9 @@ enum index {
>  	ITEM_MPLS_LABEL,
>  	ITEM_GRE,
>  	ITEM_GRE_PROTO,
> +	ITEM_GRE_CRKSV,
> +	ITEM_GRE_KEY,
> +	ITEM_GRE_KEY_KEY,

Assuming you move the GRE_KEY definition in rte_flow.h, please keep its
location synchronized in this list as well.

>  	ITEM_FUZZY,
>  	ITEM_FUZZY_THRESH,
>  	ITEM_GTP,
> @@ -595,6 +598,7 @@ static const enum index next_item[] = {
>  	ITEM_NVGRE,
>  	ITEM_MPLS,
>  	ITEM_GRE,
> +	ITEM_GRE_KEY,
>  	ITEM_FUZZY,
>  	ITEM_GTP,
>  	ITEM_GTPC,
> @@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
>  
>  static const enum index item_gre[] = {
>  	ITEM_GRE_PROTO,
> +	ITEM_GRE_CRKSV,

CRKSV may be unnecessary in this patch if the K bit is documented and
implemented as described in my previous comment.

> +	ITEM_NEXT,
> +	ZERO,
> +};
> +
> +static const enum index item_gre_key[] = {
> +	ITEM_GRE_KEY_KEY,
>  	ITEM_NEXT,
>  	ZERO,
>  };
> @@ -1898,6 +1909,27 @@ static const struct token token_list[] = {
>  		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
>  					     protocol)),
>  	},
> +	[ITEM_GRE_CRKSV] = {
> +		.name = "crksv",
> +		.help = "GRE's first word (bit0 - bit15)",
> +		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> +					     c_rsvd0_ver)),
> +	},
> +	[ITEM_GRE_KEY] = {
> +		.name = "gre_key",
> +		.help = "match GRE Key",
> +		.priv = PRIV_ITEM(GRE_KEY,
> +				  sizeof(rte_be32_t)),

Could be a single line.

> +		.next = NEXT(item_gre_key),
> +		.call = parse_vc,
> +	},
> +	[ITEM_GRE_KEY_KEY] = {
> +		.name = "key",
> +		.help = "GRE key",
> +		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
> +		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
> +	},
>  	[ITEM_FUZZY] = {
>  		.name = "fuzzy",
>  		.help = "fuzzy pattern match, expect faster than default",
> diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> index cb83a3ce8a..fc3ba8a009 100644
> --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> @@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
>  
>    - ``protocol {unsigned}``: protocol type.
>  
> +- ``gre_key``: match GRE optional key field.
> +
> +  - ``key {unsigned}``: key value.
> +

You should have named this field "value" then, i.e.:

 - ``value {unsigned}``: key value.

>  - ``fuzzy``: fuzzy pattern match, expect faster than default.
>  
>    - ``thresh {unsigned}``: accuracy threshold.
> -- 
> 2.21.0
> 

-- 
Adrien Mazarguil
6WIND

Re: [dpdk-dev] [PATCH v4 1/4] ethdev: add GRE key field to flow API

[Jack Min]

On Wed, 19-07-03, 16:06, Thomas Monjalon wrote:
> 02/07/2019 11:45, Xiaoyu Min:
> > +	/**
> > +	 * Matches a GRE optional key field.
> > +	 *
> > +	 * The value should a big-endian 32bit integer.
> > +	 */
> > +	RTE_FLOW_ITEM_TYPE_GRE_KEY,
> 
> We probably want to use the same format as in Dekel's patch
> for doxygen documentation of the action value:
> 

OK, I'll update it accordingly.
Thanks ~

>        /**
>         * Increase sequence number in the outermost TCP header.
>         *
>         * Action configuration specifies the value to increase
>         * TCP sequence number as a big-endian 32 bit integer.
>         *
>         * @p conf type:
>         * @code rte_be32_t * @endcode
>         *
>         * Using this action on non-matching traffic will result in
>         * undefined behavior.
>         */
>        RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ,
> 
> 
> 

Re: [dpdk-dev] [PATCH v4 1/4] ethdev: add GRE key field to flow API

[Jack Min]

On Wed, 19-07-03, 17:25, Adrien Mazarguil wrote:
> On Tue, Jul 02, 2019 at 05:45:52PM +0800, Xiaoyu Min wrote:
> > Add new rte_flow_item_gre_key in order to match the optional key field.
> > 
> > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> 
> OK with adding this feature, however I still have a bunch of comments below.
> 
> > ---
> >  doc/guides/prog_guide/rte_flow.rst | 8 ++++++++
> >  lib/librte_ethdev/rte_flow.c       | 1 +
> >  lib/librte_ethdev/rte_flow.h       | 7 +++++++
> >  3 files changed, 16 insertions(+)
> > 
> > diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
> > index a34d012e55..f4b7baa3c3 100644
> > --- a/doc/guides/prog_guide/rte_flow.rst
> > +++ b/doc/guides/prog_guide/rte_flow.rst
> > @@ -980,6 +980,14 @@ Matches a GRE header.
> >  - ``protocol``: protocol type.
> >  - Default ``mask`` matches protocol only.
> >  
> > +Item: ``GRE_KEY``
> > +^^^^^^^^^^^^^^^^^
> > +
> > +Matches a GRE key field.
> > +This should be preceded by item ``GRE``
> 
> Nit: missing ending "."
> 

Ok, I'll add it.

> > +
> > +- Value to be matched is a big-endian 32 bit integer
> > +
> >  Item: ``FUZZY``
> >  ^^^^^^^^^^^^^^^
> >  
> > diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
> > index 3277be1edb..f3e56d0bbe 100644
> > --- a/lib/librte_ethdev/rte_flow.c
> > +++ b/lib/librte_ethdev/rte_flow.c
> > @@ -55,6 +55,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
> >  	MK_FLOW_ITEM(NVGRE, sizeof(struct rte_flow_item_nvgre)),
> >  	MK_FLOW_ITEM(MPLS, sizeof(struct rte_flow_item_mpls)),
> >  	MK_FLOW_ITEM(GRE, sizeof(struct rte_flow_item_gre)),
> > +	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> 
> Hmm? Adding a new item in the middle?
> 

I'll add it at the end.

> >  	MK_FLOW_ITEM(FUZZY, sizeof(struct rte_flow_item_fuzzy)),
> >  	MK_FLOW_ITEM(GTP, sizeof(struct rte_flow_item_gtp)),
> >  	MK_FLOW_ITEM(GTPC, sizeof(struct rte_flow_item_gtp)),
> > diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
> > index f3a8fb103f..5d3702a44c 100644
> > --- a/lib/librte_ethdev/rte_flow.h
> > +++ b/lib/librte_ethdev/rte_flow.h
> > @@ -289,6 +289,13 @@ enum rte_flow_item_type {
> >  	 */
> >  	RTE_FLOW_ITEM_TYPE_GRE,
> >  
> > +	/**
> > +	 * Matches a GRE optional key field.
> > +	 *
> > +	 * The value should a big-endian 32bit integer.
> > +	 */
> > +	RTE_FLOW_ITEM_TYPE_GRE_KEY,
> > +
> 
> Same comment. While I understand the intent to group GRE and GRE_KEY, doing
> so causes ABI breakage by shifting the value of all subsequent pattern
> items (see IPV6 and IPV6_EXT for instance).
> 

Oh, I was't aware of this. Thank you for explaination.

> We could later decide to sort them while knowingly breaking ABI on purpose,
> however right now there's no choice but adding new pattern items and actions
> at the end of their respective enums, please do that.
> 

Yes, I'll do this.

> -- 
> Adrien Mazarguil
> 6WIND

Re: [dpdk-dev] [PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Jack Min]

On Wed, 19-07-03, 17:25, Adrien Mazarguil wrote:
> On Tue, Jul 02, 2019 at 05:45:55PM +0800, Xiaoyu Min wrote:
> > support matching on GRE key and present bits (C,K,S)
> > 
> > example testpmd command could be:
> >   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> >           gre crksv is 0x2000 crksv mask 0xb000 /
> > 	  gre_key key is 0x12345678 / end
> > 	  actions rss queues 1 0 end / mark id 196 / end
> > 
> > Which will match GRE packet with k present bit set and key value is
> > 0x12345678.
> > 
> > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> 
> I'm wondering... Is matching the K bit mandatory if one explicitly matches
> gre_key already or is this a specific hardware limitation in your case?
> 

If there is gre_key item MLX5 PMD will force set HW matching on K bit,
From HW perspective it is mandatory. But, from testpmd (user)
perspective, I agree with you, user needn't set matching on K bit if
they already explicitly set gre_key item.

> Perhaps we could document that the K bit is implicitly matched as "1" in the
> default mask when a gre_key pattern item is present. If a user explicitly

Yes, I should document this.
So it should be documented in __testpmd_funcs.rst__ ?

> spec/mask K as "0" and still provides gre_key, the PMD can safely ignore the
> gre_key item.
> 

Well, actullay, when a user explicitly set spec/mask K as "0" and still
provide gre_key item, MLX5 PMD will implicitly set match on K bit as
"1", just ingore the K bit set by user.
The reason is wanna keep code simple, needn't to get
information from other item (gre) inside gre_key item, or vice verse.

And, I think, when a user provides a gre_key item, most probably, they do
really wanna match on gre_key. What do you think?

> I'm asking because I think most users won't bother with the K bit when
> attempting to match some key and their rules may not behave as expected as a
> result.
> 

I see.

> More below.
> 
> > ---
> > ** This patch is based on patch [1]
> > 
> > [1] https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatches.dpdk.org%2Fpatch%2F55773%2F&amp;data=02%7C01%7Cjackmin%40mellanox.com%7C590e61b809bb42869cf508d6ffcaa82c%7Ca652971c7d2e4d9ba6a4d149256f461b%7C0%7C0%7C636977643198683579&amp;sdata=LhTsrHRfX3LHhiHRBtz4WKUUklWupJueSBgWmiHPECM%3D&amp;reserved=0
> > ---
> >  app/test-pmd/cmdline_flow.c                 | 32 +++++++++++++++++++++
> >  doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +++
> >  2 files changed, 36 insertions(+)
> > 
> > diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
> > index 201bd9de56..8504cc8bc1 100644
> > --- a/app/test-pmd/cmdline_flow.c
> > +++ b/app/test-pmd/cmdline_flow.c
> > @@ -148,6 +148,9 @@ enum index {
> >  	ITEM_MPLS_LABEL,
> >  	ITEM_GRE,
> >  	ITEM_GRE_PROTO,
> > +	ITEM_GRE_CRKSV,
> > +	ITEM_GRE_KEY,
> > +	ITEM_GRE_KEY_KEY,
> 
> Assuming you move the GRE_KEY definition in rte_flow.h, please keep its
> location synchronized in this list as well.
> 

I'll do this.

> >  	ITEM_FUZZY,
> >  	ITEM_FUZZY_THRESH,
> >  	ITEM_GTP,
> > @@ -595,6 +598,7 @@ static const enum index next_item[] = {
> >  	ITEM_NVGRE,
> >  	ITEM_MPLS,
> >  	ITEM_GRE,
> > +	ITEM_GRE_KEY,
> >  	ITEM_FUZZY,
> >  	ITEM_GTP,
> >  	ITEM_GTPC,
> > @@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
> >  
> >  static const enum index item_gre[] = {
> >  	ITEM_GRE_PROTO,
> > +	ITEM_GRE_CRKSV,
> 
> CRKSV may be unnecessary in this patch if the K bit is documented and
> implemented as described in my previous comment.
> 

Well, actully, we also wanna testpmd can match on C,S bits with K bit
together so we can test on gre packet with key only or csum + key, or
csum + key + sequence.

> > +	ITEM_NEXT,
> > +	ZERO,
> > +};
> > +
> > +static const enum index item_gre_key[] = {
> > +	ITEM_GRE_KEY_KEY,
> >  	ITEM_NEXT,
> >  	ZERO,
> >  };
> > @@ -1898,6 +1909,27 @@ static const struct token token_list[] = {
> >  		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> >  					     protocol)),
> >  	},
> > +	[ITEM_GRE_CRKSV] = {
> > +		.name = "crksv",
> > +		.help = "GRE's first word (bit0 - bit15)",
> > +		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
> > +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> > +					     c_rsvd0_ver)),
> > +	},
> > +	[ITEM_GRE_KEY] = {
> > +		.name = "gre_key",
> > +		.help = "match GRE Key",
> > +		.priv = PRIV_ITEM(GRE_KEY,
> > +				  sizeof(rte_be32_t)),
> 
> Could be a single line.
> 

Yes, I'll update it.

> > +		.next = NEXT(item_gre_key),
> > +		.call = parse_vc,
> > +	},
> > +	[ITEM_GRE_KEY_KEY] = {
> > +		.name = "key",
> > +		.help = "GRE key",
> > +		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
> > +		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
> > +	},
> >  	[ITEM_FUZZY] = {
> >  		.name = "fuzzy",
> >  		.help = "fuzzy pattern match, expect faster than default",
> > diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> > index cb83a3ce8a..fc3ba8a009 100644
> > --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> > +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> > @@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
> >  
> >    - ``protocol {unsigned}``: protocol type.
> >  
> > +- ``gre_key``: match GRE optional key field.
> > +
> > +  - ``key {unsigned}``: key value.
> > +
> 
> You should have named this field "value" then, i.e.:
> 
>  - ``value {unsigned}``: key value.
> 

OK, I'll update it.

> >  - ``fuzzy``: fuzzy pattern match, expect faster than default.
> >  
> >    - ``thresh {unsigned}``: accuracy threshold.
> > -- 
> > 2.21.0
> > 
> 
> -- 
> Adrien Mazarguil
> 6WIND

Re: [dpdk-dev] [PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Adrien Mazarguil]

On Thu, Jul 04, 2019 at 05:52:43AM +0000, Jack Min wrote:
> On Wed, 19-07-03, 17:25, Adrien Mazarguil wrote:
> > On Tue, Jul 02, 2019 at 05:45:55PM +0800, Xiaoyu Min wrote:
> > > support matching on GRE key and present bits (C,K,S)
> > > 
> > > example testpmd command could be:
> > >   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> > >           gre crksv is 0x2000 crksv mask 0xb000 /
> > > 	  gre_key key is 0x12345678 / end
> > > 	  actions rss queues 1 0 end / mark id 196 / end
> > > 
> > > Which will match GRE packet with k present bit set and key value is
> > > 0x12345678.
> > > 
> > > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> > 
> > I'm wondering... Is matching the K bit mandatory if one explicitly matches
> > gre_key already or is this a specific hardware limitation in your case?
> > 
> 
> If there is gre_key item MLX5 PMD will force set HW matching on K bit,
> From HW perspective it is mandatory. But, from testpmd (user)
> perspective, I agree with you, user needn't set matching on K bit if
> they already explicitly set gre_key item.

OK, makes sense.

> > Perhaps we could document that the K bit is implicitly matched as "1" in the
> > default mask when a gre_key pattern item is present. If a user explicitly
> 
> Yes, I should document this.
> So it should be documented in __testpmd_funcs.rst__ ?

No it would be a change in the GRE_KEY item itself at the rte_flow API
level (rte_flow.h) & documentation (rte_flow.rst). The flow rules created by
testpmd must be an exact translation of user input, as a debugging tool it
can't request something that wasn't explicitly written.

> > spec/mask K as "0" and still provides gre_key, the PMD can safely ignore the
> > gre_key item.
> > 
> 
> Well, actullay, when a user explicitly set spec/mask K as "0" and still
> provide gre_key item, MLX5 PMD will implicitly set match on K bit as
> "1", just ingore the K bit set by user.

Not good then. You should spit an error out if it's an impossible
combination. You can't match both K == 0 *and* a GRE key, unless perhaps if
key mask is also 0, e.g.:

 gre crksv is 0x0000 crksv mask 0xb000 /
 gre_key value spec 0x00000000 value mask 0x00000000

This is merely an overly complex way for telling the PMD that one wants to
match packets without GRE keys that you could technically support.

> The reason is wanna keep code simple, needn't to get
> information from other item (gre) inside gre_key item, or vice verse.

PMDs typically maintain context as they process the pattern. The GRE pattern
item is guaranteed to come before GRE_KEY, so you already know at this point
whether users want to match K at all, and if so, what value they want it to
have.

> And, I think, when a user provides a gre_key item, most probably, they do
> really wanna match on gre_key. What do you think?

Depends. They may want to match all GRE traffic with a key, doesn't matter
which, in order to process it through a different path. To do so they could
either:

1. Use the GRE item only to match K bit == 1.

2. Use the GRE_KEY item to match a nonspecific key value (mask == 0).

3. Use a combination of both.

I think you can easily support all three of them with mlx5 if you support
partial masks on GRE keys (I haven't checked), even if you're unable to
specifically match the K bit itself.

[...]
> > > @@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
> > >  
> > >  static const enum index item_gre[] = {
> > >  	ITEM_GRE_PROTO,
> > > +	ITEM_GRE_CRKSV,
> > 
> > CRKSV may be unnecessary in this patch if the K bit is documented and
> > implemented as described in my previous comment.
> > 
> 
> Well, actully, we also wanna testpmd can match on C,S bits with K bit
> together so we can test on gre packet with key only or csum + key, or
> csum + key + sequence.

OK no problem. Perhaps you could make this easier by allowing users to match
individual bits, let me explain:

The flow command in testpmd is a direct interface to manipulate rte_flow's
structures. The "crksv" field doesn't exist in rte_flow_item_gre, its name
is "c_rsvd0_ver". Testpmd must use the same in its command and internal
code.

However since bit-masks are usually a pain to mentally work out, you can
provide extras for convenience. The "types" field of the RSS action
(ACTION_RSS_TYPES) is an extreme example of this approach.

So I suggest adding ITEM_GRE_C_RSVD0_VER taking a 16-bit value like CRKSV,
and complete it with ITEM_GRE_C_BIT, ITEM_GRE_S_BIT and ITEM_GRE_K_BIT
addressing the individual bits you would like to expose for convenience.

[...]
> > You should have named this field "value" then, i.e.:
> > 
> >  - ``value {unsigned}``: key value.
> > 
> 
> OK, I'll update it.

Please remember to update it in rte_flow.h and documentation as well,
thanks.

-- 
Adrien Mazarguil
6WIND

Re: [dpdk-dev] [PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Jack Min]

On Thu, 19-07-04, 11:52, Adrien Mazarguil wrote:
> On Thu, Jul 04, 2019 at 05:52:43AM +0000, Jack Min wrote:
> > On Wed, 19-07-03, 17:25, Adrien Mazarguil wrote:
> > > On Tue, Jul 02, 2019 at 05:45:55PM +0800, Xiaoyu Min wrote:
> > > > support matching on GRE key and present bits (C,K,S)
> > > > 
> > > > example testpmd command could be:
> > > >   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> > > >           gre crksv is 0x2000 crksv mask 0xb000 /
> > > > 	  gre_key key is 0x12345678 / end
> > > > 	  actions rss queues 1 0 end / mark id 196 / end
> > > > 
> > > > Which will match GRE packet with k present bit set and key value is
> > > > 0x12345678.
> > > > 
> > > > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> > > 
> > > I'm wondering... Is matching the K bit mandatory if one explicitly matches
> > > gre_key already or is this a specific hardware limitation in your case?
> > > 
> > 
> > If there is gre_key item MLX5 PMD will force set HW matching on K bit,
> > From HW perspective it is mandatory. But, from testpmd (user)
> > perspective, I agree with you, user needn't set matching on K bit if
> > they already explicitly set gre_key item.
> 
> OK, makes sense.
> 
> > > Perhaps we could document that the K bit is implicitly matched as "1" in the
> > > default mask when a gre_key pattern item is present. If a user explicitly
> > 
> > Yes, I should document this.
> > So it should be documented in __testpmd_funcs.rst__ ?
> 
> No it would be a change in the GRE_KEY item itself at the rte_flow API
> level (rte_flow.h) & documentation (rte_flow.rst). The flow rules created by
> testpmd must be an exact translation of user input, as a debugging tool it
> can't request something that wasn't explicitly written.
> 

will update rte_flow.h & rte_flow.rst

> > > spec/mask K as "0" and still provides gre_key, the PMD can safely ignore the
> > > gre_key item.
> > > 
> > 
> > Well, actullay, when a user explicitly set spec/mask K as "0" and still
> > provide gre_key item, MLX5 PMD will implicitly set match on K bit as
> > "1", just ingore the K bit set by user.
> 
> Not good then. You should spit an error out if it's an impossible
> combination. You can't match both K == 0 *and* a GRE key, unless perhaps if
> key mask is also 0, e.g.:
> 
>  gre crksv is 0x0000 crksv mask 0xb000 /
>  gre_key value spec 0x00000000 value mask 0x00000000
> 

Never thought man will wirte thing like this, they don't wanna match
gre_key why put the item there ?
But, since you have raised this example, I'll update PMD part to handle this.

> This is merely an overly complex way for telling the PMD that one wants to
> match packets without GRE keys that you could technically support.
> 
> > The reason is wanna keep code simple, needn't to get
> > information from other item (gre) inside gre_key item, or vice verse.
> 
> PMDs typically maintain context as they process the pattern. The GRE pattern
> item is guaranteed to come before GRE_KEY, so you already know at this point
> whether users want to match K at all, and if so, what value they want it to
> have.
> 

Yes, PMD can know. Just need to add some code.

> > And, I think, when a user provides a gre_key item, most probably, they do
> > really wanna match on gre_key. What do you think?
> 
> Depends. They may want to match all GRE traffic with a key, doesn't matter
> which, in order to process it through a different path. To do so they could
> either:
> 
> 1. Use the GRE item only to match K bit == 1.
> 
> 2. Use the GRE_KEY item to match a nonspecific key value (mask == 0).
> 
> 3. Use a combination of both.
> 
> I think you can easily support all three of them with mlx5 if you support
> partial masks on GRE keys (I haven't checked), even if you're unable to
> specifically match the K bit itself.
> 

Already support this.

> [...]
> > > > @@ -755,6 +759,13 @@ static const enum index item_mpls[] = {
> > > >  
> > > >  static const enum index item_gre[] = {
> > > >  	ITEM_GRE_PROTO,
> > > > +	ITEM_GRE_CRKSV,
> > > 
> > > CRKSV may be unnecessary in this patch if the K bit is documented and
> > > implemented as described in my previous comment.
> > > 
> > 
> > Well, actully, we also wanna testpmd can match on C,S bits with K bit
> > together so we can test on gre packet with key only or csum + key, or
> > csum + key + sequence.
> 
> OK no problem. Perhaps you could make this easier by allowing users to match
> individual bits, let me explain:
> 
> The flow command in testpmd is a direct interface to manipulate rte_flow's
> structures. The "crksv" field doesn't exist in rte_flow_item_gre, its name
> is "c_rsvd0_ver". Testpmd must use the same in its command and internal
> code.
> 
> However since bit-masks are usually a pain to mentally work out, you can
> provide extras for convenience. The "types" field of the RSS action
> (ACTION_RSS_TYPES) is an extreme example of this approach.
> 
> So I suggest adding ITEM_GRE_C_RSVD0_VER taking a 16-bit value like CRKSV,
> and complete it with ITEM_GRE_C_BIT, ITEM_GRE_S_BIT and ITEM_GRE_K_BIT
> addressing the individual bits you would like to expose for convenience.
> 

So something like:
  eth / ipv4 / gre c_rsvd0_ver c_bit is 0 s_bit is 0 k_bit is 1 / ...

Is it right?

> [...]
> > > You should have named this field "value" then, i.e.:
> > > 
> > >  - ``value {unsigned}``: key value.
> > > 
> > 
> > OK, I'll update it.
> 
> Please remember to update it in rte_flow.h and documentation as well,
> thanks.
> 
OK.
> -- 
> Adrien Mazarguil
> 6WIND

Re: [dpdk-dev] [PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Adrien Mazarguil]

On Thu, Jul 04, 2019 at 11:56:35AM +0000, Jack Min wrote:
> On Thu, 19-07-04, 11:52, Adrien Mazarguil wrote:
> > On Thu, Jul 04, 2019 at 05:52:43AM +0000, Jack Min wrote:
> > > On Wed, 19-07-03, 17:25, Adrien Mazarguil wrote:
> > > > On Tue, Jul 02, 2019 at 05:45:55PM +0800, Xiaoyu Min wrote:
> > > > > support matching on GRE key and present bits (C,K,S)
> > > > > 
> > > > > example testpmd command could be:
> > > > >   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> > > > >           gre crksv is 0x2000 crksv mask 0xb000 /
> > > > > 	  gre_key key is 0x12345678 / end
> > > > > 	  actions rss queues 1 0 end / mark id 196 / end
> > > > > 
> > > > > Which will match GRE packet with k present bit set and key value is
> > > > > 0x12345678.
> > > > > 
> > > > > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
[...]
> > > Well, actullay, when a user explicitly set spec/mask K as "0" and still
> > > provide gre_key item, MLX5 PMD will implicitly set match on K bit as
> > > "1", just ingore the K bit set by user.
> > 
> > Not good then. You should spit an error out if it's an impossible
> > combination. You can't match both K == 0 *and* a GRE key, unless perhaps if
> > key mask is also 0, e.g.:
> > 
> >  gre crksv is 0x0000 crksv mask 0xb000 /
> >  gre_key value spec 0x00000000 value mask 0x00000000
> > 
> 
> Never thought man will wirte thing like this, they don't wanna match
> gre_key why put the item there ?
> But, since you have raised this example, I'll update PMD part to handle this.

It's just an example of valid yet convoluted command mind you, I'm not
forcing you to support it, however if you don't, you must raise an error,
you can't just ignore the K bit if user provides GRE_KEY.

[...]
> > Depends. They may want to match all GRE traffic with a key, doesn't matter
> > which, in order to process it through a different path. To do so they could
> > either:
> > 
> > 1. Use the GRE item only to match K bit == 1.
> > 
> > 2. Use the GRE_KEY item to match a nonspecific key value (mask == 0).
> > 
> > 3. Use a combination of both.
> > 
> > I think you can easily support all three of them with mlx5 if you support
> > partial masks on GRE keys (I haven't checked), even if you're unable to
> > specifically match the K bit itself.
> > 
> 
> Already support this.

OK, nice.

[...]
> > > Well, actully, we also wanna testpmd can match on C,S bits with K bit
> > > together so we can test on gre packet with key only or csum + key, or
> > > csum + key + sequence.
> > 
> > OK no problem. Perhaps you could make this easier by allowing users to match
> > individual bits, let me explain:
> > 
> > The flow command in testpmd is a direct interface to manipulate rte_flow's
> > structures. The "crksv" field doesn't exist in rte_flow_item_gre, its name
> > is "c_rsvd0_ver". Testpmd must use the same in its command and internal
> > code.
> > 
> > However since bit-masks are usually a pain to mentally work out, you can
> > provide extras for convenience. The "types" field of the RSS action
> > (ACTION_RSS_TYPES) is an extreme example of this approach.
> > 
> > So I suggest adding ITEM_GRE_C_RSVD0_VER taking a 16-bit value like CRKSV,
> > and complete it with ITEM_GRE_C_BIT, ITEM_GRE_S_BIT and ITEM_GRE_K_BIT
> > addressing the individual bits you would like to expose for convenience.
> > 
> 
> So something like:
>   eth / ipv4 / gre c_rsvd0_ver c_bit is 0 s_bit is 0 k_bit is 1 / ...
> 
> Is it right?

Looks like "c_rsvd0_ver" is incomplete, I assume you meant:

 eth / ipv4 / gre c_rsvd0_ver is 0 c_bit is 0 s_bit is 0 k_bit is 1 / ...

And yes it's valid. Of course since nothing is matched by default, users
will typically not provide c_rsvd0_ver at all and focus on the relevant bits
for their use case: 

 eth / ipv4 / gre k_bit is 1 / ...

Another suggestion, use BOOLEAN instead of INTEGER type for C/K/S to support
other binary expressions:

 eth / ipv4 / gre k_bit is on / ...

-- 
Adrien Mazarguil
6WIND

Re: [dpdk-dev] [PATCH v4 4/4] app/testpmd: match GRE's key and present bits

[Jack Min]

On Thu, 19-07-04, 14:13, Adrien Mazarguil wrote:
> On Thu, Jul 04, 2019 at 11:56:35AM +0000, Jack Min wrote:
> > On Thu, 19-07-04, 11:52, Adrien Mazarguil wrote:
> > > On Thu, Jul 04, 2019 at 05:52:43AM +0000, Jack Min wrote:
> > > > On Wed, 19-07-03, 17:25, Adrien Mazarguil wrote:
> > > > > On Tue, Jul 02, 2019 at 05:45:55PM +0800, Xiaoyu Min wrote:
> > > > > > support matching on GRE key and present bits (C,K,S)
> > > > > > 
> > > > > > example testpmd command could be:
> > > > > >   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> > > > > >           gre crksv is 0x2000 crksv mask 0xb000 /
> > > > > > 	  gre_key key is 0x12345678 / end
> > > > > > 	  actions rss queues 1 0 end / mark id 196 / end
> > > > > > 
> > > > > > Which will match GRE packet with k present bit set and key value is
> > > > > > 0x12345678.
> > > > > > 
> > > > > > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> [...]
> > > > Well, actullay, when a user explicitly set spec/mask K as "0" and still
> > > > provide gre_key item, MLX5 PMD will implicitly set match on K bit as
> > > > "1", just ingore the K bit set by user.
> > > 
> > > Not good then. You should spit an error out if it's an impossible
> > > combination. You can't match both K == 0 *and* a GRE key, unless perhaps if
> > > key mask is also 0, e.g.:
> > > 
> > >  gre crksv is 0x0000 crksv mask 0xb000 /
> > >  gre_key value spec 0x00000000 value mask 0x00000000
> > > 
> > 
> > Never thought man will wirte thing like this, they don't wanna match
> > gre_key why put the item there ?
> > But, since you have raised this example, I'll update PMD part to handle this.
> 
> It's just an example of valid yet convoluted command mind you, I'm not
> forcing you to support it, however if you don't, you must raise an error,
> you can't just ignore the K bit if user provides GRE_KEY.
> 
OK, make sense.
> [...]
> > > Depends. They may want to match all GRE traffic with a key, doesn't matter
> > > which, in order to process it through a different path. To do so they could
> > > either:
> > > 
> > > 1. Use the GRE item only to match K bit == 1.
> > > 
> > > 2. Use the GRE_KEY item to match a nonspecific key value (mask == 0).
> > > 
> > > 3. Use a combination of both.
> > > 
> > > I think you can easily support all three of them with mlx5 if you support
> > > partial masks on GRE keys (I haven't checked), even if you're unable to
> > > specifically match the K bit itself.
> > > 
> > 
> > Already support this.
> 
> OK, nice.
> 
> [...]
> > > > Well, actully, we also wanna testpmd can match on C,S bits with K bit
> > > > together so we can test on gre packet with key only or csum + key, or
> > > > csum + key + sequence.
> > > 
> > > OK no problem. Perhaps you could make this easier by allowing users to match
> > > individual bits, let me explain:
> > > 
> > > The flow command in testpmd is a direct interface to manipulate rte_flow's
> > > structures. The "crksv" field doesn't exist in rte_flow_item_gre, its name
> > > is "c_rsvd0_ver". Testpmd must use the same in its command and internal
> > > code.
> > > 
> > > However since bit-masks are usually a pain to mentally work out, you can
> > > provide extras for convenience. The "types" field of the RSS action
> > > (ACTION_RSS_TYPES) is an extreme example of this approach.
> > > 
> > > So I suggest adding ITEM_GRE_C_RSVD0_VER taking a 16-bit value like CRKSV,
> > > and complete it with ITEM_GRE_C_BIT, ITEM_GRE_S_BIT and ITEM_GRE_K_BIT
> > > addressing the individual bits you would like to expose for convenience.
> > > 
> > 
> > So something like:
> >   eth / ipv4 / gre c_rsvd0_ver c_bit is 0 s_bit is 0 k_bit is 1 / ...
> > 
> > Is it right?
> 
> Looks like "c_rsvd0_ver" is incomplete, I assume you meant:
> 
>  eth / ipv4 / gre c_rsvd0_ver is 0 c_bit is 0 s_bit is 0 k_bit is 1 / ...
> 
> And yes it's valid. Of course since nothing is matched by default, users
> will typically not provide c_rsvd0_ver at all and focus on the relevant bits
> for their use case: 
> 
>  eth / ipv4 / gre k_bit is 1 / ...
> 
> Another suggestion, use BOOLEAN instead of INTEGER type for C/K/S to support
> other binary expressions:
> 
>  eth / ipv4 / gre k_bit is on / ...
>
OK~ 
> -- 
> Adrien Mazarguil
> 6WIND

[dpdk-dev] [PATCH v5 0/4] match on GRE's key

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

[1] https://patches.dpdk.org/patch/53432/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention
v3:
  * updated release note
  * fixed one bug
v4:
  * resend patchs in thread mode
v5:
  * report error when K is off but gre_key item present
  * removed ITEM_CRKSV, added c_bit, k_bit, s_bit in testpmd
  * document updated
--
Xiaoyu Min (4):
  ethdev: add GRE key field to flow API
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits
  app/testpmd: match GRE's key and present bits

 app/test-pmd/cmdline_flow.c                 | 61 +++++++++++++++
 doc/guides/prog_guide/rte_flow.rst          |  9 +++
 doc/guides/rel_notes/release_19_08.rst      |  5 ++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +
 drivers/net/mlx5/mlx5_flow.c                | 64 +++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h                |  6 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 84 +++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h                 |  6 +-
 lib/librte_ethdev/rte_flow.c                |  1 +
 lib/librte_ethdev/rte_flow.h                | 13 ++++
 10 files changed, 251 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v5 1/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

Add new rte_flow_item_gre_key in order to match the optional key field.

Acked-by: Ori Kam <orika@mellanox.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/prog_guide/rte_flow.rst |  9 +++++++++
 lib/librte_ethdev/rte_flow.c       |  1 +
 lib/librte_ethdev/rte_flow.h       | 13 +++++++++++++
 3 files changed, 23 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index a34d012e55..8072fc1664 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -980,6 +980,15 @@ Matches a GRE header.
 - ``protocol``: protocol type.
 - Default ``mask`` matches protocol only.
 
+Item: ``GRE_KEY``
+^^^^^^^^^^^^^^^^^
+
+Matches a GRE key field.
+This should be preceded by item ``GRE``.
+
+- Value to be matched is a big-endian 32 bit integer.
+- When this item present it implicitly match K bit in default mask as "1"
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
index 5c4952242f..f617e0304f 100644
--- a/lib/librte_ethdev/rte_flow.c
+++ b/lib/librte_ethdev/rte_flow.c
@@ -74,6 +74,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 		     sizeof(struct rte_flow_item_icmp6_nd_opt_tla_eth)),
 	MK_FLOW_ITEM(MARK, sizeof(struct rte_flow_item_mark)),
 	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
+	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
 };
 
 /** Generate flow_action[] entry. */
diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
index f3a8fb103f..bdb8edee42 100644
--- a/lib/librte_ethdev/rte_flow.h
+++ b/lib/librte_ethdev/rte_flow.h
@@ -421,6 +421,19 @@ enum rte_flow_item_type {
 	 * See struct rte_flow_item_meta.
 	 */
 	RTE_FLOW_ITEM_TYPE_META,
+
+	/**
+	 * Matches a GRE optional key field.
+	 *
+	 * The value should a big-endian 32bit integer.
+	 *
+	 * When this item present the K bit is implicitly matched as "1"
+	 * in the default mask.
+	 *
+	 * @p spec/mask type:
+	 * @code rte_be32_t * @endcode
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_KEY,
 };
 
 /**
-- 
2.21.0

[dpdk-dev] [PATCH v5 2/4] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index dc48252791..0c6bf4114b 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1610,6 +1610,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1617,6 +1618,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v5 3/4] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/rel_notes/release_19_08.rst |  5 ++
 drivers/net/mlx5/mlx5_flow.c           | 62 ++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  6 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 161 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 223479c6d4..1ba551d2a7 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -128,6 +128,11 @@ New Features
   Added telemetry mode to l3fwd-power application to report
   application level busyness, empty and full polls of rte_eth_rx_burst().
 
+* **Updated Mellanox mlx5 driver.**
+
+   Updated Mellanox mlx5 driver with new features and improvements, including:
+
+   * Added support for matching on GRE's key and C,K,S present bits.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 0c6bf4114b..ebb8b28a92 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1562,6 +1562,62 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error)
+{
+	const rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+	if (gre_spec && !(gre_spec->c_rsvd0_ver &
+			  gre_mask->c_rsvd0_ver &
+			  RTE_BE16(0x2000)))
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Key bit must be on");
+
+	if (!mask)
+		mask = &gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1587,6 +1643,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(UINT16_MAX),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1606,7 +1666,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 65cfdbda9f..4439f30d8e 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -50,6 +50,8 @@
 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
 
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -462,6 +464,10 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    const struct rte_flow_item *gre_item,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 933ad0b819..16600c8f8e 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2066,6 +2066,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 	uint64_t last_item = 0;
 	uint8_t next_protocol = 0xff;
 	int actions_n = 0;
+	const struct rte_flow_item *gre_item = NULL;
 	struct rte_flow_item_tcp nic_tcp_mask = {
 		.hdr = {
 			.tcp_flags = 0xFF,
@@ -2175,8 +2176,16 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 							  next_protocol, error);
 			if (ret < 0)
 				return ret;
+			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, gre_item, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -2922,6 +2931,45 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	/* GRE K bit must be on and should already be validated */
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -2945,6 +2993,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -2965,6 +3027,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -3995,6 +4074,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1a199580c5..4022770b7b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -416,7 +416,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

[dpdk-dev] [PATCH v5 4/4] app/testpmd: match GRE's key and present bits

[Xiaoyu Min]

support matching on GRE key and present bits (C,K,S)

example testpmd command could be:
  testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
	  gre / gre_key value is 0x12345678 / end
	  actions rss queues 1 0 end / mark id 196 / end

Which will match GRE packet with k present bit set and key value is
0x12345678.

Acked-by: Ori Kam <orika@mellanox.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 app/test-pmd/cmdline_flow.c                 | 61 +++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 ++
 2 files changed, 65 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 201bd9de56..8a579b645e 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -148,6 +148,10 @@ enum index {
 	ITEM_MPLS_LABEL,
 	ITEM_GRE,
 	ITEM_GRE_PROTO,
+	ITEM_GRE_C_RSVD0_VER,
+	ITEM_GRE_C_BIT,
+	ITEM_GRE_K_BIT,
+	ITEM_GRE_S_BIT,
 	ITEM_FUZZY,
 	ITEM_FUZZY_THRESH,
 	ITEM_GTP,
@@ -181,6 +185,8 @@ enum index {
 	ITEM_ICMP6_ND_OPT_TLA_ETH_TLA,
 	ITEM_META,
 	ITEM_META_DATA,
+	ITEM_GRE_KEY,
+	ITEM_GRE_KEY_VALUE,
 
 	/* Validate/create actions. */
 	ACTIONS,
@@ -610,6 +616,7 @@ static const enum index next_item[] = {
 	ITEM_ICMP6_ND_OPT_SLA_ETH,
 	ITEM_ICMP6_ND_OPT_TLA_ETH,
 	ITEM_META,
+	ITEM_GRE_KEY,
 	ZERO,
 };
 
@@ -755,6 +762,16 @@ static const enum index item_mpls[] = {
 
 static const enum index item_gre[] = {
 	ITEM_GRE_PROTO,
+	ITEM_GRE_C_RSVD0_VER,
+	ITEM_GRE_C_BIT,
+	ITEM_GRE_K_BIT,
+	ITEM_GRE_S_BIT,
+	ITEM_NEXT,
+	ZERO,
+};
+
+static const enum index item_gre_key[] = {
+	ITEM_GRE_KEY_VALUE,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -1898,6 +1915,50 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
 					     protocol)),
 	},
+	[ITEM_GRE_C_RSVD0_VER] = {
+		.name = "c_rsvd0_ver",
+		.help = "GRE's first word (bit0 - bit15)",
+		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
+					     c_rsvd0_ver)),
+	},
+	[ITEM_GRE_C_BIT] = {
+		.name = "c_bit",
+		.help = "GRE's C present bit",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x80\x00\x00\x00")),
+	},
+	[ITEM_GRE_S_BIT] = {
+		.name = "s_bit",
+		.help = "GRE's S present bit",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x10\x00\x00\x00")),
+	},
+	[ITEM_GRE_K_BIT] = {
+		.name = "k_bit",
+		.help = "GRE's K present bit",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x20\x00\x00\x00")),
+	},
+	[ITEM_GRE_KEY] = {
+		.name = "gre_key",
+		.help = "match GRE Key",
+		.priv = PRIV_ITEM(GRE_KEY, sizeof(rte_be32_t)),
+		.next = NEXT(item_gre_key),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_KEY_VALUE] = {
+		.name = "value",
+		.help = "GRE key value",
+		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
+	},
 	[ITEM_FUZZY] = {
 		.name = "fuzzy",
 		.help = "fuzzy pattern match, expect faster than default",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index cb83a3ce8a..9ef1796ee1 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``protocol {unsigned}``: protocol type.
 
+- ``gre_key``: match GRE optional key field.
+
+  - ``value {unsigned}``: key value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
2.21.0

[dpdk-dev] [PATCH v6 0/4] match on GRE's key

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

[1] https://patches.dpdk.org/patch/53432/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention
v3:
  * updated release note
  * fixed one bug
v4:
  * resend patchs in thread mode
v5:
  * report error when K is off but gre_key item present
  * removed ITEM_CRKSV, added c_bit, k_bit, s_bit in testpmd
  * document updated
v6:
  * one fix in pmd
--
Xiaoyu Min (4):
  ethdev: add GRE key field to flow API
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits
  app/testpmd: match GRE's key and present bits

 app/test-pmd/cmdline_flow.c                 | 61 +++++++++++++++
 doc/guides/prog_guide/rte_flow.rst          |  9 +++
 doc/guides/rel_notes/release_19_08.rst      |  5 ++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +
 drivers/net/mlx5/mlx5_flow.c                | 63 +++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h                |  6 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 84 +++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h                 |  6 +-
 lib/librte_ethdev/rte_flow.c                |  1 +
 lib/librte_ethdev/rte_flow.h                | 13 ++++
 10 files changed, 250 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v6 1/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

Add new rte_flow_item_gre_key in order to match the optional key field.

Acked-by: Ori Kam <orika@mellanox.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/prog_guide/rte_flow.rst |  9 +++++++++
 lib/librte_ethdev/rte_flow.c       |  1 +
 lib/librte_ethdev/rte_flow.h       | 13 +++++++++++++
 3 files changed, 23 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index a34d012e55..8072fc1664 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -980,6 +980,15 @@ Matches a GRE header.
 - ``protocol``: protocol type.
 - Default ``mask`` matches protocol only.
 
+Item: ``GRE_KEY``
+^^^^^^^^^^^^^^^^^
+
+Matches a GRE key field.
+This should be preceded by item ``GRE``.
+
+- Value to be matched is a big-endian 32 bit integer.
+- When this item present it implicitly match K bit in default mask as "1"
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
index 5c4952242f..f617e0304f 100644
--- a/lib/librte_ethdev/rte_flow.c
+++ b/lib/librte_ethdev/rte_flow.c
@@ -74,6 +74,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 		     sizeof(struct rte_flow_item_icmp6_nd_opt_tla_eth)),
 	MK_FLOW_ITEM(MARK, sizeof(struct rte_flow_item_mark)),
 	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
+	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
 };
 
 /** Generate flow_action[] entry. */
diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
index f3a8fb103f..bdb8edee42 100644
--- a/lib/librte_ethdev/rte_flow.h
+++ b/lib/librte_ethdev/rte_flow.h
@@ -421,6 +421,19 @@ enum rte_flow_item_type {
 	 * See struct rte_flow_item_meta.
 	 */
 	RTE_FLOW_ITEM_TYPE_META,
+
+	/**
+	 * Matches a GRE optional key field.
+	 *
+	 * The value should a big-endian 32bit integer.
+	 *
+	 * When this item present the K bit is implicitly matched as "1"
+	 * in the default mask.
+	 *
+	 * @p spec/mask type:
+	 * @code rte_be32_t * @endcode
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_KEY,
 };
 
 /**
-- 
2.21.0

[dpdk-dev] [PATCH v6 2/4] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index dc48252791..0c6bf4114b 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1610,6 +1610,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1617,6 +1618,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v6 3/4] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/rel_notes/release_19_08.rst |  5 ++
 drivers/net/mlx5/mlx5_flow.c           | 61 ++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  6 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 160 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 223479c6d4..1ba551d2a7 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -128,6 +128,11 @@ New Features
   Added telemetry mode to l3fwd-power application to report
   application level busyness, empty and full polls of rte_eth_rx_burst().
 
+* **Updated Mellanox mlx5 driver.**
+
+   Updated Mellanox mlx5 driver with new features and improvements, including:
+
+   * Added support for matching on GRE's key and C,K,S present bits.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 0c6bf4114b..498d93da1b 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1562,6 +1562,61 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error)
+{
+	const rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+	if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+			 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Key bit must be on");
+
+	if (!mask)
+		mask = &gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1587,6 +1642,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(UINT16_MAX),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1606,7 +1665,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 65cfdbda9f..4439f30d8e 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -50,6 +50,8 @@
 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
 
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -462,6 +464,10 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    const struct rte_flow_item *gre_item,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 933ad0b819..16600c8f8e 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2066,6 +2066,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 	uint64_t last_item = 0;
 	uint8_t next_protocol = 0xff;
 	int actions_n = 0;
+	const struct rte_flow_item *gre_item = NULL;
 	struct rte_flow_item_tcp nic_tcp_mask = {
 		.hdr = {
 			.tcp_flags = 0xFF,
@@ -2175,8 +2176,16 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 							  next_protocol, error);
 			if (ret < 0)
 				return ret;
+			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, gre_item, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -2922,6 +2931,45 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	/* GRE K bit must be on and should already be validated */
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -2945,6 +2993,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -2965,6 +3027,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -3995,6 +4074,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1a199580c5..4022770b7b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -416,7 +416,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

[dpdk-dev] [PATCH v6 4/4] app/testpmd: match GRE's key and present bits

[Xiaoyu Min]

support matching on GRE key and present bits (C,K,S)

example testpmd command could be:
  testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
	  gre / gre_key value is 0x12345678 / end
	  actions rss queues 1 0 end / mark id 196 / end

Which will match GRE packet with k present bit set and key value is
0x12345678.

Acked-by: Ori Kam <orika@mellanox.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 app/test-pmd/cmdline_flow.c                 | 61 +++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 ++
 2 files changed, 65 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 201bd9de56..8a579b645e 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -148,6 +148,10 @@ enum index {
 	ITEM_MPLS_LABEL,
 	ITEM_GRE,
 	ITEM_GRE_PROTO,
+	ITEM_GRE_C_RSVD0_VER,
+	ITEM_GRE_C_BIT,
+	ITEM_GRE_K_BIT,
+	ITEM_GRE_S_BIT,
 	ITEM_FUZZY,
 	ITEM_FUZZY_THRESH,
 	ITEM_GTP,
@@ -181,6 +185,8 @@ enum index {
 	ITEM_ICMP6_ND_OPT_TLA_ETH_TLA,
 	ITEM_META,
 	ITEM_META_DATA,
+	ITEM_GRE_KEY,
+	ITEM_GRE_KEY_VALUE,
 
 	/* Validate/create actions. */
 	ACTIONS,
@@ -610,6 +616,7 @@ static const enum index next_item[] = {
 	ITEM_ICMP6_ND_OPT_SLA_ETH,
 	ITEM_ICMP6_ND_OPT_TLA_ETH,
 	ITEM_META,
+	ITEM_GRE_KEY,
 	ZERO,
 };
 
@@ -755,6 +762,16 @@ static const enum index item_mpls[] = {
 
 static const enum index item_gre[] = {
 	ITEM_GRE_PROTO,
+	ITEM_GRE_C_RSVD0_VER,
+	ITEM_GRE_C_BIT,
+	ITEM_GRE_K_BIT,
+	ITEM_GRE_S_BIT,
+	ITEM_NEXT,
+	ZERO,
+};
+
+static const enum index item_gre_key[] = {
+	ITEM_GRE_KEY_VALUE,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -1898,6 +1915,50 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
 					     protocol)),
 	},
+	[ITEM_GRE_C_RSVD0_VER] = {
+		.name = "c_rsvd0_ver",
+		.help = "GRE's first word (bit0 - bit15)",
+		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
+					     c_rsvd0_ver)),
+	},
+	[ITEM_GRE_C_BIT] = {
+		.name = "c_bit",
+		.help = "GRE's C present bit",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x80\x00\x00\x00")),
+	},
+	[ITEM_GRE_S_BIT] = {
+		.name = "s_bit",
+		.help = "GRE's S present bit",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x10\x00\x00\x00")),
+	},
+	[ITEM_GRE_K_BIT] = {
+		.name = "k_bit",
+		.help = "GRE's K present bit",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x20\x00\x00\x00")),
+	},
+	[ITEM_GRE_KEY] = {
+		.name = "gre_key",
+		.help = "match GRE Key",
+		.priv = PRIV_ITEM(GRE_KEY, sizeof(rte_be32_t)),
+		.next = NEXT(item_gre_key),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_KEY_VALUE] = {
+		.name = "value",
+		.help = "GRE key value",
+		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
+	},
 	[ITEM_FUZZY] = {
 		.name = "fuzzy",
 		.help = "fuzzy pattern match, expect faster than default",
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index cb83a3ce8a..9ef1796ee1 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``protocol {unsigned}``: protocol type.
 
+- ``gre_key``: match GRE optional key field.
+
+  - ``value {unsigned}``: key value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
2.21.0

Re: [dpdk-dev] [PATCH v6 1/4] ethdev: add GRE key field to flow API

[Adrien Mazarguil]

On Fri, Jul 05, 2019 at 10:14:42AM +0800, Xiaoyu Min wrote:
> Add new rte_flow_item_gre_key in order to match the optional key field.
> 
> Acked-by: Ori Kam <orika@mellanox.com>
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>

Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>

-- 
Adrien Mazarguil
6WIND

Re: [dpdk-dev] [PATCH v6 4/4] app/testpmd: match GRE's key and present bits

[Adrien Mazarguil]

On Fri, Jul 05, 2019 at 10:14:45AM +0800, Xiaoyu Min wrote:
> support matching on GRE key and present bits (C,K,S)
> 
> example testpmd command could be:
>   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> 	  gre / gre_key value is 0x12345678 / end
> 	  actions rss queues 1 0 end / mark id 196 / end
> 
> Which will match GRE packet with k present bit set and key value is
> 0x12345678.
> 
> Acked-by: Ori Kam <orika@mellanox.com>
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>

A few more nits below.

[...]
> @@ -1898,6 +1915,50 @@ static const struct token token_list[] = {
>  		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
>  					     protocol)),
>  	},
> +	[ITEM_GRE_C_RSVD0_VER] = {
> +		.name = "c_rsvd0_ver",
> +		.help = "GRE's first word (bit0 - bit15)",

Help strings on existing fields should ideally be the same as their
counterparts in rte_flow.h (shortened if necessary, not starting with a cap
and not ending "."), in this case for instance:

 .help =
         "checksum (1b), undefined (1b), key bit (1b),"
         " sequence number (1b), reserved 0 (9b),"
         " version (3b)",

> +		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> +					     c_rsvd0_ver)),
> +	},
> +	[ITEM_GRE_C_BIT] = {
> +		.name = "c_bit",
> +		.help = "GRE's C present bit",

A bit odd, here's a suggestion:

 "checksum bit (C)".

> +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
> +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
> +						  c_rsvd0_ver,
> +						  "\x80\x00\x00\x00")),
> +	},
> +	[ITEM_GRE_S_BIT] = {
> +		.name = "s_bit",
> +		.help = "GRE's S present bit",

Ditto:

 "sequence number bit (S)"

> +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
> +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
> +						  c_rsvd0_ver,
> +						  "\x10\x00\x00\x00")),
> +	},
> +	[ITEM_GRE_K_BIT] = {
> +		.name = "k_bit",
> +		.help = "GRE's K present bit",

Ditto:

 "key bit (K)"

> +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
> +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
> +						  c_rsvd0_ver,
> +						  "\x20\x00\x00\x00")),
> +	},
> +	[ITEM_GRE_KEY] = {
> +		.name = "gre_key",
> +		.help = "match GRE Key",

Nit: no caps for "Key" => "match GRE key"

> +		.priv = PRIV_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> +		.next = NEXT(item_gre_key),
> +		.call = parse_vc,
> +	},
> +	[ITEM_GRE_KEY_VALUE] = {
> +		.name = "value",
> +		.help = "GRE key value",

No need to repeat "GRE" here since it's already in GRE context:

 "key value"

> +		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
> +		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
> +	},

Also ITEM_GRE_KEY and ITEM_GRE_KEY_VALUE should come after ITEM_META_DATA to
keep the same order as everywhere else.

Then assuming all the suggested changes are made:

Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>

Note I did not look at mlx5 patches, please make sure someone has reviewed
them. Thanks.

-- 
Adrien Mazarguil
6WIND

Re: [dpdk-dev] [PATCH v6 4/4] app/testpmd: match GRE's key and present bits

[Jack Min]

On Fri, 19-07-05, 10:58, Adrien Mazarguil wrote:
> On Fri, Jul 05, 2019 at 10:14:45AM +0800, Xiaoyu Min wrote:
> > support matching on GRE key and present bits (C,K,S)
> > 
> > example testpmd command could be:
> >   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> > 	  gre / gre_key value is 0x12345678 / end
> > 	  actions rss queues 1 0 end / mark id 196 / end
> > 
> > Which will match GRE packet with k present bit set and key value is
> > 0x12345678.
> > 
> > Acked-by: Ori Kam <orika@mellanox.com>
> > Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
> 
> A few more nits below.
> 
> [...]
> > @@ -1898,6 +1915,50 @@ static const struct token token_list[] = {
> >  		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> >  					     protocol)),
> >  	},
> > +	[ITEM_GRE_C_RSVD0_VER] = {
> > +		.name = "c_rsvd0_ver",
> > +		.help = "GRE's first word (bit0 - bit15)",
> 
> Help strings on existing fields should ideally be the same as their
> counterparts in rte_flow.h (shortened if necessary, not starting with a cap
> and not ending "."), in this case for instance:
> 
Didn't know this before.

>  .help =
>          "checksum (1b), undefined (1b), key bit (1b),"
>          " sequence number (1b), reserved 0 (9b),"
>          " version (3b)",
> 
I'll update.

> > +		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
> > +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> > +					     c_rsvd0_ver)),
> > +	},
> > +	[ITEM_GRE_C_BIT] = {
> > +		.name = "c_bit",
> > +		.help = "GRE's C present bit",
> 
> A bit odd, here's a suggestion:
> 
>  "checksum bit (C)".
> 
I'll update.

> > +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
> > +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
> > +						  c_rsvd0_ver,
> > +						  "\x80\x00\x00\x00")),
> > +	},
> > +	[ITEM_GRE_S_BIT] = {
> > +		.name = "s_bit",
> > +		.help = "GRE's S present bit",
> 
> Ditto:
> 
>  "sequence number bit (S)"
> 
Ditto.

> > +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
> > +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
> > +						  c_rsvd0_ver,
> > +						  "\x10\x00\x00\x00")),
> > +	},
> > +	[ITEM_GRE_K_BIT] = {
> > +		.name = "k_bit",
> > +		.help = "GRE's K present bit",
> 
> Ditto:
> 
>  "key bit (K)"
> 
Ditto.

> > +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
> > +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
> > +						  c_rsvd0_ver,
> > +						  "\x20\x00\x00\x00")),
> > +	},
> > +	[ITEM_GRE_KEY] = {
> > +		.name = "gre_key",
> > +		.help = "match GRE Key",
> 
> Nit: no caps for "Key" => "match GRE key"
> 
OK.

> > +		.priv = PRIV_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> > +		.next = NEXT(item_gre_key),
> > +		.call = parse_vc,
> > +	},
> > +	[ITEM_GRE_KEY_VALUE] = {
> > +		.name = "value",
> > +		.help = "GRE key value",
> 
> No need to repeat "GRE" here since it's already in GRE context:
> 
>  "key value"
> 
OK.

> > +		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
> > +		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
> > +	},
> 
> Also ITEM_GRE_KEY and ITEM_GRE_KEY_VALUE should come after ITEM_META_DATA to
> keep the same order as everywhere else.
> 
Yes, it should be. 

> Then assuming all the suggested changes are made:
> 
> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
> 
Thank you!

> Note I did not look at mlx5 patches, please make sure someone has reviewed
> them. Thanks.
> 
Yes, Slava will review them.

> -- 
> Adrien Mazarguil
> 6WIND

[dpdk-dev] [PATCH v7 0/4] match on GRE's key

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

[1] https://patches.dpdk.org/patch/53432/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention
v3:
  * updated release note
  * fixed one bug
v4:
  * resend patchs in thread mode
v5:
  * report error when K is off but gre_key item present
  * removed ITEM_CRKSV, added c_bit, k_bit, s_bit in testpmd
  * document updated
v6:
  * one fix in pmd
v7:
  * addressed comments in TestPMD
---
Xiaoyu Min (4):
  ethdev: add GRE key field to flow API
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits
  app/testpmd: match GRE's key and present bits

 app/test-pmd/cmdline_flow.c                 | 64 ++++++++++++++++
 doc/guides/prog_guide/rte_flow.rst          |  9 +++
 doc/guides/rel_notes/release_19_08.rst      |  5 ++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 +
 drivers/net/mlx5/mlx5_flow.c                | 63 +++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h                |  6 ++
 drivers/net/mlx5/mlx5_flow_dv.c             | 84 +++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h                 |  6 +-
 lib/librte_ethdev/rte_flow.c                |  1 +
 lib/librte_ethdev/rte_flow.h                | 13 ++++
 10 files changed, 253 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v7 1/4] ethdev: add GRE key field to flow API

[Xiaoyu Min]

Add new rte_flow_item_gre_key in order to match the optional key field.

Acked-by: Ori Kam <orika@mellanox.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/prog_guide/rte_flow.rst |  9 +++++++++
 lib/librte_ethdev/rte_flow.c       |  1 +
 lib/librte_ethdev/rte_flow.h       | 13 +++++++++++++
 3 files changed, 23 insertions(+)

diff --git a/doc/guides/prog_guide/rte_flow.rst b/doc/guides/prog_guide/rte_flow.rst
index a34d012e55..8072fc1664 100644
--- a/doc/guides/prog_guide/rte_flow.rst
+++ b/doc/guides/prog_guide/rte_flow.rst
@@ -980,6 +980,15 @@ Matches a GRE header.
 - ``protocol``: protocol type.
 - Default ``mask`` matches protocol only.
 
+Item: ``GRE_KEY``
+^^^^^^^^^^^^^^^^^
+
+Matches a GRE key field.
+This should be preceded by item ``GRE``.
+
+- Value to be matched is a big-endian 32 bit integer.
+- When this item present it implicitly match K bit in default mask as "1"
+
 Item: ``FUZZY``
 ^^^^^^^^^^^^^^^
 
diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c
index 5c4952242f..f617e0304f 100644
--- a/lib/librte_ethdev/rte_flow.c
+++ b/lib/librte_ethdev/rte_flow.c
@@ -74,6 +74,7 @@ static const struct rte_flow_desc_data rte_flow_desc_item[] = {
 		     sizeof(struct rte_flow_item_icmp6_nd_opt_tla_eth)),
 	MK_FLOW_ITEM(MARK, sizeof(struct rte_flow_item_mark)),
 	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
+	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
 };
 
 /** Generate flow_action[] entry. */
diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h
index f3a8fb103f..bdb8edee42 100644
--- a/lib/librte_ethdev/rte_flow.h
+++ b/lib/librte_ethdev/rte_flow.h
@@ -421,6 +421,19 @@ enum rte_flow_item_type {
 	 * See struct rte_flow_item_meta.
 	 */
 	RTE_FLOW_ITEM_TYPE_META,
+
+	/**
+	 * Matches a GRE optional key field.
+	 *
+	 * The value should a big-endian 32bit integer.
+	 *
+	 * When this item present the K bit is implicitly matched as "1"
+	 * in the default mask.
+	 *
+	 * @p spec/mask type:
+	 * @code rte_be32_t * @endcode
+	 */
+	RTE_FLOW_ITEM_TYPE_GRE_KEY,
 };
 
 /**
-- 
2.21.0

[dpdk-dev] [PATCH v7 2/4] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index dc48252791..0c6bf4114b 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1610,6 +1610,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1617,6 +1618,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v7 3/4] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 doc/guides/rel_notes/release_19_08.rst |  5 ++
 drivers/net/mlx5/mlx5_flow.c           | 61 ++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  6 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 160 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 223479c6d4..1ba551d2a7 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -128,6 +128,11 @@ New Features
   Added telemetry mode to l3fwd-power application to report
   application level busyness, empty and full polls of rte_eth_rx_burst().
 
+* **Updated Mellanox mlx5 driver.**
+
+   Updated Mellanox mlx5 driver with new features and improvements, including:
+
+   * Added support for matching on GRE's key and C,K,S present bits.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 0c6bf4114b..fbae33a768 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1562,6 +1562,61 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error)
+{
+	const rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+	if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+			 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Key bit must be on");
+
+	if (!mask)
+		mask = &gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1587,6 +1642,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1606,7 +1665,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 65cfdbda9f..4439f30d8e 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -50,6 +50,8 @@
 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
 
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
+
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
 	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
@@ -462,6 +464,10 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    const struct rte_flow_item *gre_item,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 933ad0b819..16600c8f8e 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2066,6 +2066,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 	uint64_t last_item = 0;
 	uint8_t next_protocol = 0xff;
 	int actions_n = 0;
+	const struct rte_flow_item *gre_item = NULL;
 	struct rte_flow_item_tcp nic_tcp_mask = {
 		.hdr = {
 			.tcp_flags = 0xFF,
@@ -2175,8 +2176,16 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 							  next_protocol, error);
 			if (ret < 0)
 				return ret;
+			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, gre_item, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -2922,6 +2931,45 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	/* GRE K bit must be on and should already be validated */
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -2945,6 +2993,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -2965,6 +3027,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -3995,6 +4074,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 1a199580c5..4022770b7b 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -416,7 +416,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

[dpdk-dev] [PATCH v7 4/4] app/testpmd: match GRE's key and present bits

[Xiaoyu Min]

support matching on GRE key and present bits (C,K,S)

example testpmd command could be:
  testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
	  gre / gre_key value is 0x12345678 / end
	  actions rss queues 1 0 end / mark id 196 / end

Which will match GRE packet with k present bit set and key value is
0x12345678.

Acked-by: Ori Kam <orika@mellanox.com>
Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
---
 app/test-pmd/cmdline_flow.c                 | 64 +++++++++++++++++++++
 doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 ++
 2 files changed, 68 insertions(+)

diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
index 201bd9de56..949a38a0e7 100644
--- a/app/test-pmd/cmdline_flow.c
+++ b/app/test-pmd/cmdline_flow.c
@@ -148,6 +148,10 @@ enum index {
 	ITEM_MPLS_LABEL,
 	ITEM_GRE,
 	ITEM_GRE_PROTO,
+	ITEM_GRE_C_RSVD0_VER,
+	ITEM_GRE_C_BIT,
+	ITEM_GRE_K_BIT,
+	ITEM_GRE_S_BIT,
 	ITEM_FUZZY,
 	ITEM_FUZZY_THRESH,
 	ITEM_GTP,
@@ -181,6 +185,8 @@ enum index {
 	ITEM_ICMP6_ND_OPT_TLA_ETH_TLA,
 	ITEM_META,
 	ITEM_META_DATA,
+	ITEM_GRE_KEY,
+	ITEM_GRE_KEY_VALUE,
 
 	/* Validate/create actions. */
 	ACTIONS,
@@ -610,6 +616,7 @@ static const enum index next_item[] = {
 	ITEM_ICMP6_ND_OPT_SLA_ETH,
 	ITEM_ICMP6_ND_OPT_TLA_ETH,
 	ITEM_META,
+	ITEM_GRE_KEY,
 	ZERO,
 };
 
@@ -755,6 +762,16 @@ static const enum index item_mpls[] = {
 
 static const enum index item_gre[] = {
 	ITEM_GRE_PROTO,
+	ITEM_GRE_C_RSVD0_VER,
+	ITEM_GRE_C_BIT,
+	ITEM_GRE_K_BIT,
+	ITEM_GRE_S_BIT,
+	ITEM_NEXT,
+	ZERO,
+};
+
+static const enum index item_gre_key[] = {
+	ITEM_GRE_KEY_VALUE,
 	ITEM_NEXT,
 	ZERO,
 };
@@ -1898,6 +1915,40 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
 					     protocol)),
 	},
+	[ITEM_GRE_C_RSVD0_VER] = {
+		.name = "c_rsvd0_ver",
+		.help =
+			"checksum (1b), undefined (1b), key bit (1b),"
+			" sequence number (1b), reserved 0 (9b),"
+			" version (3b)",
+		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
+					     c_rsvd0_ver)),
+	},
+	[ITEM_GRE_C_BIT] = {
+		.name = "c_bit",
+		.help = "checksum bit (C)",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x80\x00\x00\x00")),
+	},
+	[ITEM_GRE_S_BIT] = {
+		.name = "s_bit",
+		.help = "sequence number bit (S)",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x10\x00\x00\x00")),
+	},
+	[ITEM_GRE_K_BIT] = {
+		.name = "k_bit",
+		.help = "key bit (K)",
+		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN), item_param),
+		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_gre,
+						  c_rsvd0_ver,
+						  "\x20\x00\x00\x00")),
+	},
 	[ITEM_FUZZY] = {
 		.name = "fuzzy",
 		.help = "fuzzy pattern match, expect faster than default",
@@ -2150,6 +2201,19 @@ static const struct token token_list[] = {
 		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct rte_flow_item_meta,
 						  data, "\xff\xff\xff\xff")),
 	},
+	[ITEM_GRE_KEY] = {
+		.name = "gre_key",
+		.help = "match GRE key",
+		.priv = PRIV_ITEM(GRE_KEY, sizeof(rte_be32_t)),
+		.next = NEXT(item_gre_key),
+		.call = parse_vc,
+	},
+	[ITEM_GRE_KEY_VALUE] = {
+		.name = "value",
+		.help = "key value",
+		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED), item_param),
+		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
+	},
 
 	/* Validate/create actions. */
 	[ACTIONS] = {
diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
index cb83a3ce8a..9ef1796ee1 100644
--- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
+++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
@@ -3804,6 +3804,10 @@ This section lists supported pattern items and their attributes, if any.
 
   - ``protocol {unsigned}``: protocol type.
 
+- ``gre_key``: match GRE optional key field.
+
+  - ``value {unsigned}``: key value.
+
 - ``fuzzy``: fuzzy pattern match, expect faster than default.
 
   - ``thresh {unsigned}``: accuracy threshold.
-- 
2.21.0

Re: [dpdk-dev] [PATCH v7 0/4] match on GRE's key

[Ferruh Yigit]

On 7/5/2019 10:54 AM, Xiaoyu Min wrote:
> This series patchs are based on RFC [1], which enable the matching on
> GRE's key field.
> And enabled MLX5 device supports on this.
> 
> [1] https://patches.dpdk.org/patch/53432/
> 
> ---
> v2:
>   * remove struct rte_flow_item_gre_key in order to comply new convention
> v3:
>   * updated release note
>   * fixed one bug
> v4:
>   * resend patchs in thread mode
> v5:
>   * report error when K is off but gre_key item present
>   * removed ITEM_CRKSV, added c_bit, k_bit, s_bit in testpmd
>   * document updated
> v6:
>   * one fix in pmd
> v7:
>   * addressed comments in TestPMD
> ---
> Xiaoyu Min (4):
>   ethdev: add GRE key field to flow API
>   net/mlx5: support match GRE protocol on DR engine
>   net/mlx5: match GRE's key and present bits
>   app/testpmd: match GRE's key and present bits

mlx5 patches seems not acked by mlx5 maintainers, also it conflicts with latest
next-net-mlx5 tree, so only getting ethdev + testpmd. mlx patches can go in in rc2.

Series partially applied to dpdk-next-net/master, thanks.

Re: [dpdk-dev] [Suspected-Phishing][PATCH v7 1/4] ethdev: add GRE key field to flow API

[Slava Ovsiienko]

> -----Original Message-----
> From: Xiaoyu Min <jackmin@mellanox.com>
> Sent: Friday, July 5, 2019 12:54
> To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; Ori Kam
> <orika@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>;
> John McNamara <john.mcnamara@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Thomas Monjalon
> <thomas@monjalon.net>; Ferruh Yigit <ferruh.yigit@intel.com>; Andrew
> Rybchenko <arybchenko@solarflare.com>
> Cc: dev@dpdk.org
> Subject: [Suspected-Phishing][PATCH v7 1/4] ethdev: add GRE key field to
> flow API
> 
> Add new rte_flow_item_gre_key in order to match the optional key field.
> 
> Acked-by: Ori Kam <orika@mellanox.com>
> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

> ---
>  doc/guides/prog_guide/rte_flow.rst |  9 +++++++++
>  lib/librte_ethdev/rte_flow.c       |  1 +
>  lib/librte_ethdev/rte_flow.h       | 13 +++++++++++++
>  3 files changed, 23 insertions(+)
> 
> diff --git a/doc/guides/prog_guide/rte_flow.rst
> b/doc/guides/prog_guide/rte_flow.rst
> index a34d012e55..8072fc1664 100644
> --- a/doc/guides/prog_guide/rte_flow.rst
> +++ b/doc/guides/prog_guide/rte_flow.rst
> @@ -980,6 +980,15 @@ Matches a GRE header.
>  - ``protocol``: protocol type.
>  - Default ``mask`` matches protocol only.
> 
> +Item: ``GRE_KEY``
> +^^^^^^^^^^^^^^^^^
> +
> +Matches a GRE key field.
> +This should be preceded by item ``GRE``.
> +
> +- Value to be matched is a big-endian 32 bit integer.
> +- When this item present it implicitly match K bit in default mask as "1"
> +
>  Item: ``FUZZY``
>  ^^^^^^^^^^^^^^^
> 
> diff --git a/lib/librte_ethdev/rte_flow.c b/lib/librte_ethdev/rte_flow.c index
> 5c4952242f..f617e0304f 100644
> --- a/lib/librte_ethdev/rte_flow.c
> +++ b/lib/librte_ethdev/rte_flow.c
> @@ -74,6 +74,7 @@ static const struct rte_flow_desc_data
> rte_flow_desc_item[] = {
>  		     sizeof(struct rte_flow_item_icmp6_nd_opt_tla_eth)),
>  	MK_FLOW_ITEM(MARK, sizeof(struct rte_flow_item_mark)),
>  	MK_FLOW_ITEM(META, sizeof(struct rte_flow_item_meta)),
> +	MK_FLOW_ITEM(GRE_KEY, sizeof(rte_be32_t)),
>  };
> 
>  /** Generate flow_action[] entry. */
> diff --git a/lib/librte_ethdev/rte_flow.h b/lib/librte_ethdev/rte_flow.h index
> f3a8fb103f..bdb8edee42 100644
> --- a/lib/librte_ethdev/rte_flow.h
> +++ b/lib/librte_ethdev/rte_flow.h
> @@ -421,6 +421,19 @@ enum rte_flow_item_type {
>  	 * See struct rte_flow_item_meta.
>  	 */
>  	RTE_FLOW_ITEM_TYPE_META,
> +
> +	/**
> +	 * Matches a GRE optional key field.
> +	 *
> +	 * The value should a big-endian 32bit integer.
> +	 *
> +	 * When this item present the K bit is implicitly matched as "1"
> +	 * in the default mask.
> +	 *
> +	 * @p spec/mask type:
> +	 * @code rte_be32_t * @endcode
> +	 */
> +	RTE_FLOW_ITEM_TYPE_GRE_KEY,
>  };
> 
>  /**
> --
> 2.21.0

Re: [dpdk-dev] [Suspected-Phishing][PATCH v7 2/4] net/mlx5: support match GRE protocol on DR engine

[Slava Ovsiienko]

> -----Original Message-----
> From: Xiaoyu Min <jackmin@mellanox.com>
> Sent: Friday, July 5, 2019 12:54
> To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; Ori Kam
> <orika@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>;
> Shahaf Shuler <shahafs@mellanox.com>; Yongseok Koh
> <yskoh@mellanox.com>
> Cc: dev@dpdk.org
> Subject: [Suspected-Phishing][PATCH v7 2/4] net/mlx5: support match GRE
> protocol on DR engine
> 
> DR engine support matching on GRE protocol field without MPLS supports.
> So bypassing the MPLS check when DR is enabled.
> 
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

> ---
>  drivers/net/mlx5/mlx5_flow.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
> index dc48252791..0c6bf4114b 100644
> --- a/drivers/net/mlx5/mlx5_flow.c
> +++ b/drivers/net/mlx5/mlx5_flow.c
> @@ -1610,6 +1610,7 @@ mlx5_flow_validate_item_gre(const struct
> rte_flow_item *item,
>  		 sizeof(struct rte_flow_item_gre), error);
>  	if (ret < 0)
>  		return ret;
> +#ifndef HAVE_MLX5DV_DR
>  #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
>  	if (spec && (spec->protocol & mask->protocol))
>  		return rte_flow_error_set(error, ENOTSUP, @@ -1617,6
> +1618,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item
> *item,
>  					  "without MPLS support the"
>  					  " specification cannot be used for"
>  					  " filtering");
> +#endif
>  #endif
>  	return 0;
>  }
> --
> 2.21.0

Re: [dpdk-dev] [Suspected-Phishing][PATCH v7 3/4] net/mlx5: match GRE's key and present bits

[Slava Ovsiienko]

> -----Original Message-----
> From: Xiaoyu Min <jackmin@mellanox.com>
> Sent: Friday, July 5, 2019 12:54
> To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; Ori Kam
> <orika@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>;
> John McNamara <john.mcnamara@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>; Shahaf Shuler <shahafs@mellanox.com>;
> Yongseok Koh <yskoh@mellanox.com>
> Cc: dev@dpdk.org
> Subject: [Suspected-Phishing][PATCH v7 3/4] net/mlx5: match GRE's key and
> present bits
> 
> support matching on the present bits (C,K,S) as well as the optional key field.
> 
> If the rte_flow_item_gre_key is specified in pattern, it will set K present
> match automatically.
> 
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

> ---
>  doc/guides/rel_notes/release_19_08.rst |  5 ++
>  drivers/net/mlx5/mlx5_flow.c           | 61 ++++++++++++++++++-
>  drivers/net/mlx5/mlx5_flow.h           |  6 ++
>  drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
>  drivers/net/mlx5/mlx5_prm.h            |  6 +-
>  5 files changed, 160 insertions(+), 2 deletions(-)
> 
> diff --git a/doc/guides/rel_notes/release_19_08.rst
> b/doc/guides/rel_notes/release_19_08.rst
> index 223479c6d4..1ba551d2a7 100644
> --- a/doc/guides/rel_notes/release_19_08.rst
> +++ b/doc/guides/rel_notes/release_19_08.rst
> @@ -128,6 +128,11 @@ New Features
>    Added telemetry mode to l3fwd-power application to report
>    application level busyness, empty and full polls of rte_eth_rx_burst().
> 
> +* **Updated Mellanox mlx5 driver.**
> +
> +   Updated Mellanox mlx5 driver with new features and improvements,
> including:
> +
> +   * Added support for matching on GRE's key and C,K,S present bits.
> 
>  Removed Items
>  -------------
> diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
> index 0c6bf4114b..fbae33a768 100644
> --- a/drivers/net/mlx5/mlx5_flow.c
> +++ b/drivers/net/mlx5/mlx5_flow.c
> @@ -1562,6 +1562,61 @@ mlx5_flow_validate_item_vxlan_gpe(const
> struct rte_flow_item *item,
>  					  " defined");
>  	return 0;
>  }
> +/**
> + * Validate GRE Key item.
> + *
> + * @param[in] item
> + *   Item specification.
> + * @param[in] item_flags
> + *   Bit flags to mark detected items.
> + * @param[in] gre_item
> + *   Pointer to gre_item
> + * @param[out] error
> + *   Pointer to error structure.
> + *
> + * @return
> + *   0 on success, a negative errno value otherwise and rte_errno is set.
> + */
> +int
> +mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
> +				uint64_t item_flags,
> +				const struct rte_flow_item *gre_item,
> +				struct rte_flow_error *error)
> +{
> +	const rte_be32_t *mask = item->mask;
> +	int ret = 0;
> +	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
> +	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
> +	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
> +
> +	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
> +		return rte_flow_error_set(error, ENOTSUP,
> +					  RTE_FLOW_ERROR_TYPE_ITEM,
> item,
> +					  "Multiple GRE key not support");
> +	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
> +		return rte_flow_error_set(error, ENOTSUP,
> +					  RTE_FLOW_ERROR_TYPE_ITEM,
> item,
> +					  "No preceding GRE header");
> +	if (item_flags & MLX5_FLOW_LAYER_INNER)
> +		return rte_flow_error_set(error, ENOTSUP,
> +					  RTE_FLOW_ERROR_TYPE_ITEM,
> item,
> +					  "GRE key following a wrong item");
> +	if (!gre_mask)
> +		gre_mask = &rte_flow_item_gre_mask;
> +	if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
> +			 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
> +		return rte_flow_error_set(error, EINVAL,
> +					  RTE_FLOW_ERROR_TYPE_ITEM,
> item,
> +					  "Key bit must be on");
> +
> +	if (!mask)
> +		mask = &gre_key_default_mask;
> +	ret = mlx5_flow_item_acceptable
> +		(item, (const uint8_t *)mask,
> +		 (const uint8_t *)&gre_key_default_mask,
> +		 sizeof(rte_be32_t), error);
> +	return ret;
> +}
> 
>  /**
>   * Validate GRE item.
> @@ -1587,6 +1642,10 @@ mlx5_flow_validate_item_gre(const struct
> rte_flow_item *item,
>  	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
>  	const struct rte_flow_item_gre *mask = item->mask;
>  	int ret;
> +	const struct rte_flow_item_gre nic_mask = {
> +		.c_rsvd0_ver = RTE_BE16(0xB000),
> +		.protocol = RTE_BE16(UINT16_MAX),
> +	};
> 
>  	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
>  		return rte_flow_error_set(error, EINVAL, @@ -1606,7
> +1665,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item
> *item,
>  		mask = &rte_flow_item_gre_mask;
>  	ret = mlx5_flow_item_acceptable
>  		(item, (const uint8_t *)mask,
> -		 (const uint8_t *)&rte_flow_item_gre_mask,
> +		 (const uint8_t *)&nic_mask,
>  		 sizeof(struct rte_flow_item_gre), error);
>  	if (ret < 0)
>  		return ret;
> diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
> index 65cfdbda9f..4439f30d8e 100644
> --- a/drivers/net/mlx5/mlx5_flow.h
> +++ b/drivers/net/mlx5/mlx5_flow.h
> @@ -50,6 +50,8 @@
>  #define MLX5_FLOW_ITEM_METADATA (1u << 16)  #define
> MLX5_FLOW_ITEM_PORT_ID (1u << 17)
> 
> +#define MLX5_FLOW_LAYER_GRE_KEY (1u << 18)
> +
>  /* Outer Masks. */
>  #define MLX5_FLOW_LAYER_OUTER_L3 \
>  	(MLX5_FLOW_LAYER_OUTER_L3_IPV4 |
> MLX5_FLOW_LAYER_OUTER_L3_IPV6) @@ -462,6 +464,10 @@ int
> mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
>  				uint64_t item_flags,
>  				uint8_t target_protocol,
>  				struct rte_flow_error *error);
> +int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
> +				    uint64_t item_flags,
> +				    const struct rte_flow_item *gre_item,
> +				    struct rte_flow_error *error);
>  int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
>  				 uint64_t item_flags,
>  				 const struct rte_flow_item_ipv4 *acc_mask,
> diff --git a/drivers/net/mlx5/mlx5_flow_dv.c
> b/drivers/net/mlx5/mlx5_flow_dv.c index 933ad0b819..16600c8f8e 100644
> --- a/drivers/net/mlx5/mlx5_flow_dv.c
> +++ b/drivers/net/mlx5/mlx5_flow_dv.c
> @@ -2066,6 +2066,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const
> struct rte_flow_attr *attr,
>  	uint64_t last_item = 0;
>  	uint8_t next_protocol = 0xff;
>  	int actions_n = 0;
> +	const struct rte_flow_item *gre_item = NULL;
>  	struct rte_flow_item_tcp nic_tcp_mask = {
>  		.hdr = {
>  			.tcp_flags = 0xFF,
> @@ -2175,8 +2176,16 @@ flow_dv_validate(struct rte_eth_dev *dev, const
> struct rte_flow_attr *attr,
>  							  next_protocol,
> error);
>  			if (ret < 0)
>  				return ret;
> +			gre_item = items;
>  			last_item = MLX5_FLOW_LAYER_GRE;
>  			break;
> +		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
> +			ret = mlx5_flow_validate_item_gre_key
> +				(items, item_flags, gre_item, error);
> +			if (ret < 0)
> +				return ret;
> +			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
> +			break;
>  		case RTE_FLOW_ITEM_TYPE_VXLAN:
>  			ret = mlx5_flow_validate_item_vxlan(items,
> item_flags,
>  							    error);
> @@ -2922,6 +2931,45 @@ flow_dv_translate_item_udp(void *matcher,
> void *key,
>  		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m-
> >hdr.dst_port));  }
> 
> +/**
> + * Add GRE optional Key item to matcher and to the value.
> + *
> + * @param[in, out] matcher
> + *   Flow matcher.
> + * @param[in, out] key
> + *   Flow matcher value.
> + * @param[in] item
> + *   Flow pattern to translate.
> + * @param[in] inner
> + *   Item is inner pattern.
> + */
> +static void
> +flow_dv_translate_item_gre_key(void *matcher, void *key,
> +				   const struct rte_flow_item *item) {
> +	const rte_be32_t *key_m = item->mask;
> +	const rte_be32_t *key_v = item->spec;
> +	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher,
> misc_parameters);
> +	void *misc_v = MLX5_ADDR_OF(fte_match_param, key,
> misc_parameters);
> +	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
> +
> +	if (!key_v)
> +		return;
> +	if (!key_m)
> +		key_m = &gre_key_default_mask;
> +	/* GRE K bit must be on and should already be validated */
> +	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
> +	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
> +	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
> +		 rte_be_to_cpu_32(*key_m) >> 8);
> +	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
> +		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
> +	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
> +		 rte_be_to_cpu_32(*key_m) & 0xFF);
> +	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
> +		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF); }
> +
>  /**
>   * Add GRE item to matcher and to the value.
>   *
> @@ -2945,6 +2993,20 @@ flow_dv_translate_item_gre(void *matcher, void
> *key,
>  	void *headers_v;
>  	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher,
> misc_parameters);
>  	void *misc_v = MLX5_ADDR_OF(fte_match_param, key,
> misc_parameters);
> +	struct {
> +		union {
> +			__extension__
> +			struct {
> +				uint16_t version:3;
> +				uint16_t rsvd0:9;
> +				uint16_t s_present:1;
> +				uint16_t k_present:1;
> +				uint16_t rsvd_bit1:1;
> +				uint16_t c_present:1;
> +			};
> +			uint16_t value;
> +		};
> +	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
> 
>  	if (inner) {
>  		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
> @@ -2965,6 +3027,23 @@ flow_dv_translate_item_gre(void *matcher, void
> *key,
>  		 rte_be_to_cpu_16(gre_m->protocol));
>  	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
>  		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
> +	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m-
> >c_rsvd0_ver);
> +	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v-
> >c_rsvd0_ver);
> +	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
> +		 gre_crks_rsvd0_ver_m.c_present);
> +	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
> +		 gre_crks_rsvd0_ver_v.c_present &
> +		 gre_crks_rsvd0_ver_m.c_present);
> +	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
> +		 gre_crks_rsvd0_ver_m.k_present);
> +	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
> +		 gre_crks_rsvd0_ver_v.k_present &
> +		 gre_crks_rsvd0_ver_m.k_present);
> +	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
> +		 gre_crks_rsvd0_ver_m.s_present);
> +	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
> +		 gre_crks_rsvd0_ver_v.s_present &
> +		 gre_crks_rsvd0_ver_m.s_present);
>  }
> 
>  /**
> @@ -3995,6 +4074,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
>  						   items, tunnel);
>  			last_item = MLX5_FLOW_LAYER_GRE;
>  			break;
> +		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
> +			flow_dv_translate_item_gre_key(match_mask,
> +						       match_value, items);
> +			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
> +			break;
>  		case RTE_FLOW_ITEM_TYPE_NVGRE:
>  			flow_dv_translate_item_nvgre(match_mask,
> match_value,
>  						     items, tunnel);
> diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
> index 1a199580c5..4022770b7b 100644
> --- a/drivers/net/mlx5/mlx5_prm.h
> +++ b/drivers/net/mlx5/mlx5_prm.h
> @@ -416,7 +416,11 @@ typedef uint8_t u8;  #define
> MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
> 
>  struct mlx5_ifc_fte_match_set_misc_bits {
> -	u8 reserved_at_0[0x8];
> +	u8 gre_c_present[0x1];
> +	u8 reserved_at_1[0x1];
> +	u8 gre_k_present[0x1];
> +	u8 gre_s_present[0x1];
> +	u8 source_vhci_port[0x4];
>  	u8 source_sqn[0x18];
>  	u8 reserved_at_20[0x10];
>  	u8 source_port[0x10];
> --
> 2.21.0

Re: [dpdk-dev] [Suspected-Phishing][PATCH v7 4/4] app/testpmd: match GRE's key and present bits

[Slava Ovsiienko]

> -----Original Message-----
> From: Xiaoyu Min <jackmin@mellanox.com>
> Sent: Friday, July 5, 2019 12:54
> To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; Ori Kam
> <orika@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>;
> Wenzhuo Lu <wenzhuo.lu@intel.com>; Jingjing Wu
> <jingjing.wu@intel.com>; Bernard Iremonger
> <bernard.iremonger@intel.com>; John McNamara
> <john.mcnamara@intel.com>; Marko Kovacevic
> <marko.kovacevic@intel.com>
> Cc: dev@dpdk.org
> Subject: [Suspected-Phishing][PATCH v7 4/4] app/testpmd: match GRE's key
> and present bits
> 
> support matching on GRE key and present bits (C,K,S)
> 
> example testpmd command could be:
>   testpmd>flow create 0 ingress group 1 pattern eth / ipv4 /
> 	  gre / gre_key value is 0x12345678 / end
> 	  actions rss queues 1 0 end / mark id 196 / end
> 
> Which will match GRE packet with k present bit set and key value is
> 0x12345678.
> 
> Acked-by: Ori Kam <orika@mellanox.com>
> Acked-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
> Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

> ---
>  app/test-pmd/cmdline_flow.c                 | 64 +++++++++++++++++++++
>  doc/guides/testpmd_app_ug/testpmd_funcs.rst |  4 ++
>  2 files changed, 68 insertions(+)
> 
> diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c
> index 201bd9de56..949a38a0e7 100644
> --- a/app/test-pmd/cmdline_flow.c
> +++ b/app/test-pmd/cmdline_flow.c
> @@ -148,6 +148,10 @@ enum index {
>  	ITEM_MPLS_LABEL,
>  	ITEM_GRE,
>  	ITEM_GRE_PROTO,
> +	ITEM_GRE_C_RSVD0_VER,
> +	ITEM_GRE_C_BIT,
> +	ITEM_GRE_K_BIT,
> +	ITEM_GRE_S_BIT,
>  	ITEM_FUZZY,
>  	ITEM_FUZZY_THRESH,
>  	ITEM_GTP,
> @@ -181,6 +185,8 @@ enum index {
>  	ITEM_ICMP6_ND_OPT_TLA_ETH_TLA,
>  	ITEM_META,
>  	ITEM_META_DATA,
> +	ITEM_GRE_KEY,
> +	ITEM_GRE_KEY_VALUE,
> 
>  	/* Validate/create actions. */
>  	ACTIONS,
> @@ -610,6 +616,7 @@ static const enum index next_item[] = {
>  	ITEM_ICMP6_ND_OPT_SLA_ETH,
>  	ITEM_ICMP6_ND_OPT_TLA_ETH,
>  	ITEM_META,
> +	ITEM_GRE_KEY,
>  	ZERO,
>  };
> 
> @@ -755,6 +762,16 @@ static const enum index item_mpls[] = {
> 
>  static const enum index item_gre[] = {
>  	ITEM_GRE_PROTO,
> +	ITEM_GRE_C_RSVD0_VER,
> +	ITEM_GRE_C_BIT,
> +	ITEM_GRE_K_BIT,
> +	ITEM_GRE_S_BIT,
> +	ITEM_NEXT,
> +	ZERO,
> +};
> +
> +static const enum index item_gre_key[] = {
> +	ITEM_GRE_KEY_VALUE,
>  	ITEM_NEXT,
>  	ZERO,
>  };
> @@ -1898,6 +1915,40 @@ static const struct token token_list[] = {
>  		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
>  					     protocol)),
>  	},
> +	[ITEM_GRE_C_RSVD0_VER] = {
> +		.name = "c_rsvd0_ver",
> +		.help =
> +			"checksum (1b), undefined (1b), key bit (1b),"
> +			" sequence number (1b), reserved 0 (9b),"
> +			" version (3b)",
> +		.next = NEXT(item_gre, NEXT_ENTRY(UNSIGNED),
> item_param),
> +		.args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gre,
> +					     c_rsvd0_ver)),
> +	},
> +	[ITEM_GRE_C_BIT] = {
> +		.name = "c_bit",
> +		.help = "checksum bit (C)",
> +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN),
> item_param),
> +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct
> rte_flow_item_gre,
> +						  c_rsvd0_ver,
> +						  "\x80\x00\x00\x00")),
> +	},
> +	[ITEM_GRE_S_BIT] = {
> +		.name = "s_bit",
> +		.help = "sequence number bit (S)",
> +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN),
> item_param),
> +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct
> rte_flow_item_gre,
> +						  c_rsvd0_ver,
> +						  "\x10\x00\x00\x00")),
> +	},
> +	[ITEM_GRE_K_BIT] = {
> +		.name = "k_bit",
> +		.help = "key bit (K)",
> +		.next = NEXT(item_gre, NEXT_ENTRY(BOOLEAN),
> item_param),
> +		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct
> rte_flow_item_gre,
> +						  c_rsvd0_ver,
> +						  "\x20\x00\x00\x00")),
> +	},
>  	[ITEM_FUZZY] = {
>  		.name = "fuzzy",
>  		.help = "fuzzy pattern match, expect faster than default",
> @@ -2150,6 +2201,19 @@ static const struct token token_list[] = {
>  		.args = ARGS(ARGS_ENTRY_MASK_HTON(struct
> rte_flow_item_meta,
>  						  data, "\xff\xff\xff\xff")),
>  	},
> +	[ITEM_GRE_KEY] = {
> +		.name = "gre_key",
> +		.help = "match GRE key",
> +		.priv = PRIV_ITEM(GRE_KEY, sizeof(rte_be32_t)),
> +		.next = NEXT(item_gre_key),
> +		.call = parse_vc,
> +	},
> +	[ITEM_GRE_KEY_VALUE] = {
> +		.name = "value",
> +		.help = "key value",
> +		.next = NEXT(item_gre_key, NEXT_ENTRY(UNSIGNED),
> item_param),
> +		.args = ARGS(ARG_ENTRY_HTON(rte_be32_t)),
> +	},
> 
>  	/* Validate/create actions. */
>  	[ACTIONS] = {
> diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> index cb83a3ce8a..9ef1796ee1 100644
> --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst
> @@ -3804,6 +3804,10 @@ This section lists supported pattern items and
> their attributes, if any.
> 
>    - ``protocol {unsigned}``: protocol type.
> 
> +- ``gre_key``: match GRE optional key field.
> +
> +  - ``value {unsigned}``: key value.
> +
>  - ``fuzzy``: fuzzy pattern match, expect faster than default.
> 
>    - ``thresh {unsigned}``: accuracy threshold.
> --
> 2.21.0

[dpdk-dev] [PATCH v8 0/2] match on GRE's key

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

[1] https://patches.dpdk.org/patch/53432/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention
v3:
  * updated release note
  * fixed one bug
v4:
  * resend patchs in thread mode
v5:
  * report error when K is off but gre_key item present
  * removed ITEM_CRKSV, added c_bit, k_bit, s_bit in testpmd
  * document updated
v6:
  * one fix in pmd
v7:
  * addressed comments in TestPMD
v8:
  * rebased PMD patchs on v19.08-rc1
---
Xiaoyu Min (2):
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits

 doc/guides/rel_notes/release_19_08.rst |  5 ++
 drivers/net/mlx5/mlx5_flow.c           | 63 ++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 161 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v8 1/2] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 534cd9338e..626d0f9352 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1714,6 +1714,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1721,6 +1722,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v8 2/2] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
 doc/guides/rel_notes/release_19_08.rst |  5 ++
 drivers/net/mlx5/mlx5_flow.c           | 61 ++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 159 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 27d5915bed..dd3f2147b5 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -191,6 +191,11 @@ New Features
   Added telemetry mode to l3fwd-power application to report
   application level busyness, empty and full polls of rte_eth_rx_burst().
 
+* **Updated Mellanox mlx5 driver.**
+
+   Updated Mellanox mlx5 driver with new features and improvements, including:
+
+   * Added support for matching on GRE's key and C,K,S present bits.
 
 Removed Items
 -------------
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 626d0f9352..c7e034c815 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1666,6 +1666,61 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error)
+{
+	const rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+	if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+			 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Key bit must be on");
+
+	if (!mask)
+		mask = &gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1691,6 +1746,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1710,7 +1769,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 3d7fcf706e..6ccb8a7189 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -53,6 +53,7 @@
 /* Pattern MISC bits. */
 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
 
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
@@ -474,6 +475,10 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    const struct rte_flow_item *gre_item,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 9cc09e73c9..676f6e515b 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2294,6 +2294,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 	uint64_t last_item = 0;
 	uint8_t next_protocol = 0xff;
 	int actions_n = 0;
+	const struct rte_flow_item *gre_item = NULL;
 	struct rte_flow_item_tcp nic_tcp_mask = {
 		.hdr = {
 			.tcp_flags = 0xFF,
@@ -2403,8 +2404,16 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 							  next_protocol, error);
 			if (ret < 0)
 				return ret;
+			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, gre_item, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -3200,6 +3209,45 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	/* GRE K bit must be on and should already be validated */
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -3223,6 +3271,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -3243,6 +3305,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -4390,6 +4469,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 7482383806..fe171f17ec 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -428,7 +428,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

Re: [dpdk-dev] [PATCH v8 2/2] net/mlx5: match GRE's key and present bits

[Thomas Monjalon]

09/07/2019 11:02, Xiaoyu Min:
> --- a/doc/guides/rel_notes/release_19_08.rst
> +++ b/doc/guides/rel_notes/release_19_08.rst
> @@ -191,6 +191,11 @@ New Features
>    Added telemetry mode to l3fwd-power application to report
>    application level busyness, empty and full polls of rte_eth_rx_burst().
>  
> +* **Updated Mellanox mlx5 driver.**
> +
> +   Updated Mellanox mlx5 driver with new features and improvements, including:
> +
> +   * Added support for matching on GRE's key and C,K,S present bits.

Please move this entry with other mlx5 changes already in the release notes.

Re: [dpdk-dev] [PATCH v8 2/2] net/mlx5: match GRE's key and present bits

[Jack Min]

On Tue, 19-07-09, 11:54, Thomas Monjalon wrote:
> 09/07/2019 11:02, Xiaoyu Min:
> > --- a/doc/guides/rel_notes/release_19_08.rst
> > +++ b/doc/guides/rel_notes/release_19_08.rst
> > @@ -191,6 +191,11 @@ New Features
> >    Added telemetry mode to l3fwd-power application to report
> >    application level busyness, empty and full polls of rte_eth_rx_burst().
> >  
> > +* **Updated Mellanox mlx5 driver.**
> > +
> > +   Updated Mellanox mlx5 driver with new features and improvements, including:
> > +
> > +   * Added support for matching on GRE's key and C,K,S present bits.
> 
> Please move this entry with other mlx5 changes already in the release notes.
Oooops! Just did rebase automaticly...
I'll upate it.

> 
> 

[dpdk-dev] [PATCH v9 0/2] match on GRE's key

[Xiaoyu Min]

This series patchs are based on RFC [1], which enable the matching on
GRE's key field.
And enabled MLX5 device supports on this.

[1] https://patches.dpdk.org/patch/53432/

---
v2:
  * remove struct rte_flow_item_gre_key in order to comply new convention
v3:
  * updated release note
  * fixed one bug
v4:
  * resend patchs in thread mode
v5:
  * report error when K is off but gre_key item present
  * removed ITEM_CRKSV, added c_bit, k_bit, s_bit in testpmd
  * document updated
v6:
  * one fix in pmd
v7:
  * addressed comments in TestPMD
v8:
  * rebased PMD patchs on v19.08-rc1
v9:
  * fix release note
---
Xiaoyu Min (2):
  net/mlx5: support match GRE protocol on DR engine
  net/mlx5: match GRE's key and present bits

 doc/guides/rel_notes/release_19_08.rst |  1 +
 drivers/net/mlx5/mlx5_flow.c           | 63 ++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 157 insertions(+), 2 deletions(-)

-- 
2.21.0

[dpdk-dev] [PATCH v9 1/2] net/mlx5: support match GRE protocol on DR engine

[Xiaoyu Min]

DR engine support matching on GRE protocol field without MPLS supports.
So bypassing the MPLS check when DR is enabled.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
 drivers/net/mlx5/mlx5_flow.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 534cd9338e..626d0f9352 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1714,6 +1714,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
+#ifndef HAVE_MLX5DV_DR
 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT
 	if (spec && (spec->protocol & mask->protocol))
 		return rte_flow_error_set(error, ENOTSUP,
@@ -1721,6 +1722,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 					  "without MPLS support the"
 					  " specification cannot be used for"
 					  " filtering");
+#endif
 #endif
 	return 0;
 }
-- 
2.21.0

[dpdk-dev] [PATCH v9 2/2] net/mlx5: match GRE's key and present bits

[Xiaoyu Min]

support matching on the present bits (C,K,S)
as well as the optional key field.

If the rte_flow_item_gre_key is specified in pattern,
it will set K present match automatically.

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
---
 doc/guides/rel_notes/release_19_08.rst |  1 +
 drivers/net/mlx5/mlx5_flow.c           | 61 ++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow.h           |  5 ++
 drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
 drivers/net/mlx5/mlx5_prm.h            |  6 +-
 5 files changed, 155 insertions(+), 2 deletions(-)

diff --git a/doc/guides/rel_notes/release_19_08.rst b/doc/guides/rel_notes/release_19_08.rst
index 27d5915bed..ed58b463d0 100644
--- a/doc/guides/rel_notes/release_19_08.rst
+++ b/doc/guides/rel_notes/release_19_08.rst
@@ -112,6 +112,7 @@ New Features
   * Updated the packet header modification feature. Added support of TCP header
     sequence number and acknowledgment number modification.
   * Added support for match on ICMP/ICMP6 code and type.
+  * Added support for matching on GRE's key and C,K,S present bits.
 
 * **Updated Solarflare network PMD.**
 
diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c
index 626d0f9352..c7e034c815 100644
--- a/drivers/net/mlx5/mlx5_flow.c
+++ b/drivers/net/mlx5/mlx5_flow.c
@@ -1666,6 +1666,61 @@ mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
 					  " defined");
 	return 0;
 }
+/**
+ * Validate GRE Key item.
+ *
+ * @param[in] item
+ *   Item specification.
+ * @param[in] item_flags
+ *   Bit flags to mark detected items.
+ * @param[in] gre_item
+ *   Pointer to gre_item
+ * @param[out] error
+ *   Pointer to error structure.
+ *
+ * @return
+ *   0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				uint64_t item_flags,
+				const struct rte_flow_item *gre_item,
+				struct rte_flow_error *error)
+{
+	const rte_be32_t *mask = item->mask;
+	int ret = 0;
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+	const struct rte_flow_item_gre *gre_spec = gre_item->spec;
+	const struct rte_flow_item_gre *gre_mask = gre_item->mask;
+
+	if (item_flags & MLX5_FLOW_LAYER_GRE_KEY)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Multiple GRE key not support");
+	if (!(item_flags & MLX5_FLOW_LAYER_GRE))
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "No preceding GRE header");
+	if (item_flags & MLX5_FLOW_LAYER_INNER)
+		return rte_flow_error_set(error, ENOTSUP,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "GRE key following a wrong item");
+	if (!gre_mask)
+		gre_mask = &rte_flow_item_gre_mask;
+	if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) &&
+			 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000)))
+		return rte_flow_error_set(error, EINVAL,
+					  RTE_FLOW_ERROR_TYPE_ITEM, item,
+					  "Key bit must be on");
+
+	if (!mask)
+		mask = &gre_key_default_mask;
+	ret = mlx5_flow_item_acceptable
+		(item, (const uint8_t *)mask,
+		 (const uint8_t *)&gre_key_default_mask,
+		 sizeof(rte_be32_t), error);
+	return ret;
+}
 
 /**
  * Validate GRE item.
@@ -1691,6 +1746,10 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 	const struct rte_flow_item_gre *spec __rte_unused = item->spec;
 	const struct rte_flow_item_gre *mask = item->mask;
 	int ret;
+	const struct rte_flow_item_gre nic_mask = {
+		.c_rsvd0_ver = RTE_BE16(0xB000),
+		.protocol = RTE_BE16(UINT16_MAX),
+	};
 
 	if (target_protocol != 0xff && target_protocol != IPPROTO_GRE)
 		return rte_flow_error_set(error, EINVAL,
@@ -1710,7 +1769,7 @@ mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 		mask = &rte_flow_item_gre_mask;
 	ret = mlx5_flow_item_acceptable
 		(item, (const uint8_t *)mask,
-		 (const uint8_t *)&rte_flow_item_gre_mask,
+		 (const uint8_t *)&nic_mask,
 		 sizeof(struct rte_flow_item_gre), error);
 	if (ret < 0)
 		return ret;
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 3d7fcf706e..6ccb8a7189 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -53,6 +53,7 @@
 /* Pattern MISC bits. */
 #define MLX5_FLOW_LAYER_ICMP (1u << 18)
 #define MLX5_FLOW_LAYER_ICMP6 (1u << 19)
+#define MLX5_FLOW_LAYER_GRE_KEY (1u << 20)
 
 /* Outer Masks. */
 #define MLX5_FLOW_LAYER_OUTER_L3 \
@@ -474,6 +475,10 @@ int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
 				uint64_t item_flags,
 				uint8_t target_protocol,
 				struct rte_flow_error *error);
+int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
+				    uint64_t item_flags,
+				    const struct rte_flow_item *gre_item,
+				    struct rte_flow_error *error);
 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
 				 uint64_t item_flags,
 				 const struct rte_flow_item_ipv4 *acc_mask,
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 9cc09e73c9..676f6e515b 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -2294,6 +2294,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 	uint64_t last_item = 0;
 	uint8_t next_protocol = 0xff;
 	int actions_n = 0;
+	const struct rte_flow_item *gre_item = NULL;
 	struct rte_flow_item_tcp nic_tcp_mask = {
 		.hdr = {
 			.tcp_flags = 0xFF,
@@ -2403,8 +2404,16 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 							  next_protocol, error);
 			if (ret < 0)
 				return ret;
+			gre_item = items;
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			ret = mlx5_flow_validate_item_gre_key
+				(items, item_flags, gre_item, error);
+			if (ret < 0)
+				return ret;
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_VXLAN:
 			ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 							    error);
@@ -3200,6 +3209,45 @@ flow_dv_translate_item_udp(void *matcher, void *key,
 		 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
 }
 
+/**
+ * Add GRE optional Key item to matcher and to the value.
+ *
+ * @param[in, out] matcher
+ *   Flow matcher.
+ * @param[in, out] key
+ *   Flow matcher value.
+ * @param[in] item
+ *   Flow pattern to translate.
+ * @param[in] inner
+ *   Item is inner pattern.
+ */
+static void
+flow_dv_translate_item_gre_key(void *matcher, void *key,
+				   const struct rte_flow_item *item)
+{
+	const rte_be32_t *key_m = item->mask;
+	const rte_be32_t *key_v = item->spec;
+	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
+	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
+
+	if (!key_v)
+		return;
+	if (!key_m)
+		key_m = &gre_key_default_mask;
+	/* GRE K bit must be on and should already be validated */
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
+		 rte_be_to_cpu_32(*key_m) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
+		 rte_be_to_cpu_32(*key_m) & 0xFF);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
+		 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
+}
+
 /**
  * Add GRE item to matcher and to the value.
  *
@@ -3223,6 +3271,20 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 	void *headers_v;
 	void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
 	void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
+	struct {
+		union {
+			__extension__
+			struct {
+				uint16_t version:3;
+				uint16_t rsvd0:9;
+				uint16_t s_present:1;
+				uint16_t k_present:1;
+				uint16_t rsvd_bit1:1;
+				uint16_t c_present:1;
+			};
+			uint16_t value;
+		};
+	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 
 	if (inner) {
 		headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
@@ -3243,6 +3305,23 @@ flow_dv_translate_item_gre(void *matcher, void *key,
 		 rte_be_to_cpu_16(gre_m->protocol));
 	MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
 		 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
+	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
+	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
+		 gre_crks_rsvd0_ver_v.c_present &
+		 gre_crks_rsvd0_ver_m.c_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
+		 gre_crks_rsvd0_ver_v.k_present &
+		 gre_crks_rsvd0_ver_m.k_present);
+	MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
+		 gre_crks_rsvd0_ver_m.s_present);
+	MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
+		 gre_crks_rsvd0_ver_v.s_present &
+		 gre_crks_rsvd0_ver_m.s_present);
 }
 
 /**
@@ -4390,6 +4469,11 @@ flow_dv_translate(struct rte_eth_dev *dev,
 						   items, tunnel);
 			last_item = MLX5_FLOW_LAYER_GRE;
 			break;
+		case RTE_FLOW_ITEM_TYPE_GRE_KEY:
+			flow_dv_translate_item_gre_key(match_mask,
+						       match_value, items);
+			item_flags |= MLX5_FLOW_LAYER_GRE_KEY;
+			break;
 		case RTE_FLOW_ITEM_TYPE_NVGRE:
 			flow_dv_translate_item_nvgre(match_mask, match_value,
 						     items, tunnel);
diff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h
index 7482383806..fe171f17ec 100644
--- a/drivers/net/mlx5/mlx5_prm.h
+++ b/drivers/net/mlx5/mlx5_prm.h
@@ -428,7 +428,11 @@ typedef uint8_t u8;
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 
 struct mlx5_ifc_fte_match_set_misc_bits {
-	u8 reserved_at_0[0x8];
+	u8 gre_c_present[0x1];
+	u8 reserved_at_1[0x1];
+	u8 gre_k_present[0x1];
+	u8 gre_s_present[0x1];
+	u8 source_vhci_port[0x4];
 	u8 source_sqn[0x18];
 	u8 reserved_at_20[0x10];
 	u8 source_port[0x10];
-- 
2.21.0

Re: [dpdk-dev] [PATCH v9 0/2] match on GRE's key

[Raslan Darawsheh]

Hi,
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Xiaoyu Min
> Sent: Tuesday, July 9, 2019 1:59 PM
> To: Adrien Mazarguil <adrien.mazarguil@6wind.com>; Ori Kam
> <orika@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>;
> Thomas Monjalon <thomas@monjalon.net>
> Cc: dev@dpdk.org
> Subject: [dpdk-dev] [PATCH v9 0/2] match on GRE's key
> 
> This series patchs are based on RFC [1], which enable the matching on
> GRE's key field.
> And enabled MLX5 device supports on this.
> 
> [1]
> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> es.dpdk.org%2Fpatch%2F53432%2F&amp;data=02%7C01%7Crasland%40mell
> anox.com%7C188e1523772d48861faf08d7045c811f%7Ca652971c7d2e4d9ba6a
> 4d149256f461b%7C0%7C0%7C636982667680710408&amp;sdata=S4325%2FE7
> H%2FINoACgqcotSAu2ZskTnAhU07Xq9%2FL4WSU%3D&amp;reserved=0
> 
> ---
> v2:
>   * remove struct rte_flow_item_gre_key in order to comply new convention
> v3:
>   * updated release note
>   * fixed one bug
> v4:
>   * resend patchs in thread mode
> v5:
>   * report error when K is off but gre_key item present
>   * removed ITEM_CRKSV, added c_bit, k_bit, s_bit in testpmd
>   * document updated
> v6:
>   * one fix in pmd
> v7:
>   * addressed comments in TestPMD
> v8:
>   * rebased PMD patchs on v19.08-rc1
> v9:
>   * fix release note
> ---
> Xiaoyu Min (2):
>   net/mlx5: support match GRE protocol on DR engine
>   net/mlx5: match GRE's key and present bits
> 
>  doc/guides/rel_notes/release_19_08.rst |  1 +
>  drivers/net/mlx5/mlx5_flow.c           | 63 ++++++++++++++++++-
>  drivers/net/mlx5/mlx5_flow.h           |  5 ++
>  drivers/net/mlx5/mlx5_flow_dv.c        | 84 ++++++++++++++++++++++++++
>  drivers/net/mlx5/mlx5_prm.h            |  6 +-
>  5 files changed, 157 insertions(+), 2 deletions(-)
> 
> --
> 2.21.0

Series applied to next-net-mlx,

Kindest regards,
Raslan Darawsheh