From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 75CDBA046B for ; Fri, 26 Jul 2019 15:59:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C64EA1C486; Fri, 26 Jul 2019 15:59:05 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id 9C989F04; Fri, 26 Jul 2019 15:59:04 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jul 2019 06:59:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,311,1559545200"; d="scan'208";a="369537330" Received: from silpixa00389816.ir.intel.com ([10.237.222.12]) by fmsmga005.fm.intel.com with ESMTP; 26 Jul 2019 06:58:59 -0700 From: hgovindh To: Marko Kovacevic , Ori Kam , Bruce Richardson , Pablo de Lara , Radu Nicolau , Akhil Goyal , Tomasz Kantecki Cc: dev@dpdk.org, drc@linux.vnet.ibm.com, ruifeng.wang@arm.com, hgovindh , maciej.czekaj@caviumnetworks.com, stable@dpdk.org Date: Fri, 26 Jul 2019 14:58:58 +0100 Message-Id: <20190726135858.55792-1-hariprasad.govindharajan@intel.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190726132758.55217-1-hariprasad.govindharajan@intel.com> References: <20190726132758.55217-1-hariprasad.govindharajan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v4] examples/l3fwd: fix unaligned memory access X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Fix unaligned memory access when reading IPv6 header which leads to segmentation fault by changing aligned memory read to unaligned memory read. Bugzilla ID: 279 Fixes: 64d3955de1de ("examples/l3fwd: fix ARM build") Cc: maciej.czekaj@caviumnetworks.com Cc: stable@dpdk.org Signed-off-by: hgovindh --- V2: Added functions which will do unaligned load based on the underlying architecture V3: Removed functions added in V2 and replaced them with if macros which will branch based on the underlying architecture. As per my understanding since the unaligned load affects only Intel arch, I added that function branch and left the original code for other arc. Can someone with ARM and PowerPC arch, could you please validate this patch and let me know? --- examples/l3fwd/l3fwd_em.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/examples/l3fwd/l3fwd_em.c b/examples/l3fwd/l3fwd_em.c index 5f499e005..ad6fe76e8 100644 --- a/examples/l3fwd/l3fwd_em.c +++ b/examples/l3fwd/l3fwd_em.c @@ -287,8 +287,11 @@ em_get_ipv6_dst_port(void *ipv6_hdr, uint16_t portid, void *lookup_struct) * Get part of 5 tuple: dst IP address lower 96 bits * and src IP address higher 32 bits. */ +#if defined RTE_ARCH_X86 + key.xmm[1] = _mm_loadu_si128(data1); +#else key.xmm[1] = *(xmm_t *)data1; - +#endif /* * Get part of 5 tuple: dst port and src port * and dst IP address higher 32 bits. -- 2.22.0