From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E6474A00E6 for ; Mon, 5 Aug 2019 07:41:05 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BDCAA1BE45; Mon, 5 Aug 2019 07:41:05 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 4AC751BE3B for ; Mon, 5 Aug 2019 07:41:04 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x755f3bG006967 for ; Sun, 4 Aug 2019 22:41:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=FgmWnntF8lbD1iQaOBAGDeFkTnATntpfhbIpF3cyuPE=; b=PZuI2Ldve/4ys8lAenQ9Qm+goYI30KW5CvlwIelgCxj7SUzSALsNj5ZHA7qeTdSrA3j0 X+b2r+vNd8GmNgPEAGWDow88INm0kA/sLzqHNPsEwjHCiWMYMXL7nOZcXk/mk7K5S6dD 8oU5wqEYLA6RWsKWgviV5qhkuiA7DHRmKW3SagipximtyozfDnV4SajXpCsIkdwBD8Ym aYsaLGis35gimvaXd8zh/Zs+sNqn4TlBsdx2Mgka6WzN/y9JyESMxzBJjZOs124hwezY QWirtWygzr6eaWE7d8zytDaJnLfv/OTNn63ouMZufQaaJvCYhSDSMKhZIlcrDCZxtnmj og== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 2u59skn29v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 04 Aug 2019 22:41:03 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 4 Aug 2019 22:40:56 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 4 Aug 2019 22:40:56 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id C09A63F7040; Sun, 4 Aug 2019 22:40:54 -0700 (PDT) From: Nithin Dabilpuram To: Jerin Jacob , Nithin Dabilpuram , Vamsi Attunuru , "Kiran Kumar K" CC: Date: Mon, 5 Aug 2019 11:10:51 +0530 Message-ID: <20190805054052.31519-1-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-05_02:2019-07-31,2019-08-05 signatures=0 Subject: [dpdk-dev] [PATCH] net/octeontx2: add 96xx A1 silicon revision support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update workaround changes for erratas that are fixed on 96xx A1. This patch also enables cq drop for all the passes for maintaining performance along with updating a default Rx ring size in dev_info. Signed-off-by: Nithin Dabilpuram --- drivers/common/octeontx2/otx2_dev.h | 16 ++++++++++++++++ drivers/net/octeontx2/otx2_ethdev.c | 29 +++++++++++++++++------------ drivers/net/octeontx2/otx2_ethdev.h | 7 +++++-- drivers/net/octeontx2/otx2_ethdev_ops.c | 4 ++++ drivers/net/octeontx2/otx2_flow_ctrl.c | 2 +- 5 files changed, 43 insertions(+), 15 deletions(-) diff --git a/drivers/common/octeontx2/otx2_dev.h b/drivers/common/octeontx2/otx2_dev.h index 53a3669..5fd05fa 100644 --- a/drivers/common/octeontx2/otx2_dev.h +++ b/drivers/common/octeontx2/otx2_dev.h @@ -26,6 +26,22 @@ #define otx2_dev_is_Ax(dev) \ ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0)) +#define otx2_dev_is_95xx_A0(dev) \ + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \ + (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) && \ + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1)) +#define otx2_dev_is_95xx_Ax(dev) \ + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \ + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x1)) + +#define otx2_dev_is_96xx_A0(dev) \ + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \ + (RVU_PCI_REV_MINOR(otx2_dev_revid(dev)) == 0x0) && \ + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0)) +#define otx2_dev_is_96xx_Ax(dev) \ + ((RVU_PCI_REV_MAJOR(otx2_dev_revid(dev)) == 0x0) && \ + (RVU_PCI_REV_MIDR_ID(otx2_dev_revid(dev)) == 0x0)) + struct otx2_dev; /* Link status callback */ diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 3fb7bd9..f151527 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -266,26 +266,31 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev, aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT); aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR); - /* TX pause frames enable flowctrl on RX side */ - if (dev->fc_info.tx_pause) { - /* Single bpid is allocated for all rx channels for now */ - aq->cq.bpid = dev->fc_info.bpid[0]; - aq->cq.bp = NIX_CQ_BP_LEVEL; - aq->cq.bp_ena = 1; - } - /* Many to one reduction */ aq->cq.qint_idx = qid % dev->qints; /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */ aq->cq.cint_idx = qid; if (otx2_ethdev_fixup_is_limit_cq_full(dev)) { + const float rx_cq_skid = NIX_CQ_FULL_ERRATA_SKID; uint16_t min_rx_drop; - const float rx_cq_skid = 1024 * 256; min_rx_drop = ceil(rx_cq_skid / (float)cq_size); aq->cq.drop = min_rx_drop; aq->cq.drop_ena = 1; + rxq->cq_drop = min_rx_drop; + } else { + rxq->cq_drop = NIX_CQ_THRESH_LEVEL; + aq->cq.drop = rxq->cq_drop; + aq->cq.drop_ena = 1; + } + + /* TX pause frames enable flowctrl on RX side */ + if (dev->fc_info.tx_pause) { + /* Single bpid is allocated for all rx channels for now */ + aq->cq.bpid = dev->fc_info.bpid[0]; + aq->cq.bp = rxq->cq_drop; + aq->cq.bp_ena = 1; } rc = otx2_mbox_process(mbox); @@ -324,8 +329,7 @@ nix_cq_rq_init(struct rte_eth_dev *eth_dev, struct otx2_eth_dev *dev, /* Many to one reduction */ aq->rq.qint_idx = qid % dev->qints; - if (otx2_ethdev_fixup_is_limit_cq_full(dev)) - aq->rq.xqe_drop_ena = 1; + aq->rq.xqe_drop_ena = 1; rc = otx2_mbox_process(mbox); if (rc) { @@ -1826,7 +1830,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev) dev->tx_offload_capa = nix_get_tx_offload_capa(dev); dev->rx_offload_capa = nix_get_rx_offload_capa(dev); - if (otx2_dev_is_Ax(dev)) { + if (otx2_dev_is_96xx_A0(dev) || + otx2_dev_is_95xx_Ax(dev)) { dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q; dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL; } diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 720386f..6c3505c 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -80,6 +80,7 @@ #define NIX_CQ_ALIGN 512 #define NIX_SQB_LOWER_THRESH 90 #define LMT_SLOT_MASK 0x7f +#define NIX_RX_DEFAULT_RING_SZ 4096 /* If PTP is enabled additional SEND MEM DESC is required which * takes 2 words, hence max 7 iova address are possible @@ -94,8 +95,9 @@ ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \ + NIX_TX_NB_SEG_MAX) -/* Apply BP when CQ is 75% full */ -#define NIX_CQ_BP_LEVEL (25 * 256 / 100) +/* Apply BP/DROP when CQ is 95% full */ +#define NIX_CQ_THRESH_LEVEL (5 * 256 / 100) +#define NIX_CQ_FULL_ERRATA_SKID (1024ull * 256) #define CQ_OP_STAT_OP_ERR 63 #define CQ_OP_STAT_CQ_ERR 46 @@ -344,6 +346,7 @@ struct otx2_eth_rxq { enum nix_q_size_e qsize; struct rte_eth_dev *eth_dev; struct otx2_eth_qconf qconf; + uint16_t cq_drop; } __rte_cache_aligned; static inline struct otx2_eth_dev * diff --git a/drivers/net/octeontx2/otx2_ethdev_ops.c b/drivers/net/octeontx2/otx2_ethdev_ops.c index 5a16a3c..8d0a3dc 100644 --- a/drivers/net/octeontx2/otx2_ethdev_ops.c +++ b/drivers/net/octeontx2/otx2_ethdev_ops.c @@ -431,6 +431,10 @@ otx2_nix_info_get(struct rte_eth_dev *eth_dev, struct rte_eth_dev_info *devinfo) .offloads = 0, }; + devinfo->default_rxportconf = (struct rte_eth_dev_portconf) { + .ring_size = NIX_RX_DEFAULT_RING_SZ, + }; + devinfo->rx_desc_lim = (struct rte_eth_desc_lim) { .nb_max = UINT16_MAX, .nb_min = NIX_RX_MIN_DESC, diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c index ae56352..419ad97 100644 --- a/drivers/net/octeontx2/otx2_flow_ctrl.c +++ b/drivers/net/octeontx2/otx2_flow_ctrl.c @@ -110,7 +110,7 @@ otx2_nix_cq_bp_cfg(struct rte_eth_dev *eth_dev, bool enb) if (enb) { aq->cq.bpid = fc->bpid[0]; aq->cq_mask.bpid = ~(aq->cq_mask.bpid); - aq->cq.bp = NIX_CQ_BP_LEVEL; + aq->cq.bp = rxq->cq_drop; aq->cq_mask.bp = ~(aq->cq_mask.bp); } -- 2.8.4