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Mon, 26 Aug 2019 12:49:44 +0000 Received: from MN2PR18MB2797.namprd18.prod.outlook.com ([fe80::28ff:b1d2:ef69:5e84]) by MN2PR18MB2797.namprd18.prod.outlook.com ([fe80::28ff:b1d2:ef69:5e84%5]) with mapi id 15.20.2199.021; Mon, 26 Aug 2019 12:49:44 +0000 From: Nagadheeraj Rottela To: "akhil.goyal@nxp.com" , "pablo.de.lara.guarch@intel.com" , "mattias.ronnblom@ericsson.com" CC: "dev@dpdk.org" , Srikanth Jampala , Nagadheeraj Rottela Thread-Topic: [PATCH v4 08/11] crypto/nitrox: add burst enqueue and dequeue operations Thread-Index: AQHVXAy7liq4f1zWtUyiDfU6VcRaxg== Date: Mon, 26 Aug 2019 12:49:43 +0000 Message-ID: <20190826124836.21187-9-rnagadheeraj@marvell.com> References: <4b0fc70c-768a-a474-ace4-b69513412cae@ericsson.com> <20190826124836.21187-1-rnagadheeraj@marvell.com> In-Reply-To: <20190826124836.21187-1-rnagadheeraj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::28) To MN2PR18MB2797.namprd18.prod.outlook.com (2603:10b6:208:a0::16) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.13.6 x-originating-ip: [115.113.156.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 1c2b3d91-6756-4e7d-065c-08d72a23ddd4 x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2512; H:MN2PR18MB2797.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: HlId7ytsnmW3EfGbyff0OdIzXq7jS9rk7AjTO6Zo4Y1CTDLb/YwZ19DjrKu4D0qV4p8vkeN02cpmDlboACq+FbrooVanHIXuPbDoZy5pJNGtU2tDC2vJGmGBUrRqoWPVcgOg3So11TJ/2Yr7nUgniDtkn6FrXhY0S5KPXa87uTQiNuxHduZYQ2M0kfDufKcxQztNEQaG0C916svrz0bg15PMimTflXgH/SLLmGqEvr2dvRF3hVPKG1LgjjK5Idz3UZxp6+T9LDRLtqfiC87TnpXORVawSvhcts03BIyGGGhR6hofUJKo67SStGLlcAuVkINTY08tYUptnK67V7ulV2PrQuHGDxH9uV5qTOjsvvpyCpudjtqZyLV3gqPZ8k5dOwFzrhCasLPmbzREmejD/5jukef/0BCaJUdZkThzorE= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 1c2b3d91-6756-4e7d-065c-08d72a23ddd4 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2019 12:49:43.9500 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: QFF6zT5arUqeNiELOHQ6/xl86WGcMnSvvxV5naKFDEOuyDiq9LFoRF6LFfgAgk2lQOGBiuUwU3veS9ylJFB51W6UTg7n9lcP2NrxhLCK1LM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2512 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-26_07:2019-08-26,2019-08-26 signatures=0 Subject: [dpdk-dev] [PATCH v4 08/11] crypto/nitrox: add burst enqueue and dequeue operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add burst enqueue and dequeue operations along with interface for symmetric request manager. Signed-off-by: Nagadheeraj Rottela --- drivers/crypto/nitrox/nitrox_qp.h | 60 +++++++++++ drivers/crypto/nitrox/nitrox_sym.c | 128 +++++++++++++++++++++- drivers/crypto/nitrox/nitrox_sym_reqmgr.c | 174 ++++++++++++++++++++++++++= ++++ drivers/crypto/nitrox/nitrox_sym_reqmgr.h | 10 ++ 4 files changed, 370 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/nitr= ox_qp.h index 0244c4dbf..e8c564cb1 100644 --- a/drivers/crypto/nitrox/nitrox_qp.h +++ b/drivers/crypto/nitrox/nitrox_qp.h @@ -34,12 +34,72 @@ struct nitrox_qp { rte_atomic16_t pending_count; }; =20 +static inline uint16_t +nitrox_qp_free_count(struct nitrox_qp *qp) +{ + uint16_t pending_count =3D rte_atomic16_read(&qp->pending_count); + + RTE_ASSERT(qp->count >=3D pending_count); + return (qp->count - pending_count); +} + static inline bool nitrox_qp_is_empty(struct nitrox_qp *qp) { return (rte_atomic16_read(&qp->pending_count) =3D=3D 0); } =20 +static inline uint16_t +nitrox_qp_used_count(struct nitrox_qp *qp) +{ + return rte_atomic16_read(&qp->pending_count); +} + +static inline struct nitrox_softreq * +nitrox_qp_get_softreq(struct nitrox_qp *qp) +{ + uint32_t tail =3D qp->tail % qp->count; + + return qp->ridq[tail].sr; +} + +static inline void +nitrox_ring_dbell(struct nitrox_qp *qp, uint16_t cnt) +{ + struct command_queue *cmdq =3D &qp->cmdq; + + if (!cnt) + return; + + rte_write64(cnt, cmdq->dbell_csr_addr); +} + +static inline void +nitrox_qp_enqueue(struct nitrox_qp *qp, void *instr, struct nitrox_softreq= *sr) +{ + uint32_t head =3D qp->head % qp->count; + + qp->head++; + memcpy(&qp->cmdq.ring[head * qp->cmdq.instr_size], + instr, qp->cmdq.instr_size); + qp->ridq[head].sr =3D sr; + rte_wmb(); + rte_atomic16_inc(&qp->pending_count); + rte_wmb(); +} + +static inline void +nitrox_qp_dequeue(struct nitrox_qp *qp) +{ + uint32_t tail =3D qp->tail % qp->count; + + qp->tail++; + qp->ridq[tail].sr =3D NULL; + rte_wmb(); + rte_atomic16_dec(&qp->pending_count); + rte_wmb(); +} + int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name, uint32_t nb_descriptors, uint8_t inst_size, int socket_id); diff --git a/drivers/crypto/nitrox/nitrox_sym.c b/drivers/crypto/nitrox/nit= rox_sym.c index 34c62b02e..2056e1aae 100644 --- a/drivers/crypto/nitrox/nitrox_sym.c +++ b/drivers/crypto/nitrox/nitrox_sym.c @@ -521,6 +521,130 @@ nitrox_sym_dev_sess_clear(struct rte_cryptodev *cdev, rte_mempool_put(sess_mp, ctx); } =20 +static struct nitrox_crypto_ctx * +get_crypto_ctx(struct rte_crypto_op *op) +{ + if (op->sess_type =3D=3D RTE_CRYPTO_OP_WITH_SESSION) { + if (likely(op->sym->session)) + return get_sym_session_private_data(op->sym->session, + nitrox_sym_drv_id); + + } + + return NULL; +} + +static int +nitrox_enq_single_op(struct nitrox_qp *qp, struct rte_crypto_op *op) +{ + struct nitrox_crypto_ctx *ctx; + struct nitrox_softreq *sr; + int err; + + op->status =3D RTE_CRYPTO_OP_STATUS_NOT_PROCESSED; + + ctx =3D get_crypto_ctx(op); + if (unlikely(!ctx)) { + op->status =3D RTE_CRYPTO_OP_STATUS_INVALID_SESSION; + return -EINVAL; + } + + if (unlikely(rte_mempool_get(qp->sr_mp, (void **)&sr))) + return -ENOMEM; + + err =3D nitrox_process_se_req(qp->qno, op, ctx, sr); + if (unlikely(err)) { + rte_mempool_put(qp->sr_mp, sr); + op->status =3D RTE_CRYPTO_OP_STATUS_ERROR; + return err; + } + + nitrox_qp_enqueue(qp, nitrox_sym_instr_addr(sr), sr); + return 0; +} + +static uint16_t +nitrox_sym_dev_enq_burst(void *queue_pair, struct rte_crypto_op **ops, + uint16_t nb_ops) +{ + struct nitrox_qp *qp =3D queue_pair; + uint16_t free_slots =3D 0; + uint16_t cnt =3D 0; + bool err =3D false; + + free_slots =3D nitrox_qp_free_count(qp); + if (nb_ops > free_slots) + nb_ops =3D free_slots; + + for (cnt =3D 0; cnt < nb_ops; cnt++) { + if (unlikely(nitrox_enq_single_op(qp, ops[cnt]))) { + err =3D true; + break; + } + } + + nitrox_ring_dbell(qp, cnt); + qp->stats.enqueued_count +=3D cnt; + if (unlikely(err)) + qp->stats.enqueue_err_count++; + + return cnt; +} + +static int +nitrox_deq_single_op(struct nitrox_qp *qp, struct rte_crypto_op **op_ptr) +{ + struct nitrox_softreq *sr; + int ret; + struct rte_crypto_op *op; + + sr =3D nitrox_qp_get_softreq(qp); + if (unlikely(!sr)) { + NITROX_LOG(ERR, "Invalid softreq\n"); + return -EINVAL; + } + + ret =3D nitrox_check_se_req(sr, op_ptr); + if (ret < 0) + return -EAGAIN; + + op =3D *op_ptr; + nitrox_qp_dequeue(qp); + rte_mempool_put(qp->sr_mp, sr); + if (!ret) { + op->status =3D RTE_CRYPTO_OP_STATUS_SUCCESS; + qp->stats.dequeued_count++; + + return 0; + } + + if (ret =3D=3D MC_MAC_MISMATCH_ERR_CODE) + op->status =3D RTE_CRYPTO_OP_STATUS_AUTH_FAILED; + else + op->status =3D RTE_CRYPTO_OP_STATUS_ERROR; + qp->stats.dequeue_err_count++; + + return 0; +} + +static uint16_t +nitrox_sym_dev_deq_burst(void *queue_pair, struct rte_crypto_op **ops, + uint16_t nb_ops) +{ + struct nitrox_qp *qp =3D queue_pair; + uint16_t filled_slots =3D nitrox_qp_used_count(qp); + int cnt =3D 0; + + if (nb_ops > filled_slots) + nb_ops =3D filled_slots; + + for (cnt =3D 0; cnt < nb_ops; cnt++) + if (nitrox_deq_single_op(qp, &ops[cnt])) + break; + + return cnt; +} + static struct rte_cryptodev_ops nitrox_cryptodev_ops =3D { .dev_configure =3D nitrox_sym_dev_config, .dev_start =3D nitrox_sym_dev_start, @@ -565,8 +689,8 @@ nitrox_sym_pmd_create(struct nitrox_device *ndev) ndev->rte_sym_dev.name =3D cdev->data->name; cdev->driver_id =3D nitrox_sym_drv_id; cdev->dev_ops =3D &nitrox_cryptodev_ops; - cdev->enqueue_burst =3D NULL; - cdev->dequeue_burst =3D NULL; + cdev->enqueue_burst =3D nitrox_sym_dev_enq_burst; + cdev->dequeue_burst =3D nitrox_sym_dev_deq_burst; cdev->feature_flags =3D RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING | diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c b/drivers/crypto/nit= rox/nitrox_sym_reqmgr.c index 42d67317c..a37b754f2 100644 --- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.c +++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.c @@ -4,12 +4,113 @@ =20 #include #include +#include #include =20 #include "nitrox_sym_reqmgr.h" #include "nitrox_logs.h" =20 +#define PENDING_SIG 0xFFFFFFFFFFFFFFFFUL +#define CMD_TIMEOUT 2 + +union pkt_instr_hdr { + uint64_t value; + struct { +#if RTE_BYTE_ORDER =3D=3D RTE_BIG_ENDIAN + uint64_t raz_48_63 : 16; + uint64_t g : 1; + uint64_t gsz : 7; + uint64_t ihi : 1; + uint64_t ssz : 7; + uint64_t raz_30_31 : 2; + uint64_t fsz : 6; + uint64_t raz_16_23 : 8; + uint64_t tlen : 16; +#else + uint64_t tlen : 16; + uint64_t raz_16_23 : 8; + uint64_t fsz : 6; + uint64_t raz_30_31 : 2; + uint64_t ssz : 7; + uint64_t ihi : 1; + uint64_t gsz : 7; + uint64_t g : 1; + uint64_t raz_48_63 : 16; +#endif + } s; +}; + +union pkt_hdr { + uint64_t value[2]; + struct { +#if RTE_BYTE_ORDER =3D=3D RTE_BIG_ENDIAN + uint64_t opcode : 8; + uint64_t arg : 8; + uint64_t ctxc : 2; + uint64_t unca : 1; + uint64_t raz_44 : 1; + uint64_t info : 3; + uint64_t destport : 9; + uint64_t unc : 8; + uint64_t raz_19_23 : 5; + uint64_t grp : 3; + uint64_t raz_15 : 1; + uint64_t ctxl : 7; + uint64_t uddl : 8; +#else + uint64_t uddl : 8; + uint64_t ctxl : 7; + uint64_t raz_15 : 1; + uint64_t grp : 3; + uint64_t raz_19_23 : 5; + uint64_t unc : 8; + uint64_t destport : 9; + uint64_t info : 3; + uint64_t raz_44 : 1; + uint64_t unca : 1; + uint64_t ctxc : 2; + uint64_t arg : 8; + uint64_t opcode : 8; +#endif + uint64_t ctxp; + } s; +}; + +union slc_store_info { + uint64_t value[2]; + struct { +#if RTE_BYTE_ORDER =3D=3D RTE_BIG_ENDIAN + uint64_t raz_39_63 : 25; + uint64_t ssz : 7; + uint64_t raz_0_31 : 32; +#else + uint64_t raz_0_31 : 32; + uint64_t ssz : 7; + uint64_t raz_39_63 : 25; +#endif + uint64_t rptr; + } s; +}; + +struct nps_pkt_instr { + uint64_t dptr0; + union pkt_instr_hdr ih; + union pkt_hdr irh; + union slc_store_info slc; + uint64_t fdata[2]; +}; + +struct resp_hdr { + uint64_t orh; + uint64_t completion; +}; + struct nitrox_softreq { + struct nitrox_crypto_ctx *ctx; + struct rte_crypto_op *op; + struct nps_pkt_instr instr; + struct resp_hdr resp; + uint64_t timeout; rte_iova_t iova; }; =20 @@ -20,6 +121,79 @@ softreq_init(struct nitrox_softreq *sr, rte_iova_t iova= ) sr->iova =3D iova; } =20 +static int +process_cipher_auth_data(struct nitrox_softreq *sr) +{ + RTE_SET_USED(sr); + return 0; +} + +static int +process_softreq(struct nitrox_softreq *sr) +{ + struct nitrox_crypto_ctx *ctx =3D sr->ctx; + int err =3D 0; + + switch (ctx->nitrox_chain) { + case NITROX_CHAIN_CIPHER_AUTH: + case NITROX_CHAIN_AUTH_CIPHER: + err =3D process_cipher_auth_data(sr); + break; + default: + err =3D -EINVAL; + break; + } + + return err; +} + +int +nitrox_process_se_req(uint16_t qno, struct rte_crypto_op *op, + struct nitrox_crypto_ctx *ctx, + struct nitrox_softreq *sr) +{ + RTE_SET_USED(qno); + softreq_init(sr, sr->iova); + sr->ctx =3D ctx; + sr->op =3D op; + process_softreq(sr); + sr->timeout =3D rte_get_timer_cycles() + CMD_TIMEOUT * rte_get_timer_hz()= ; + return 0; +} + +int +nitrox_check_se_req(struct nitrox_softreq *sr, struct rte_crypto_op **op) +{ + uint64_t cc; + uint64_t orh; + int err; + + rte_rmb(); + cc =3D *(volatile uint64_t *)(&sr->resp.completion); + orh =3D *(volatile uint64_t *)(&sr->resp.orh); + if (cc !=3D PENDING_SIG) + err =3D 0; + else if ((orh !=3D PENDING_SIG) && (orh & 0xff)) + err =3D orh & 0xff; + else if (rte_get_timer_cycles() >=3D sr->timeout) + err =3D 0xff; + else + return -EAGAIN; + + if (unlikely(err)) + NITROX_LOG(ERR, "Request err 0x%x, orh 0x%"PRIx64"\n", err, + sr->resp.orh); + + *op =3D sr->op; + return err; +} + +void * +nitrox_sym_instr_addr(struct nitrox_softreq *sr) +{ + return &sr->instr; +} + static void req_pool_obj_init(__rte_unused struct rte_mempool *mp, __rte_unused void *opaque, void *obj, diff --git a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h b/drivers/crypto/nit= rox/nitrox_sym_reqmgr.h index 5953c958c..fa2637bdb 100644 --- a/drivers/crypto/nitrox/nitrox_sym_reqmgr.h +++ b/drivers/crypto/nitrox/nitrox_sym_reqmgr.h @@ -5,6 +5,16 @@ #ifndef _NITROX_SYM_REQMGR_H_ #define _NITROX_SYM_REQMGR_H_ =20 +#include "nitrox_sym_ctx.h" + +struct nitrox_qp; +struct nitrox_softreq; + +int nitrox_process_se_req(uint16_t qno, struct rte_crypto_op *op, + struct nitrox_crypto_ctx *ctx, + struct nitrox_softreq *sr); +int nitrox_check_se_req(struct nitrox_softreq *sr, struct rte_crypto_op **= op); +void *nitrox_sym_instr_addr(struct nitrox_softreq *sr); struct rte_mempool *nitrox_sym_req_pool_create(struct rte_cryptodev *cdev, uint32_t nobjs, uint16_t qp_id, int socket_id); --=20 2.13.6