From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 05061A0613 for ; Thu, 26 Sep 2019 07:35:16 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5C6162BEA; Thu, 26 Sep 2019 07:35:15 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by dpdk.org (Postfix) with ESMTP id 3B8D02BE6 for ; Thu, 26 Sep 2019 07:35:13 +0200 (CEST) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Sep 2019 22:35:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,550,1559545200"; d="scan'208";a="201502858" Received: from dpdk-virtio-tbie-2.sh.intel.com (HELO ___) ([10.67.104.73]) by orsmga002.jf.intel.com with ESMTP; 25 Sep 2019 22:35:10 -0700 Date: Thu, 26 Sep 2019 13:32:23 +0800 From: Tiwei Bie To: Marvin Liu Cc: maxime.coquelin@redhat.com, zhihong.wang@intel.com, stephen@networkplumber.org, gavin.hu@arm.com, dev@dpdk.org Message-ID: <20190926053221.GA8458@___> References: <20190919163643.24130-2-yong.liu@intel.com> <20190925171329.63734-1-yong.liu@intel.com> <20190925171329.63734-14-yong.liu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20190925171329.63734-14-yong.liu@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [PATCH v3 13/15] vhost: cache address translation result X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Thu, Sep 26, 2019 at 01:13:27AM +0800, Marvin Liu wrote: > Cache address translation result and use it in next translation. Due > to limited regions are supported, buffers are most likely in same > region when doing data transmission. > > Signed-off-by: Marvin Liu > > diff --git a/lib/librte_vhost/rte_vhost.h b/lib/librte_vhost/rte_vhost.h > index 7fb172912..d90235cd6 100644 > --- a/lib/librte_vhost/rte_vhost.h > +++ b/lib/librte_vhost/rte_vhost.h > @@ -91,10 +91,18 @@ struct rte_vhost_mem_region { > int fd; > }; > > +struct rte_vhost_mem_region_cache { > + uint64_t guest_phys_addr; > + uint64_t guest_phys_addr_end; > + int64_t host_user_addr_offset; > + uint64_t size; > +}; > + > /** > * Memory structure includes region and mapping information. > */ > struct rte_vhost_memory { > + struct rte_vhost_mem_region_cache cache_region; This breaks ABI. > uint32_t nregions; > struct rte_vhost_mem_region regions[]; > }; > @@ -232,11 +240,30 @@ rte_vhost_va_from_guest_pa(struct rte_vhost_memory *mem, > struct rte_vhost_mem_region *r; > uint32_t i; > > + struct rte_vhost_mem_region_cache *r_cache; > + /* check with cached region */ > + r_cache = &mem->cache_region; > + if (likely(gpa >= r_cache->guest_phys_addr && gpa < > + r_cache->guest_phys_addr_end)) { > + if (unlikely(*len > r_cache->guest_phys_addr_end - gpa)) > + *len = r_cache->guest_phys_addr_end - gpa; > + > + return gpa - r_cache->host_user_addr_offset; > + } Does this help a lot in performance? We can implement this caching for builtin backend first. > + > + > for (i = 0; i < mem->nregions; i++) { > r = &mem->regions[i]; > if (gpa >= r->guest_phys_addr && > gpa < r->guest_phys_addr + r->size) { > > + r_cache->guest_phys_addr = r->guest_phys_addr; > + r_cache->guest_phys_addr_end = r->guest_phys_addr + > + r->size; > + r_cache->size = r->size; > + r_cache->host_user_addr_offset = r->guest_phys_addr - > + r->host_user_addr; > + > if (unlikely(*len > r->guest_phys_addr + r->size - gpa)) > *len = r->guest_phys_addr + r->size - gpa; > > -- > 2.17.1 >