From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D4BCA2EDB for ; Mon, 30 Sep 2019 04:50:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6BBFE7CBC; Mon, 30 Sep 2019 04:50:09 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 0D6EC37B0 for ; Mon, 30 Sep 2019 04:50:03 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8U2j9hC026761; Sun, 29 Sep 2019 19:50:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=QItPuqQMJkd6C+v2G0ll/TZ+Ffb99RSH/zgHNxS46jo=; b=D7EaYowGf9SXmZn2LmPiCGPTh+OI6LCZjB6Xnt9ZLEsVJz1lKmOpdsXXZTtUXqIvcaVA do14RBVEhjOyiDe/DQyqjveYVs8ogoh47oiGgv0BewAqFvK7XqPakbP6YnRnJWEeZcyp xbi/653/2dCGO4grcaZe6zSdS2AZjtW5pwkDXPWK/dk+x5RS5s7M3bWVbVdO6gglWFOZ Xm2ldNJznjwtey3aKw2VdheYnx3KDBcBERUboqHITcamzKNMuEcwJbGKc414BptsQeK8 3J1Pz3LYD64JCg71yrBnv1vl6bGKJ6m3C1ZriC+WMbEkS2dEJfls8DBDQR29QILGHL8m XA== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 2va4vrw0p4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sun, 29 Sep 2019 19:50:02 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Sun, 29 Sep 2019 19:50:00 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Sun, 29 Sep 2019 19:50:00 -0700 Received: from irv1user08.caveonetworks.com (unknown [10.104.116.105]) by maili.marvell.com (Postfix) with ESMTP id 1CFB93F7040; Sun, 29 Sep 2019 19:49:59 -0700 (PDT) Received: (from rmody@localhost) by irv1user08.caveonetworks.com (8.14.4/8.14.4/Submit) id x8U2nxYT022284; Sun, 29 Sep 2019 19:49:59 -0700 X-Authentication-Warning: irv1user08.caveonetworks.com: rmody set sender to rmody@marvell.com using -f From: Rasesh Mody To: , , CC: Rasesh Mody , Date: Sun, 29 Sep 2019 19:49:17 -0700 Message-ID: <20190930024921.21818-6-rmody@marvell.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190930024921.21818-1-rmody@marvell.com> References: <20190930024921.21818-1-rmody@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-09-30_01:2019-09-25,2019-09-30 signatures=0 Subject: [dpdk-dev] [PATCH 5/9] net/qede/base: update rt defs NVM cfg and mcp code X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Update and add runtime array offsets (rt defs), non-volatile memory configuration options (nvm cfg) and management co-processor (mcp) shared code in preparation to update the firmware to version 8.40.25.0. Signed-off-by: Rasesh Mody --- drivers/net/qede/base/bcm_osal.h | 5 +- drivers/net/qede/base/ecore_rt_defs.h | 870 +++++++++++------------- drivers/net/qede/base/mcp_public.h | 59 +- drivers/net/qede/base/nvm_cfg.h | 909 +++++++++++++++++++++++++- 4 files changed, 1351 insertions(+), 492 deletions(-) diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index 51edc4151..0f09557cf 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -148,8 +148,8 @@ void osal_dma_free_mem(struct ecore_dev *edev, dma_addr_t phys); ((u8 *)(uintptr_t)(_p_hwfn->doorbells) + \ (_db_addr)), (u32)_val) -#define DIRECT_REG_WR64(hwfn, addr, value) nothing -#define DIRECT_REG_RD64(hwfn, addr) 0 +#define DIRECT_REG_RD64(hwfn, addr) rte_read64(addr) +#define DIRECT_REG_WR64(hwfn, addr, value) rte_write64((value), (addr)) /* Mutexes */ @@ -455,6 +455,7 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length); #define OSAL_DIV_S64(a, b) ((a) / (b)) #define OSAL_LLDP_RX_TLVS(p_hwfn, tlv_buf, tlv_size) nothing +#define OSAL_GET_EPOCH(p_hwfn) 0 #define OSAL_DBG_ALLOC_USER_DATA(p_hwfn, user_data_ptr) (0) #define OSAL_DB_REC_OCCURRED(p_hwfn) nothing diff --git a/drivers/net/qede/base/ecore_rt_defs.h b/drivers/net/qede/base/ecore_rt_defs.h index 3860e1a56..08b1f4700 100644 --- a/drivers/net/qede/base/ecore_rt_defs.h +++ b/drivers/net/qede/base/ecore_rt_defs.h @@ -24,512 +24,428 @@ #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 -#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 -#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 -#define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18 -#define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19 -#define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20 -#define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21 -#define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22 -#define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23 -#define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24 -#define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25 -#define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26 -#define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27 -#define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28 -#define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29 -#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30 -#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31 -#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32 -#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33 -#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34 -#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35 -#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36 -#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37 -#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38 -#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39 -#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40 -#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41 -#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42 -#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43 -#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44 -#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45 -#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024 -#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069 -#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024 -#define CAU_REG_PI_MEMORY_RT_OFFSET 2093 +#define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16 +#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17 +#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18 +#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19 +#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20 +#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21 +#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22 +#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23 +#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24 +#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25 +#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26 +#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 +#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762 +#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 +#define CAU_REG_PI_MEMORY_RT_OFFSET 1498 #define CAU_REG_PI_MEMORY_RT_SIZE 4416 -#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509 -#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510 -#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511 -#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512 -#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513 -#define PRS_REG_SEARCH_TCP_RT_OFFSET 6514 -#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515 -#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516 -#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517 -#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518 -#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519 -#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520 -#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521 -#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522 -#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523 -#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524 -#define SRC_REG_FIRSTFREE_RT_OFFSET 6525 +#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914 +#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915 +#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916 +#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917 +#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918 +#define PRS_REG_SEARCH_TCP_RT_OFFSET 5919 +#define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920 +#define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921 +#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922 +#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923 +#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924 +#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925 +#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926 +#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927 +#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928 +#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929 +#define SRC_REG_FIRSTFREE_RT_OFFSET 5930 #define SRC_REG_FIRSTFREE_RT_SIZE 2 -#define SRC_REG_LASTFREE_RT_OFFSET 6527 +#define SRC_REG_LASTFREE_RT_OFFSET 5932 #define SRC_REG_LASTFREE_RT_SIZE 2 -#define SRC_REG_COUNTFREE_RT_OFFSET 6529 -#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530 -#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531 -#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532 -#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533 -#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534 -#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535 -#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536 -#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537 -#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538 -#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539 -#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540 -#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541 -#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542 -#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543 -#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544 -#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545 -#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546 -#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547 -#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548 -#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549 -#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550 -#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551 -#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552 -#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553 -#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554 -#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555 -#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556 -#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557 -#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558 -#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559 -#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560 -#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561 -#define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562 -#define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563 -#define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564 -#define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565 -#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566 -#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414 -#define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980 -#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981 -#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982 -#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983 -#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984 -#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985 -#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986 -#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987 -#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988 -#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989 -#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990 -#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991 -#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992 +#define SRC_REG_COUNTFREE_RT_OFFSET 5934 +#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935 +#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936 +#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937 +#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938 +#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939 +#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940 +#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941 +#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942 +#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943 +#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944 +#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945 +#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946 +#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947 +#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948 +#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949 +#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950 +#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951 +#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952 +#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953 +#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954 +#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955 +#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956 +#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957 +#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958 +#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959 +#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960 +#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961 +#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962 +#define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963 +#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964 +#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965 +#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966 +#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967 +#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 +#define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967 +#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968 +#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969 +#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970 +#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971 +#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972 +#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973 +#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974 +#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975 +#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976 +#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977 +#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978 +#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 -#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408 -#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608 -#define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016 -#define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017 -#define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018 -#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019 -#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020 -#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021 -#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022 -#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023 -#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024 -#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025 -#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026 -#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027 -#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028 -#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029 -#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030 -#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031 -#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032 -#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033 -#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034 -#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035 -#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036 -#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037 -#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038 -#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039 -#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040 -#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041 -#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042 -#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043 -#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044 -#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045 -#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046 -#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047 -#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048 -#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049 -#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050 -#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051 -#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052 -#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053 -#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054 -#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055 -#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056 -#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057 -#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058 -#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059 -#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060 -#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061 -#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062 -#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063 -#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064 -#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065 -#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066 -#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067 -#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068 -#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069 -#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070 -#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071 -#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072 -#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073 -#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074 -#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075 -#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076 -#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077 -#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078 -#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079 -#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080 -#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081 -#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082 -#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083 +#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395 +#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512 +#define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907 +#define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908 +#define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909 +#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910 +#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911 +#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912 +#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913 +#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914 +#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915 +#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916 +#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917 +#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918 +#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919 +#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920 +#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921 +#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922 +#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923 +#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924 +#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925 +#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926 +#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927 +#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928 +#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929 +#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930 +#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931 +#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932 +#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933 +#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934 +#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935 +#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936 +#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937 +#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938 +#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939 +#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940 +#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941 +#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942 +#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943 +#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944 +#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945 +#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946 +#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947 +#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948 +#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949 +#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950 +#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951 +#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952 +#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953 +#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954 +#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955 +#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956 +#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957 +#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958 +#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959 +#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960 +#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961 +#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962 +#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963 +#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964 +#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965 +#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966 +#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967 +#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968 +#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969 +#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970 +#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971 +#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972 +#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973 +#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 -#define QM_REG_PTRTBLOTHER_RT_OFFSET 34211 +#define QM_REG_PTRTBLOTHER_RT_OFFSET 29102 #define QM_REG_PTRTBLOTHER_RT_SIZE 256 -#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34467 -#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34468 -#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34469 -#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34470 -#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34471 -#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34472 -#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34473 -#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34474 -#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34475 -#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34476 -#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34477 -#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34478 -#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34479 -#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34480 -#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34481 -#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34482 -#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34483 -#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34484 -#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34485 -#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34486 -#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34487 -#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34488 -#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34489 -#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34490 -#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34491 -#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34492 -#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34493 -#define QM_REG_PQTX2PF_0_RT_OFFSET 34494 -#define QM_REG_PQTX2PF_1_RT_OFFSET 34495 -#define QM_REG_PQTX2PF_2_RT_OFFSET 34496 -#define QM_REG_PQTX2PF_3_RT_OFFSET 34497 -#define QM_REG_PQTX2PF_4_RT_OFFSET 34498 -#define QM_REG_PQTX2PF_5_RT_OFFSET 34499 -#define QM_REG_PQTX2PF_6_RT_OFFSET 34500 -#define QM_REG_PQTX2PF_7_RT_OFFSET 34501 -#define QM_REG_PQTX2PF_8_RT_OFFSET 34502 -#define QM_REG_PQTX2PF_9_RT_OFFSET 34503 -#define QM_REG_PQTX2PF_10_RT_OFFSET 34504 -#define QM_REG_PQTX2PF_11_RT_OFFSET 34505 -#define QM_REG_PQTX2PF_12_RT_OFFSET 34506 -#define QM_REG_PQTX2PF_13_RT_OFFSET 34507 -#define QM_REG_PQTX2PF_14_RT_OFFSET 34508 -#define QM_REG_PQTX2PF_15_RT_OFFSET 34509 -#define QM_REG_PQTX2PF_16_RT_OFFSET 34510 -#define QM_REG_PQTX2PF_17_RT_OFFSET 34511 -#define QM_REG_PQTX2PF_18_RT_OFFSET 34512 -#define QM_REG_PQTX2PF_19_RT_OFFSET 34513 -#define QM_REG_PQTX2PF_20_RT_OFFSET 34514 -#define QM_REG_PQTX2PF_21_RT_OFFSET 34515 -#define QM_REG_PQTX2PF_22_RT_OFFSET 34516 -#define QM_REG_PQTX2PF_23_RT_OFFSET 34517 -#define QM_REG_PQTX2PF_24_RT_OFFSET 34518 -#define QM_REG_PQTX2PF_25_RT_OFFSET 34519 -#define QM_REG_PQTX2PF_26_RT_OFFSET 34520 -#define QM_REG_PQTX2PF_27_RT_OFFSET 34521 -#define QM_REG_PQTX2PF_28_RT_OFFSET 34522 -#define QM_REG_PQTX2PF_29_RT_OFFSET 34523 -#define QM_REG_PQTX2PF_30_RT_OFFSET 34524 -#define QM_REG_PQTX2PF_31_RT_OFFSET 34525 -#define QM_REG_PQTX2PF_32_RT_OFFSET 34526 -#define QM_REG_PQTX2PF_33_RT_OFFSET 34527 -#define QM_REG_PQTX2PF_34_RT_OFFSET 34528 -#define QM_REG_PQTX2PF_35_RT_OFFSET 34529 -#define QM_REG_PQTX2PF_36_RT_OFFSET 34530 -#define QM_REG_PQTX2PF_37_RT_OFFSET 34531 -#define QM_REG_PQTX2PF_38_RT_OFFSET 34532 -#define QM_REG_PQTX2PF_39_RT_OFFSET 34533 -#define QM_REG_PQTX2PF_40_RT_OFFSET 34534 -#define QM_REG_PQTX2PF_41_RT_OFFSET 34535 -#define QM_REG_PQTX2PF_42_RT_OFFSET 34536 -#define QM_REG_PQTX2PF_43_RT_OFFSET 34537 -#define QM_REG_PQTX2PF_44_RT_OFFSET 34538 -#define QM_REG_PQTX2PF_45_RT_OFFSET 34539 -#define QM_REG_PQTX2PF_46_RT_OFFSET 34540 -#define QM_REG_PQTX2PF_47_RT_OFFSET 34541 -#define QM_REG_PQTX2PF_48_RT_OFFSET 34542 -#define QM_REG_PQTX2PF_49_RT_OFFSET 34543 -#define QM_REG_PQTX2PF_50_RT_OFFSET 34544 -#define QM_REG_PQTX2PF_51_RT_OFFSET 34545 -#define QM_REG_PQTX2PF_52_RT_OFFSET 34546 -#define QM_REG_PQTX2PF_53_RT_OFFSET 34547 -#define QM_REG_PQTX2PF_54_RT_OFFSET 34548 -#define QM_REG_PQTX2PF_55_RT_OFFSET 34549 -#define QM_REG_PQTX2PF_56_RT_OFFSET 34550 -#define QM_REG_PQTX2PF_57_RT_OFFSET 34551 -#define QM_REG_PQTX2PF_58_RT_OFFSET 34552 -#define QM_REG_PQTX2PF_59_RT_OFFSET 34553 -#define QM_REG_PQTX2PF_60_RT_OFFSET 34554 -#define QM_REG_PQTX2PF_61_RT_OFFSET 34555 -#define QM_REG_PQTX2PF_62_RT_OFFSET 34556 -#define QM_REG_PQTX2PF_63_RT_OFFSET 34557 -#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34558 -#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34559 -#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34560 -#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34561 -#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34562 -#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34563 -#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34564 -#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34565 -#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34566 -#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34567 -#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34568 -#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34569 -#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34570 -#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34571 -#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34572 -#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34573 -#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34574 -#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34575 -#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34576 -#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34577 -#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34578 -#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34579 -#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34580 -#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34581 -#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34582 -#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34583 -#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34584 -#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34585 -#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34586 +#define QM_REG_VOQCRDLINE_RT_OFFSET 29358 +#define QM_REG_VOQCRDLINE_RT_SIZE 20 +#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378 +#define QM_REG_VOQINITCRDLINE_RT_SIZE 20 +#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398 +#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399 +#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400 +#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401 +#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402 +#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403 +#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404 +#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405 +#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406 +#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407 +#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408 +#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409 +#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410 +#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411 +#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412 +#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413 +#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414 +#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415 +#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416 +#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417 +#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418 +#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419 +#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420 +#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421 +#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422 +#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423 +#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424 +#define QM_REG_PQTX2PF_0_RT_OFFSET 29425 +#define QM_REG_PQTX2PF_1_RT_OFFSET 29426 +#define QM_REG_PQTX2PF_2_RT_OFFSET 29427 +#define QM_REG_PQTX2PF_3_RT_OFFSET 29428 +#define QM_REG_PQTX2PF_4_RT_OFFSET 29429 +#define QM_REG_PQTX2PF_5_RT_OFFSET 29430 +#define QM_REG_PQTX2PF_6_RT_OFFSET 29431 +#define QM_REG_PQTX2PF_7_RT_OFFSET 29432 +#define QM_REG_PQTX2PF_8_RT_OFFSET 29433 +#define QM_REG_PQTX2PF_9_RT_OFFSET 29434 +#define QM_REG_PQTX2PF_10_RT_OFFSET 29435 +#define QM_REG_PQTX2PF_11_RT_OFFSET 29436 +#define QM_REG_PQTX2PF_12_RT_OFFSET 29437 +#define QM_REG_PQTX2PF_13_RT_OFFSET 29438 +#define QM_REG_PQTX2PF_14_RT_OFFSET 29439 +#define QM_REG_PQTX2PF_15_RT_OFFSET 29440 +#define QM_REG_PQTX2PF_16_RT_OFFSET 29441 +#define QM_REG_PQTX2PF_17_RT_OFFSET 29442 +#define QM_REG_PQTX2PF_18_RT_OFFSET 29443 +#define QM_REG_PQTX2PF_19_RT_OFFSET 29444 +#define QM_REG_PQTX2PF_20_RT_OFFSET 29445 +#define QM_REG_PQTX2PF_21_RT_OFFSET 29446 +#define QM_REG_PQTX2PF_22_RT_OFFSET 29447 +#define QM_REG_PQTX2PF_23_RT_OFFSET 29448 +#define QM_REG_PQTX2PF_24_RT_OFFSET 29449 +#define QM_REG_PQTX2PF_25_RT_OFFSET 29450 +#define QM_REG_PQTX2PF_26_RT_OFFSET 29451 +#define QM_REG_PQTX2PF_27_RT_OFFSET 29452 +#define QM_REG_PQTX2PF_28_RT_OFFSET 29453 +#define QM_REG_PQTX2PF_29_RT_OFFSET 29454 +#define QM_REG_PQTX2PF_30_RT_OFFSET 29455 +#define QM_REG_PQTX2PF_31_RT_OFFSET 29456 +#define QM_REG_PQTX2PF_32_RT_OFFSET 29457 +#define QM_REG_PQTX2PF_33_RT_OFFSET 29458 +#define QM_REG_PQTX2PF_34_RT_OFFSET 29459 +#define QM_REG_PQTX2PF_35_RT_OFFSET 29460 +#define QM_REG_PQTX2PF_36_RT_OFFSET 29461 +#define QM_REG_PQTX2PF_37_RT_OFFSET 29462 +#define QM_REG_PQTX2PF_38_RT_OFFSET 29463 +#define QM_REG_PQTX2PF_39_RT_OFFSET 29464 +#define QM_REG_PQTX2PF_40_RT_OFFSET 29465 +#define QM_REG_PQTX2PF_41_RT_OFFSET 29466 +#define QM_REG_PQTX2PF_42_RT_OFFSET 29467 +#define QM_REG_PQTX2PF_43_RT_OFFSET 29468 +#define QM_REG_PQTX2PF_44_RT_OFFSET 29469 +#define QM_REG_PQTX2PF_45_RT_OFFSET 29470 +#define QM_REG_PQTX2PF_46_RT_OFFSET 29471 +#define QM_REG_PQTX2PF_47_RT_OFFSET 29472 +#define QM_REG_PQTX2PF_48_RT_OFFSET 29473 +#define QM_REG_PQTX2PF_49_RT_OFFSET 29474 +#define QM_REG_PQTX2PF_50_RT_OFFSET 29475 +#define QM_REG_PQTX2PF_51_RT_OFFSET 29476 +#define QM_REG_PQTX2PF_52_RT_OFFSET 29477 +#define QM_REG_PQTX2PF_53_RT_OFFSET 29478 +#define QM_REG_PQTX2PF_54_RT_OFFSET 29479 +#define QM_REG_PQTX2PF_55_RT_OFFSET 29480 +#define QM_REG_PQTX2PF_56_RT_OFFSET 29481 +#define QM_REG_PQTX2PF_57_RT_OFFSET 29482 +#define QM_REG_PQTX2PF_58_RT_OFFSET 29483 +#define QM_REG_PQTX2PF_59_RT_OFFSET 29484 +#define QM_REG_PQTX2PF_60_RT_OFFSET 29485 +#define QM_REG_PQTX2PF_61_RT_OFFSET 29486 +#define QM_REG_PQTX2PF_62_RT_OFFSET 29487 +#define QM_REG_PQTX2PF_63_RT_OFFSET 29488 +#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489 +#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490 +#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491 +#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492 +#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493 +#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494 +#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495 +#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496 +#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497 +#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498 +#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499 +#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500 +#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501 +#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502 +#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503 +#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504 +#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505 +#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506 +#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507 +#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508 +#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509 +#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510 +#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511 +#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512 +#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513 +#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514 +#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515 +#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516 +#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 -#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34842 +#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 -#define QM_REG_RLGLBLCRD_RT_OFFSET 35098 +#define QM_REG_RLGLBLCRD_RT_OFFSET 30029 #define QM_REG_RLGLBLCRD_RT_SIZE 256 -#define QM_REG_RLGLBLENABLE_RT_OFFSET 35354 -#define QM_REG_RLPFPERIOD_RT_OFFSET 35355 -#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35356 -#define QM_REG_RLPFINCVAL_RT_OFFSET 35357 +#define QM_REG_RLGLBLENABLE_RT_OFFSET 30285 +#define QM_REG_RLPFPERIOD_RT_OFFSET 30286 +#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287 +#define QM_REG_RLPFINCVAL_RT_OFFSET 30288 #define QM_REG_RLPFINCVAL_RT_SIZE 16 -#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35373 +#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_RLPFCRD_RT_OFFSET 35389 +#define QM_REG_RLPFCRD_RT_OFFSET 30320 #define QM_REG_RLPFCRD_RT_SIZE 16 -#define QM_REG_RLPFENABLE_RT_OFFSET 35405 -#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35406 -#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35407 +#define QM_REG_RLPFENABLE_RT_OFFSET 30336 +#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337 +#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 -#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35423 +#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 -#define QM_REG_WFQPFCRD_RT_OFFSET 35439 -#define QM_REG_WFQPFCRD_RT_SIZE 256 -#define QM_REG_WFQPFENABLE_RT_OFFSET 35695 -#define QM_REG_WFQVPENABLE_RT_OFFSET 35696 -#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35697 +#define QM_REG_WFQPFCRD_RT_OFFSET 30370 +#define QM_REG_WFQPFCRD_RT_SIZE 160 +#define QM_REG_WFQPFENABLE_RT_OFFSET 30530 +#define QM_REG_WFQVPENABLE_RT_OFFSET 30531 +#define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 -#define QM_REG_TXPQMAP_RT_OFFSET 36209 +#define QM_REG_TXPQMAP_RT_OFFSET 31044 #define QM_REG_TXPQMAP_RT_SIZE 512 -#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36721 +#define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 -#define QM_REG_WFQVPCRD_RT_OFFSET 37233 +#define QM_REG_WFQVPCRD_RT_OFFSET 32068 #define QM_REG_WFQVPCRD_RT_SIZE 512 -#define QM_REG_WFQVPMAP_RT_OFFSET 37745 +#define QM_REG_WFQVPMAP_RT_OFFSET 32580 #define QM_REG_WFQVPMAP_RT_SIZE 512 -#define QM_REG_PTRTBLTX_RT_OFFSET 38257 +#define QM_REG_PTRTBLTX_RT_OFFSET 33092 #define QM_REG_PTRTBLTX_RT_SIZE 1024 -#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 39281 -#define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 -#define QM_REG_VOQCRDLINE_RT_OFFSET 39601 -#define QM_REG_VOQCRDLINE_RT_SIZE 36 -#define QM_REG_VOQINITCRDLINE_RT_OFFSET 39637 -#define QM_REG_VOQINITCRDLINE_RT_SIZE 36 -#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 39673 -#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 39674 -#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 39675 -#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 39676 -#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 39677 -#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 39678 -#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 39679 -#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 39680 -#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 39681 +#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34116 +#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160 +#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34276 +#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34277 +#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34278 +#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34279 +#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34280 +#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34281 +#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34282 +#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34283 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 39685 +#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34287 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 -#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 39689 +#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34291 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 -#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 39721 +#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34323 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 39737 +#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34339 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 39753 +#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34355 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 -#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 39769 +#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34371 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 -#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 39785 -#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 39786 +#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34387 +#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34388 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 39794 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 40818 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 41330 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 41842 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 42354 -#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512 -#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 42866 -#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32 -#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 42898 -#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 42899 -#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 42900 -#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 42901 -#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 42902 -#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 42903 -#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 42904 -#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 42905 -#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 42906 -#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 42907 -#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 42908 -#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 42909 -#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 42910 -#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 42911 -#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 42912 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 42913 -#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 42914 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 42915 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 42916 -#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 42917 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 42918 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 42919 -#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 42920 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 42921 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 42922 -#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 42923 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 42924 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 42925 -#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 42926 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 42927 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 42928 -#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 42929 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 42930 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 42931 -#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 42932 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 42933 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 42934 -#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 42935 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 42936 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 42937 -#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 42938 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 42939 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 42940 -#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 42941 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 42942 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 42943 -#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 42944 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 42945 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 42946 -#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 42947 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 42948 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 42949 -#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 42950 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 42951 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 42952 -#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 42953 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 42954 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 42955 -#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 42956 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 42957 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 42958 -#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 42959 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 42960 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 42961 -#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 42962 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 42963 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 42964 -#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 42965 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 42966 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 42967 -#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 42968 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 42969 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 42970 -#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 42971 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 42972 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 42973 -#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 42974 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 42975 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 42976 -#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 42977 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 42978 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 42979 -#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 42980 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 42981 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 42982 -#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 42983 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 42984 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 42985 -#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 42986 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 42987 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 42988 -#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 42989 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 42990 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 42991 -#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 42992 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 42993 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 42994 -#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 42995 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 42996 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 42997 -#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 42998 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 42999 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 43000 -#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 43001 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 43002 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 43003 -#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 43004 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 43005 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 43006 -#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 43007 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 43008 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 43009 -#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 43010 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 43011 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 43012 -#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 43013 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 43014 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 43015 -#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 43016 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 43017 -#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 43018 -#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 43019 -#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 43020 -#define XCM_REG_CON_PHY_Q3_RT_OFFSET 43021 +#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34396 +#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34397 +#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34398 +#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34399 +#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34400 +#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34401 +#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34402 +#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34403 +#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34404 +#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34405 +#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34406 +#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34407 +#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34408 +#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34409 +#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34410 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34411 +#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34412 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34413 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34414 +#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34415 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34416 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34417 +#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34418 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34419 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34420 +#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34421 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34422 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34423 +#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34424 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34425 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34426 +#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34427 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34428 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34429 +#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34430 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34431 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34432 +#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34433 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34434 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34435 +#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34436 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34437 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34438 +#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34439 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34440 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34441 +#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34442 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34443 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34444 +#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34445 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34446 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34447 +#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34448 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34449 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34450 +#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34451 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34452 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34453 +#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34454 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34455 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34456 +#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34457 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34458 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34459 +#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34460 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34461 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34462 +#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34463 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34464 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34465 +#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34466 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34467 +#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34468 +#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34469 +#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34470 +#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34471 -#define RUNTIME_ARRAY_SIZE 43022 +#define RUNTIME_ARRAY_SIZE 34472 /* Init Callbacks */ #define DMAE_READY_CB 0 diff --git a/drivers/net/qede/base/mcp_public.h b/drivers/net/qede/base/mcp_public.h index 13c2e2d11..98b9723dd 100644 --- a/drivers/net/qede/base/mcp_public.h +++ b/drivers/net/qede/base/mcp_public.h @@ -18,6 +18,15 @@ #define MCP_PUBLIC_H #define VF_MAX_STATIC 192 /* In case of AH */ +#define VF_BITMAP_SIZE_IN_DWORDS (VF_MAX_STATIC / 32) +#define VF_BITMAP_SIZE_IN_BYTES (VF_BITMAP_SIZE_IN_DWORDS * sizeof(u32)) + +/* Extended array size to support for 240 VFs 8 dwords */ +#define EXT_VF_MAX_STATIC 240 +#define EXT_VF_BITMAP_SIZE_IN_DWORDS (((EXT_VF_MAX_STATIC - 1) / 32) + 1) +#define EXT_VF_BITMAP_SIZE_IN_BYTES (EXT_VF_BITMAP_SIZE_IN_DWORDS * \ + sizeof(u32)) +#define ADDED_VF_BITMAP_SIZE 2 #define MCP_GLOB_PATH_MAX 2 #define MCP_PORT_MAX 2 /* Global */ @@ -591,6 +600,8 @@ struct public_path { #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 #define PROCESS_KILL_GLOB_AEU_BIT_OFFSET 16 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) + /*Added to support E5 240 VFs*/ + u32 mcp_vf_disabled2[ADDED_VF_BITMAP_SIZE]; }; /**************************************/ @@ -1270,6 +1281,12 @@ struct public_drv_mb { /* params [31:8] - reserved, [7:0] - bitmap */ #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 +/* Param: [0:15] Option ID, [16] - All, [17] - Init, [18] - Commit, + * [19] - Free + */ +#define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000 +/* Param: [0:15] Option ID, [17] - Init, [18] , [19] - Free */ +#define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000 /*deprecated don't use*/ #define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 @@ -1317,6 +1334,7 @@ struct public_drv_mb { #define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000 /* Param: [0:3] - version, [4:15] - name (null terminated) */ #define DRV_MSG_CODE_SET_VERSION 0x000f0000 +#define DRV_MSG_CODE_MCP_RESET_FORCE 0x000f04ce /* Halts the MCP. To resume MCP, user will need to use * MCP_REG_CPU_STATE/MCP_REG_CPU_MODE registers. */ @@ -1607,6 +1625,9 @@ struct public_drv_mb { #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 +#define DRV_MB_PARAM_SET_LED1_MODE_ON 0x3 +#define DRV_MB_PARAM_SET_LED2_MODE_ON 0x4 +#define DRV_MB_PARAM_SET_ACT_LED_MODE_ON 0x6 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 @@ -1664,8 +1685,32 @@ struct public_drv_mb { #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 +#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0 +/* Option# */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF +#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_OFFSET 16 +/* (Only for Set) Applies option<92>s value to all entities (port/func) + * depending on the option type + */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000 +#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_OFFSET 17 +/* When set, and state is IDLE, MFW will allocate resources and load + * configuration from NVM + */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000 +#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_OFFSET 18 +/* (Only for Set) - When set submit changed nvm_cfg1 to flash */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000 +#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_OFFSET 19 +/* Free - When set, free allocated resources, and return to IDLE state. */ +#define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000 +#define SINGLE_NVM_WR_OP(optionId) \ + ((((optionId) & DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK) << \ + DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET) | \ + (DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK | \ + DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK | \ + DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK)) u32 fw_mb_header; -#define FW_MSG_CODE_MASK 0xffff0000 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 @@ -1704,6 +1749,12 @@ struct public_drv_mb { #define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 +#define FW_MSG_CODE_ERR_RESOURCE_TEMPORARY_UNAVAILABLE 0x008b0000 +#define FW_MSG_CODE_ERR_RESOURCE_ALREADY_ALLOCATED 0x008c0000 +#define FW_MSG_CODE_ERR_RESOURCE_NOT_ALLOCATED 0x008d0000 +#define FW_MSG_CODE_ERR_NON_USER_OPTION 0x008e0000 +#define FW_MSG_CODE_ERR_UNKNOWN_OPTION 0x008f0000 +#define FW_MSG_CODE_WAIT 0x00900000 #define FW_MSG_CODE_FLR_ACK 0x02000000 #define FW_MSG_CODE_FLR_NACK 0x02100000 #define FW_MSG_CODE_SET_DRIVER_DONE 0x02200000 @@ -1783,11 +1834,13 @@ struct public_drv_mb { #define FW_MSG_CODE_WOL_READ_BUFFER_OK 0x00850000 #define FW_MSG_CODE_WOL_READ_BUFFER_INVALID_VAL 0x00860000 -#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff - #define FW_MSG_CODE_ATTRIBUTE_INVALID_KEY 0x00020000 #define FW_MSG_CODE_ATTRIBUTE_INVALID_CMD 0x00030000 +#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff +#define FW_MSG_SEQ_NUMBER_OFFSET 0 +#define FW_MSG_CODE_MASK 0xffff0000 +#define FW_MSG_CODE_OFFSET 16 u32 fw_mb_param; /* Resource Allocation params - MFW version support */ #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 diff --git a/drivers/net/qede/base/nvm_cfg.h b/drivers/net/qede/base/nvm_cfg.h index ab86260ed..daa5437dd 100644 --- a/drivers/net/qede/base/nvm_cfg.h +++ b/drivers/net/qede/base/nvm_cfg.h @@ -11,20 +11,21 @@ * Description: NVM config file - Generated file from nvm cfg excel. * DO NOT MODIFY !!! * - * Created: 5/8/2017 + * Created: 1/6/2019 * ****************************************************************************/ #ifndef NVM_CFG_H #define NVM_CFG_H -#define NVM_CFG_version 0x83000 -#define NVM_CFG_new_option_seq 23 +#define NVM_CFG_version 0x84500 -#define NVM_CFG_removed_option_seq 1 +#define NVM_CFG_new_option_seq 45 -#define NVM_CFG_updated_value_seq 4 +#define NVM_CFG_removed_option_seq 4 + +#define NVM_CFG_updated_value_seq 13 struct nvm_cfg_mac_address { u32 mac_addr_hi; @@ -54,6 +55,7 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 + #define NVM_CFG1_GLOB_MF_MODE_DCI_NPAR 0x8 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12 #define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0 @@ -153,6 +155,7 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF + #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G_LIO2 0x10 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8 #define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0 @@ -510,6 +513,18 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_OFFSET 28 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_DISABLED 0x0 #define NVM_CFG1_GLOB_VOLTAGE_REGULATOR_TYPE_TI 0x1 + /* Enable/Disable PCIE Relaxed Ordering */ + #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_MASK 0x40000000 + #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_OFFSET 30 + #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_DISABLED 0x0 + #define NVM_CFG1_GLOB_PCIE_RELAXED_ORDERING_ENABLED 0x1 + /* Reset the chip using iPOR to release PCIe due to short PERST + * issues + */ + #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_MASK 0x80000000 + #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_OFFSET 31 + #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_DISABLED 0x0 + #define NVM_CFG1_GLOB_SHORT_PERST_PROTECTION_ENABLED 0x1 u32 led_global_settings; /* 0x74 */ #define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F #define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0 @@ -590,6 +605,11 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_RUNTIME_PORT2_SWAP_MAP_OFFSET 27 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_MASK 0x60000000 #define NVM_CFG1_GLOB_RUNTIME_PORT3_SWAP_MAP_OFFSET 29 + /* Option to Disable embedded LLDP, 0 - Off, 1 - On */ + #define NVM_CFG1_GLOB_LLDP_DISABLE_MASK 0x80000000 + #define NVM_CFG1_GLOB_LLDP_DISABLE_OFFSET 31 + #define NVM_CFG1_GLOB_LLDP_DISABLE_OFF 0x0 + #define NVM_CFG1_GLOB_LLDP_DISABLE_ON 0x1 u32 mbi_version; /* 0x7C */ #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 @@ -1037,13 +1057,308 @@ struct nvm_cfg1_glob { #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO29 0x1E #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO30 0x1F #define NVM_CFG1_GLOB_THERMAL_ALARM_GPIO_GPIO31 0x20 + /* Select the number of allowed port link in aux power */ + #define NVM_CFG1_GLOB_NCSI_AUX_LINK_MASK 0x00000300 + #define NVM_CFG1_GLOB_NCSI_AUX_LINK_OFFSET 8 + #define NVM_CFG1_GLOB_NCSI_AUX_LINK_DEFAULT 0x0 + #define NVM_CFG1_GLOB_NCSI_AUX_LINK_1_PORT 0x1 + #define NVM_CFG1_GLOB_NCSI_AUX_LINK_2_PORTS 0x2 + #define NVM_CFG1_GLOB_NCSI_AUX_LINK_3_PORTS 0x3 + /* Set Trace Filter Log Level */ + #define NVM_CFG1_GLOB_TRACE_LEVEL_MASK 0x00000C00 + #define NVM_CFG1_GLOB_TRACE_LEVEL_OFFSET 10 + #define NVM_CFG1_GLOB_TRACE_LEVEL_ALL 0x0 + #define NVM_CFG1_GLOB_TRACE_LEVEL_DEBUG 0x1 + #define NVM_CFG1_GLOB_TRACE_LEVEL_TRACE 0x2 + #define NVM_CFG1_GLOB_TRACE_LEVEL_ERROR 0x3 + /* For OCP2.0, MFW listens on SMBUS slave address 0x3e, and return + * temperature reading + */ + #define NVM_CFG1_GLOB_EMULATED_TMP421_MASK 0x00001000 + #define NVM_CFG1_GLOB_EMULATED_TMP421_OFFSET 12 + #define NVM_CFG1_GLOB_EMULATED_TMP421_DISABLED 0x0 + #define NVM_CFG1_GLOB_EMULATED_TMP421_ENABLED 0x1 + /* GPIO which triggers when ASIC temperature reaches nvm option 286 + * value + */ + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_MASK 0x001FE000 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_OFFSET 13 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_NA 0x0 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO0 0x1 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO1 0x2 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO2 0x3 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO3 0x4 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO4 0x5 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO5 0x6 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO6 0x7 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO7 0x8 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO8 0x9 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO9 0xA + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO10 0xB + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO11 0xC + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO12 0xD + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO13 0xE + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO14 0xF + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO15 0x10 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO16 0x11 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO17 0x12 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO18 0x13 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO19 0x14 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO20 0x15 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO21 0x16 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO22 0x17 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO23 0x18 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO24 0x19 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO25 0x1A + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO26 0x1B + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO27 0x1C + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO28 0x1D + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO29 0x1E + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO30 0x1F + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_GPIO_GPIO31 0x20 + /* Warning temperature threshold used with nvm option 286 */ + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_THRESHOLD_MASK 0x1FE00000 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_THRESHOLD_OFFSET 21 + /* Disable PLDM protocol */ + #define NVM_CFG1_GLOB_DISABLE_PLDM_MASK 0x20000000 + #define NVM_CFG1_GLOB_DISABLE_PLDM_OFFSET 29 + #define NVM_CFG1_GLOB_DISABLE_PLDM_DISABLED 0x0 + #define NVM_CFG1_GLOB_DISABLE_PLDM_ENABLED 0x1 + /* Disable OCBB protocol */ + #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_MASK 0x40000000 + #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_OFFSET 30 + #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_DISABLED 0x0 + #define NVM_CFG1_GLOB_DISABLE_MCTP_OEM_ENABLED 0x1 u32 preboot_debug_mode_std; /* 0x140 */ u32 preboot_debug_mode_ext; /* 0x144 */ u32 ext_phy_cfg1; /* 0x148 */ /* Ext PHY MDI pair swap value */ - #define NVM_CFG1_GLOB_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF - #define NVM_CFG1_GLOB_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0 - u32 reserved[55]; /* 0x14C */ + #define NVM_CFG1_GLOB_RESERVED_244_MASK 0x0000FFFF + #define NVM_CFG1_GLOB_RESERVED_244_OFFSET 0 + /* Define for PGOOD signal Mapping for EXT PHY */ + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_OFFSET 16 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_NA 0x0 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO0 0x1 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO1 0x2 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO2 0x3 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO3 0x4 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO4 0x5 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO5 0x6 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO6 0x7 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO7 0x8 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO8 0x9 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO9 0xA + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO10 0xB + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO11 0xC + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO12 0xD + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO13 0xE + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO14 0xF + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO15 0x10 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO16 0x11 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO17 0x12 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO18 0x13 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO19 0x14 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO20 0x15 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO21 0x16 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO22 0x17 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO23 0x18 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO24 0x19 + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO25 0x1A + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO26 0x1B + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO27 0x1C + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO28 0x1D + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO29 0x1E + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO30 0x1F + #define NVM_CFG1_GLOB_EXT_PHY_PGOOD_GPIO31 0x20 + /* GPIO which trigger when PERST asserted */ + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_MASK 0xFF000000 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_OFFSET 24 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_NA 0x0 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO0 0x1 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO1 0x2 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO2 0x3 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO3 0x4 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO4 0x5 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO5 0x6 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO6 0x7 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO7 0x8 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO8 0x9 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO9 0xA + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO10 0xB + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO11 0xC + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO12 0xD + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO13 0xE + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO14 0xF + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO15 0x10 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO16 0x11 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO17 0x12 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO18 0x13 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO19 0x14 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO20 0x15 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO21 0x16 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO22 0x17 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO23 0x18 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO24 0x19 + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO25 0x1A + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO26 0x1B + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO27 0x1C + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO28 0x1D + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO29 0x1E + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO30 0x1F + #define NVM_CFG1_GLOB_PERST_INDICATION_GPIO_GPIO31 0x20 + u32 clocks; /* 0x14C */ + /* Sets core clock frequency */ + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MASK 0x000000FF + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_OFFSET 0 + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_DEFAULT 0x0 + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_375 0x1 + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_350 0x2 + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_325 0x3 + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_300 0x4 + #define NVM_CFG1_GLOB_MAIN_CLOCK_FREQUENCY_MAIN_CLK_280 0x5 + /* Sets MAC clock frequency */ + #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_OFFSET 8 + #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_DEFAULT 0x0 + #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_782 0x1 + #define NVM_CFG1_GLOB_MAC_CLOCK_FREQUENCY_MAC_CLK_516 0x2 + /* Sets storm clock frequency */ + #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_OFFSET 16 + #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_DEFAULT 0x0 + #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1200 0x1 + #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1000 0x2 + #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_900 0x3 + #define NVM_CFG1_GLOB_STORM_CLOCK_FREQUENCY_STORM_CLK_1100 0x4 + /* Non zero value will override PCIe AGC threshold to improve + * receiver + */ + #define NVM_CFG1_GLOB_OVERRIDE_AGC_THRESHOLD_MASK 0xFF000000 + #define NVM_CFG1_GLOB_OVERRIDE_AGC_THRESHOLD_OFFSET 24 + u32 pre2_generic_cont_1; /* 0x150 */ + #define NVM_CFG1_GLOB_50G_HLPC_PRE2_MASK 0x000000FF + #define NVM_CFG1_GLOB_50G_HLPC_PRE2_OFFSET 0 + #define NVM_CFG1_GLOB_50G_MLPC_PRE2_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_50G_MLPC_PRE2_OFFSET 8 + #define NVM_CFG1_GLOB_50G_LLPC_PRE2_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_50G_LLPC_PRE2_OFFSET 16 + #define NVM_CFG1_GLOB_25G_HLPC_PRE2_MASK 0xFF000000 + #define NVM_CFG1_GLOB_25G_HLPC_PRE2_OFFSET 24 + u32 pre2_generic_cont_2; /* 0x154 */ + #define NVM_CFG1_GLOB_25G_LLPC_PRE2_MASK 0x000000FF + #define NVM_CFG1_GLOB_25G_LLPC_PRE2_OFFSET 0 + #define NVM_CFG1_GLOB_25G_AC_PRE2_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_25G_AC_PRE2_OFFSET 8 + #define NVM_CFG1_GLOB_10G_PC_PRE2_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_10G_PC_PRE2_OFFSET 16 + #define NVM_CFG1_GLOB_PRE2_10G_AC_MASK 0xFF000000 + #define NVM_CFG1_GLOB_PRE2_10G_AC_OFFSET 24 + u32 pre2_generic_cont_3; /* 0x158 */ + #define NVM_CFG1_GLOB_1G_PRE2_MASK 0x000000FF + #define NVM_CFG1_GLOB_1G_PRE2_OFFSET 0 + #define NVM_CFG1_GLOB_5G_BT_PRE2_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_5G_BT_PRE2_OFFSET 8 + #define NVM_CFG1_GLOB_10G_BT_PRE2_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_10G_BT_PRE2_OFFSET 16 + /* When temperature goes below (warning temperature - delta) warning + * gpio is unset + */ + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_DELTA_MASK 0xFF000000 + #define NVM_CFG1_GLOB_WARNING_TEMPERATURE_DELTA_OFFSET 24 + u32 tx_rx_eq_50g_hlpc; /* 0x15C */ + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_HLPC_MASK 0x000000FF + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_HLPC_OFFSET 0 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_HLPC_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_HLPC_OFFSET 8 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_HLPC_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_HLPC_OFFSET 16 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_HLPC_MASK 0xFF000000 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_HLPC_OFFSET 24 + u32 tx_rx_eq_50g_mlpc; /* 0x160 */ + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_MLPC_MASK 0x000000FF + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_MLPC_OFFSET 0 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_MLPC_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_MLPC_OFFSET 8 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_MLPC_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_MLPC_OFFSET 16 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_MLPC_MASK 0xFF000000 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_MLPC_OFFSET 24 + u32 tx_rx_eq_50g_llpc; /* 0x164 */ + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_LLPC_MASK 0x000000FF + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_LLPC_OFFSET 0 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_LLPC_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_LLPC_OFFSET 8 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_LLPC_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_LLPC_OFFSET 16 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_LLPC_MASK 0xFF000000 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_LLPC_OFFSET 24 + u32 tx_rx_eq_50g_ac; /* 0x168 */ + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_AC_MASK 0x000000FF + #define NVM_CFG1_GLOB_INDEX0_RX_TX_EQ_50G_AC_OFFSET 0 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_AC_MASK 0x0000FF00 + #define NVM_CFG1_GLOB_INDEX1_RX_TX_EQ_50G_AC_OFFSET 8 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_AC_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_INDEX2_RX_TX_EQ_50G_AC_OFFSET 16 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_AC_MASK 0xFF000000 + #define NVM_CFG1_GLOB_INDEX3_RX_TX_EQ_50G_AC_OFFSET 24 + /* Set Trace Filter Modules Log Bit Mask */ + u32 trace_modules; /* 0x16C */ + #define NVM_CFG1_GLOB_TRACE_MODULES_ERROR 0x1 + #define NVM_CFG1_GLOB_TRACE_MODULES_DBG 0x2 + #define NVM_CFG1_GLOB_TRACE_MODULES_DRV_HSI 0x4 + #define NVM_CFG1_GLOB_TRACE_MODULES_INTERRUPT 0x8 + #define NVM_CFG1_GLOB_TRACE_MODULES_VPD 0x10 + #define NVM_CFG1_GLOB_TRACE_MODULES_FLR 0x20 + #define NVM_CFG1_GLOB_TRACE_MODULES_INIT 0x40 + #define NVM_CFG1_GLOB_TRACE_MODULES_NVM 0x80 + #define NVM_CFG1_GLOB_TRACE_MODULES_PIM 0x100 + #define NVM_CFG1_GLOB_TRACE_MODULES_NET 0x200 + #define NVM_CFG1_GLOB_TRACE_MODULES_POWER 0x400 + #define NVM_CFG1_GLOB_TRACE_MODULES_UTILS 0x800 + #define NVM_CFG1_GLOB_TRACE_MODULES_RESOURCES 0x1000 + #define NVM_CFG1_GLOB_TRACE_MODULES_SCHEDULER 0x2000 + #define NVM_CFG1_GLOB_TRACE_MODULES_PHYMOD 0x4000 + #define NVM_CFG1_GLOB_TRACE_MODULES_EVENTS 0x8000 + #define NVM_CFG1_GLOB_TRACE_MODULES_PMM 0x10000 + #define NVM_CFG1_GLOB_TRACE_MODULES_DBG_DRV 0x20000 + #define NVM_CFG1_GLOB_TRACE_MODULES_ETH 0x40000 + #define NVM_CFG1_GLOB_TRACE_MODULES_SECURITY 0x80000 + #define NVM_CFG1_GLOB_TRACE_MODULES_PCIE 0x100000 + #define NVM_CFG1_GLOB_TRACE_MODULES_TRACE 0x200000 + #define NVM_CFG1_GLOB_TRACE_MODULES_MANAGEMENT 0x400000 + #define NVM_CFG1_GLOB_TRACE_MODULES_SIM 0x800000 + u32 pcie_class_code_fcoe; /* 0x170 */ + /* Set PCIe FCoE Class Code */ + #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_FCOE_MASK 0x00FFFFFF + #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_FCOE_OFFSET 0 + /* When temperature goes below (ALOM FAN ON AUX value - delta) ALOM + * FAN ON AUX gpio is unset + */ + #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_DELTA_MASK 0xFF000000 + #define NVM_CFG1_GLOB_ALOM_FAN_ON_AUX_DELTA_OFFSET 24 + u32 pcie_class_code_iscsi; /* 0x174 */ + /* Set PCIe iSCSI Class Code */ + #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_ISCSI_MASK 0x00FFFFFF + #define NVM_CFG1_GLOB_PCIE_CLASS_CODE_ISCSI_OFFSET 0 + /* When temperature goes below (Dead Temp TH - delta)Thermal Event + * gpio is unset + */ + #define NVM_CFG1_GLOB_DEAD_TEMP_TH_DELTA_MASK 0xFF000000 + #define NVM_CFG1_GLOB_DEAD_TEMP_TH_DELTA_OFFSET 24 + u32 no_provisioned_mac; /* 0x178 */ + /* Set number of provisioned MAC addresses */ + #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_MAC_MASK 0x0000FFFF + #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_MAC_OFFSET 0 + /* Set number of provisioned VF MAC addresses */ + #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_VF_MAC_MASK 0x00FF0000 + #define NVM_CFG1_GLOB_NUMBER_OF_PROVISIONED_VF_MAC_OFFSET 16 + /* Enable/Disable BMC MAC */ + #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_MASK 0x01000000 + #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_OFFSET 24 + #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_DISABLED 0x0 + #define NVM_CFG1_GLOB_PROVISIONED_BMC_MAC_ENABLED 0x1 + u32 reserved[43]; /* 0x17C */ }; struct nvm_cfg1_path { @@ -1073,6 +1388,10 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_LED_MODE_PHY11 0xE #define NVM_CFG1_PORT_LED_MODE_PHY12 0xF #define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10 + #define NVM_CFG1_PORT_LED_MODE_OCP_3_0 0x11 + #define NVM_CFG1_PORT_LED_MODE_OCP_3_0_MAC2 0x12 + #define NVM_CFG1_PORT_LED_MODE_SW_DEF1 0x13 + #define NVM_CFG1_PORT_LED_MODE_SW_DEF1_MAC2 0x14 #define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00 #define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 @@ -1220,6 +1539,16 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_OFFSET 24 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_DISABLED 0x0 #define NVM_CFG1_PORT_RESERVED_WAS_MFW_SMARTLINQ_ENABLED 0x1 + /* Enable/Disable RX PAM-4 precoding */ + #define NVM_CFG1_PORT_RX_PRECODE_MASK 0x02000000 + #define NVM_CFG1_PORT_RX_PRECODE_OFFSET 25 + #define NVM_CFG1_PORT_RX_PRECODE_DISABLED 0x0 + #define NVM_CFG1_PORT_RX_PRECODE_ENABLED 0x1 + /* Enable/Disable TX PAM-4 precoding */ + #define NVM_CFG1_PORT_TX_PRECODE_MASK 0x04000000 + #define NVM_CFG1_PORT_TX_PRECODE_OFFSET 26 + #define NVM_CFG1_PORT_TX_PRECODE_DISABLED 0x0 + #define NVM_CFG1_PORT_TX_PRECODE_ENABLED 0x1 u32 phy_cfg; /* 0x1C */ #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF #define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0 @@ -1261,6 +1590,7 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM8485X 0x1 #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM5422X 0x2 + #define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_88X33X0 0x3 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00 #define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8 /* EEE power saving mode */ @@ -1337,6 +1667,13 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_AH_50G 0x10 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_50G 0x20 #define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40 + /* UID LED Blink Mode Settings */ + #define NVM_CFG1_PORT_UID_LED_MODE_MASK_MASK 0x0F000000 + #define NVM_CFG1_PORT_UID_LED_MODE_MASK_OFFSET 24 + #define NVM_CFG1_PORT_UID_LED_MODE_MASK_ACTIVITY_LED 0x1 + #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED0 0x2 + #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED1 0x4 + #define NVM_CFG1_PORT_UID_LED_MODE_MASK_LINK_LED2 0x8 u32 transceiver_00; /* 0x40 */ /* Define for mapping of transceiver signal module absent */ #define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF @@ -1379,6 +1716,11 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000 #define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12 + /* Option to override SmartAN FEC requirements */ + #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_MASK 0x00010000 + #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_OFFSET 16 + #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_DISABLED 0x0 + #define NVM_CFG1_PORT_SMARTAN_FEC_OVERRIDE_ENABLED 0x1 u32 device_ids; /* 0x44 */ #define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF #define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0 @@ -1840,7 +2182,289 @@ struct nvm_cfg1_port { #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_MASK \ 0x0000FF00 #define NVM_CFG1_PORT_PHY_MODULE_ALOM_FAN_ON_TEMP_TH_OFFSET 8 - u32 reserved[115]; /* 0x8C */ + /* Warning temperature threshold used with nvm option 235 */ + #define NVM_CFG1_PORT_PHY_MODULE_WARNING_TEMP_TH_MASK 0x00FF0000 + #define NVM_CFG1_PORT_PHY_MODULE_WARNING_TEMP_TH_OFFSET 16 + u32 ext_phy_cfg1; /* 0x8C */ + /* Ext PHY MDI pair swap value */ + #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_MASK 0x0000FFFF + #define NVM_CFG1_PORT_EXT_PHY_MDI_PAIR_SWAP_OFFSET 0 + u32 extended_speed; /* 0x90 */ + /* Sets speed in conjunction with legacy speed field */ + #define NVM_CFG1_PORT_EXTENDED_SPEED_MASK 0x0000FFFF + #define NVM_CFG1_PORT_EXTENDED_SPEED_OFFSET 0 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_NONE 0x1 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_1G 0x2 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_10G 0x4 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_25G 0x8 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_40G 0x10 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R 0x20 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_50G_R2 0x40 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R2 0x80 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_R4 0x100 + #define NVM_CFG1_PORT_EXTENDED_SPEED_EXTND_SPD_100G_P4 0x200 + /* Sets speed capabilities in conjunction with legacy capabilities + * field + */ + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_MASK 0xFFFF0000 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_OFFSET 16 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_NONE 0x1 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_1G 0x2 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_10G 0x4 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_25G 0x8 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_40G 0x10 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R 0x20 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_50G_R2 0x40 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R2 0x80 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_R4 0x100 + #define NVM_CFG1_PORT_EXTENDED_SPEED_CAP_EXTND_SPD_100G_P4 0x200 + /* Set speed specific FEC setting in conjunction with legacy FEC + * mode + */ + u32 extended_fec_mode; /* 0x94 */ + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_NONE 0x1 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_10G_NONE 0x2 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_10G_BASE_R 0x4 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_NONE 0x8 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_BASE_R 0x10 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_25G_RS528 0x20 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_40G_NONE 0x40 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_40G_BASE_R 0x80 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_NONE 0x100 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_BASE_R 0x200 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_RS528 0x400 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_50G_RS544 0x800 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_NONE 0x1000 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_BASE_R 0x2000 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_RS528 0x4000 + #define NVM_CFG1_PORT_EXTENDED_FEC_MODE_EXTND_FEC_100G_RS544 0x8000 + u32 port_generic_cont_01; /* 0x98 */ + /* Define for GPIO mapping of SFP Rate Select 0 */ + #define NVM_CFG1_PORT_MODULE_RS0_MASK 0x000000FF + #define NVM_CFG1_PORT_MODULE_RS0_OFFSET 0 + #define NVM_CFG1_PORT_MODULE_RS0_NA 0x0 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO0 0x1 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO1 0x2 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO2 0x3 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO3 0x4 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO4 0x5 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO5 0x6 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO6 0x7 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO7 0x8 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO8 0x9 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO9 0xA + #define NVM_CFG1_PORT_MODULE_RS0_GPIO10 0xB + #define NVM_CFG1_PORT_MODULE_RS0_GPIO11 0xC + #define NVM_CFG1_PORT_MODULE_RS0_GPIO12 0xD + #define NVM_CFG1_PORT_MODULE_RS0_GPIO13 0xE + #define NVM_CFG1_PORT_MODULE_RS0_GPIO14 0xF + #define NVM_CFG1_PORT_MODULE_RS0_GPIO15 0x10 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO16 0x11 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO17 0x12 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO18 0x13 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO19 0x14 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO20 0x15 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO21 0x16 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO22 0x17 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO23 0x18 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO24 0x19 + #define NVM_CFG1_PORT_MODULE_RS0_GPIO25 0x1A + #define NVM_CFG1_PORT_MODULE_RS0_GPIO26 0x1B + #define NVM_CFG1_PORT_MODULE_RS0_GPIO27 0x1C + #define NVM_CFG1_PORT_MODULE_RS0_GPIO28 0x1D + #define NVM_CFG1_PORT_MODULE_RS0_GPIO29 0x1E + #define NVM_CFG1_PORT_MODULE_RS0_GPIO30 0x1F + #define NVM_CFG1_PORT_MODULE_RS0_GPIO31 0x20 + /* Define for GPIO mapping of SFP Rate Select 1 */ + #define NVM_CFG1_PORT_MODULE_RS1_MASK 0x0000FF00 + #define NVM_CFG1_PORT_MODULE_RS1_OFFSET 8 + #define NVM_CFG1_PORT_MODULE_RS1_NA 0x0 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO0 0x1 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO1 0x2 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO2 0x3 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO3 0x4 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO4 0x5 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO5 0x6 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO6 0x7 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO7 0x8 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO8 0x9 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO9 0xA + #define NVM_CFG1_PORT_MODULE_RS1_GPIO10 0xB + #define NVM_CFG1_PORT_MODULE_RS1_GPIO11 0xC + #define NVM_CFG1_PORT_MODULE_RS1_GPIO12 0xD + #define NVM_CFG1_PORT_MODULE_RS1_GPIO13 0xE + #define NVM_CFG1_PORT_MODULE_RS1_GPIO14 0xF + #define NVM_CFG1_PORT_MODULE_RS1_GPIO15 0x10 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO16 0x11 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO17 0x12 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO18 0x13 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO19 0x14 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO20 0x15 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO21 0x16 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO22 0x17 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO23 0x18 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO24 0x19 + #define NVM_CFG1_PORT_MODULE_RS1_GPIO25 0x1A + #define NVM_CFG1_PORT_MODULE_RS1_GPIO26 0x1B + #define NVM_CFG1_PORT_MODULE_RS1_GPIO27 0x1C + #define NVM_CFG1_PORT_MODULE_RS1_GPIO28 0x1D + #define NVM_CFG1_PORT_MODULE_RS1_GPIO29 0x1E + #define NVM_CFG1_PORT_MODULE_RS1_GPIO30 0x1F + #define NVM_CFG1_PORT_MODULE_RS1_GPIO31 0x20 + /* Define for GPIO mapping of SFP Module TX Fault */ + #define NVM_CFG1_PORT_MODULE_TX_FAULT_MASK 0x00FF0000 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_OFFSET 16 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_NA 0x0 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO0 0x1 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO1 0x2 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO2 0x3 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO3 0x4 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO4 0x5 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO5 0x6 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO6 0x7 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO7 0x8 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO8 0x9 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO9 0xA + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO10 0xB + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO11 0xC + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO12 0xD + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO13 0xE + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO14 0xF + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO15 0x10 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO16 0x11 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO17 0x12 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO18 0x13 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO19 0x14 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO20 0x15 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO21 0x16 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO22 0x17 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO23 0x18 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO24 0x19 + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO25 0x1A + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO26 0x1B + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO27 0x1C + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO28 0x1D + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO29 0x1E + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO30 0x1F + #define NVM_CFG1_PORT_MODULE_TX_FAULT_GPIO31 0x20 + /* Define for GPIO mapping of QSFP Reset signal */ + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_MASK 0xFF000000 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_OFFSET 24 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_NA 0x0 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO0 0x1 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO1 0x2 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO2 0x3 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO3 0x4 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO4 0x5 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO5 0x6 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO6 0x7 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO7 0x8 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO8 0x9 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO9 0xA + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO10 0xB + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO11 0xC + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO12 0xD + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO13 0xE + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO14 0xF + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO15 0x10 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO16 0x11 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO17 0x12 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO18 0x13 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO19 0x14 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO20 0x15 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO21 0x16 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO22 0x17 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO23 0x18 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO24 0x19 + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO25 0x1A + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO26 0x1B + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO27 0x1C + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO28 0x1D + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO29 0x1E + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO30 0x1F + #define NVM_CFG1_PORT_QSFP_MODULE_RESET_GPIO31 0x20 + u32 port_generic_cont_02; /* 0x9C */ + /* Define for GPIO mapping of QSFP Transceiver LP mode */ + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_MASK 0x000000FF + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_OFFSET 0 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_NA 0x0 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO0 0x1 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO1 0x2 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO2 0x3 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO3 0x4 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO4 0x5 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO5 0x6 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO6 0x7 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO7 0x8 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO8 0x9 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO9 0xA + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO10 0xB + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO11 0xC + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO12 0xD + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO13 0xE + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO14 0xF + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO15 0x10 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO16 0x11 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO17 0x12 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO18 0x13 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO19 0x14 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO20 0x15 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO21 0x16 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO22 0x17 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO23 0x18 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO24 0x19 + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO25 0x1A + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO26 0x1B + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO27 0x1C + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO28 0x1D + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO29 0x1E + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO30 0x1F + #define NVM_CFG1_PORT_QSFP_MODULE_LP_MODE_GPIO31 0x20 + /* Define for GPIO mapping of Transceiver Power Enable */ + #define NVM_CFG1_PORT_MODULE_POWER_MASK 0x0000FF00 + #define NVM_CFG1_PORT_MODULE_POWER_OFFSET 8 + #define NVM_CFG1_PORT_MODULE_POWER_NA 0x0 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO0 0x1 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO1 0x2 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO2 0x3 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO3 0x4 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO4 0x5 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO5 0x6 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO6 0x7 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO7 0x8 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO8 0x9 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO9 0xA + #define NVM_CFG1_PORT_MODULE_POWER_GPIO10 0xB + #define NVM_CFG1_PORT_MODULE_POWER_GPIO11 0xC + #define NVM_CFG1_PORT_MODULE_POWER_GPIO12 0xD + #define NVM_CFG1_PORT_MODULE_POWER_GPIO13 0xE + #define NVM_CFG1_PORT_MODULE_POWER_GPIO14 0xF + #define NVM_CFG1_PORT_MODULE_POWER_GPIO15 0x10 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO16 0x11 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO17 0x12 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO18 0x13 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO19 0x14 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO20 0x15 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO21 0x16 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO22 0x17 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO23 0x18 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO24 0x19 + #define NVM_CFG1_PORT_MODULE_POWER_GPIO25 0x1A + #define NVM_CFG1_PORT_MODULE_POWER_GPIO26 0x1B + #define NVM_CFG1_PORT_MODULE_POWER_GPIO27 0x1C + #define NVM_CFG1_PORT_MODULE_POWER_GPIO28 0x1D + #define NVM_CFG1_PORT_MODULE_POWER_GPIO29 0x1E + #define NVM_CFG1_PORT_MODULE_POWER_GPIO30 0x1F + #define NVM_CFG1_PORT_MODULE_POWER_GPIO31 0x20 + /* Define for LASI Mapping of Interrupt from module or PHY */ + #define NVM_CFG1_PORT_LASI_INTR_IN_MASK 0x000F0000 + #define NVM_CFG1_PORT_LASI_INTR_IN_OFFSET 16 + #define NVM_CFG1_PORT_LASI_INTR_IN_NA 0x0 + #define NVM_CFG1_PORT_LASI_INTR_IN_LASI0 0x1 + #define NVM_CFG1_PORT_LASI_INTR_IN_LASI1 0x2 + #define NVM_CFG1_PORT_LASI_INTR_IN_LASI2 0x3 + #define NVM_CFG1_PORT_LASI_INTR_IN_LASI3 0x4 + u32 reserved[110]; /* 0xA0 */ }; struct nvm_cfg1_func { @@ -1874,7 +2498,6 @@ struct nvm_cfg1_func { #define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0 #define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1 #define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2 - #define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000 #define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23 #define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000 @@ -1969,6 +2592,16 @@ struct nvm_cfg1 { /****************************************** * nvm_cfg structs ******************************************/ + +struct board_info { + u16 vendor_id; + u16 eth_did_suffix; + u16 sub_vendor_id; + u16 sub_device_id; + char *board_name; + char *friendly_name; +}; + enum nvm_cfg_sections { NVM_CFG_SECTION_NVM_CFG1, NVM_CFG_SECTION_MAX @@ -1980,4 +2613,260 @@ struct nvm_cfg { struct nvm_cfg1 cfg1; }; +/****************************************** + * nvm_cfg options + ******************************************/ + +#define NVM_CFG_ID_MAC_ADDRESS 1 +#define NVM_CFG_ID_BOARD_SWAP 8 +#define NVM_CFG_ID_MF_MODE 9 +#define NVM_CFG_ID_LED_MODE 10 +#define NVM_CFG_ID_FAN_FAILURE_ENFORCEMENT 11 +#define NVM_CFG_ID_ENGINEERING_CHANGE 12 +#define NVM_CFG_ID_MANUFACTURING_ID 13 +#define NVM_CFG_ID_SERIAL_NUMBER 14 +#define NVM_CFG_ID_PCI_GEN 15 +#define NVM_CFG_ID_BEACON_WOL_ENABLED 16 +#define NVM_CFG_ID_ASPM_SUPPORT 17 +#define NVM_CFG_ID_ROCE_PRIORITY 20 +#define NVM_CFG_ID_ENABLE_WOL_ON_ACPI_PATTERN 22 +#define NVM_CFG_ID_MAGIC_PACKET_WOL 23 +#define NVM_CFG_ID_AVS_MARGIN_LOW_BB 24 +#define NVM_CFG_ID_AVS_MARGIN_HIGH_BB 25 +#define NVM_CFG_ID_DCBX_MODE 26 +#define NVM_CFG_ID_DRV_SPEED_CAPABILITY_MASK 27 +#define NVM_CFG_ID_MFW_SPEED_CAPABILITY_MASK 28 +#define NVM_CFG_ID_DRV_LINK_SPEED 29 +#define NVM_CFG_ID_DRV_FLOW_CONTROL 30 +#define NVM_CFG_ID_MFW_LINK_SPEED 31 +#define NVM_CFG_ID_MFW_FLOW_CONTROL 32 +#define NVM_CFG_ID_OPTIC_MODULE_VENDOR_ENFORCEMENT 33 +#define NVM_CFG_ID_OPTIONAL_LINK_MODES_BB 34 +#define NVM_CFG_ID_MF_VENDOR_DEVICE_ID 37 +#define NVM_CFG_ID_NETWORK_PORT_MODE 38 +#define NVM_CFG_ID_MPS10_RX_LANE_SWAP_BB 39 +#define NVM_CFG_ID_MPS10_TX_LANE_SWAP_BB 40 +#define NVM_CFG_ID_MPS10_RX_LANE_POLARITY_BB 41 +#define NVM_CFG_ID_MPS10_TX_LANE_POLARITY_BB 42 +#define NVM_CFG_ID_MPS25_RX_LANE_SWAP_BB 43 +#define NVM_CFG_ID_MPS25_TX_LANE_SWAP_BB 44 +#define NVM_CFG_ID_MPS25_RX_LANE_POLARITY 45 +#define NVM_CFG_ID_MPS25_TX_LANE_POLARITY 46 +#define NVM_CFG_ID_MPS10_PREEMPHASIS_BB 47 +#define NVM_CFG_ID_MPS10_DRIVER_CURRENT_BB 48 +#define NVM_CFG_ID_MPS10_ENFORCE_TX_FIR_CFG_BB 49 +#define NVM_CFG_ID_MPS25_PREEMPHASIS 50 +#define NVM_CFG_ID_MPS25_DRIVER_CURRENT 51 +#define NVM_CFG_ID_MPS25_ENFORCE_TX_FIR_CFG 52 +#define NVM_CFG_ID_MPS10_CORE_ADDR_BB 53 +#define NVM_CFG_ID_MPS25_CORE_ADDR_BB 54 +#define NVM_CFG_ID_EXTERNAL_PHY_TYPE 55 +#define NVM_CFG_ID_EXTERNAL_PHY_ADDRESS 56 +#define NVM_CFG_ID_SERDES_NET_INTERFACE_BB 57 +#define NVM_CFG_ID_AN_MODE_BB 58 +#define NVM_CFG_ID_PREBOOT_OPROM 59 +#define NVM_CFG_ID_MBA_DELAY_TIME 61 +#define NVM_CFG_ID_MBA_SETUP_HOT_KEY 62 +#define NVM_CFG_ID_MBA_HIDE_SETUP_PROMPT 63 +#define NVM_CFG_ID_PREBOOT_LINK_SPEED 67 +#define NVM_CFG_ID_PREBOOT_BOOT_PROTOCOL 69 +#define NVM_CFG_ID_ENABLE_SRIOV 70 +#define NVM_CFG_ID_ENABLE_ATC 71 +#define NVM_CFG_ID_NUMBER_OF_VFS_PER_PF 74 +#define NVM_CFG_ID_VF_PCI_BAR2_SIZE_K2_E5 75 +#define NVM_CFG_ID_VENDOR_ID 76 +#define NVM_CFG_ID_SUBSYSTEM_VENDOR_ID 78 +#define NVM_CFG_ID_SUBSYSTEM_DEVICE_ID 79 +#define NVM_CFG_ID_VF_PCI_BAR2_SIZE_BB 81 +#define NVM_CFG_ID_BAR1_SIZE 82 +#define NVM_CFG_ID_BAR2_SIZE_BB 83 +#define NVM_CFG_ID_VF_PCI_DEVICE_ID 84 +#define NVM_CFG_ID_MPS10_TXFIR_MAIN_BB 85 +#define NVM_CFG_ID_MPS10_TXFIR_POST_BB 86 +#define NVM_CFG_ID_MPS25_TXFIR_MAIN 87 +#define NVM_CFG_ID_MPS25_TXFIR_POST 88 +#define NVM_CFG_ID_MANUFACTURE_KIT_VERSION 89 +#define NVM_CFG_ID_MANUFACTURE_TIMESTAMP 90 +#define NVM_CFG_ID_PERSONALITY 92 +#define NVM_CFG_ID_FCOE_NODE_WWN_MAC_ADDR 93 +#define NVM_CFG_ID_FCOE_PORT_WWN_MAC_ADDR 94 +#define NVM_CFG_ID_BANDWIDTH_WEIGHT 95 +#define NVM_CFG_ID_MAX_BANDWIDTH 96 +#define NVM_CFG_ID_PAUSE_ON_HOST_RING 97 +#define NVM_CFG_ID_PCIE_PREEMPHASIS 98 +#define NVM_CFG_ID_LLDP_MAC_ADDRESS 99 +#define NVM_CFG_ID_FCOE_WWN_NODE_PREFIX 100 +#define NVM_CFG_ID_FCOE_WWN_PORT_PREFIX 101 +#define NVM_CFG_ID_LED_SPEED_SELECT 102 +#define NVM_CFG_ID_LED_PORT_SWAP 103 +#define NVM_CFG_ID_AVS_MODE_BB 104 +#define NVM_CFG_ID_OVERRIDE_SECURE_MODE 105 +#define NVM_CFG_ID_AVS_DAC_CODE_BB 106 +#define NVM_CFG_ID_MBI_VERSION 107 +#define NVM_CFG_ID_MBI_DATE 108 +#define NVM_CFG_ID_SMBUS_ADDRESS 109 +#define NVM_CFG_ID_NCSI_PACKAGE_ID 110 +#define NVM_CFG_ID_SIDEBAND_MODE 111 +#define NVM_CFG_ID_SMBUS_MODE 112 +#define NVM_CFG_ID_NCSI 113 +#define NVM_CFG_ID_TRANSCEIVER_MODULE_ABSENT 114 +#define NVM_CFG_ID_I2C_MUX_SELECT_GPIO_BB 115 +#define NVM_CFG_ID_I2C_MUX_SELECT_VALUE_BB 116 +#define NVM_CFG_ID_DEVICE_CAPABILITIES 117 +#define NVM_CFG_ID_ETH_DID_SUFFIX 118 +#define NVM_CFG_ID_FCOE_DID_SUFFIX 119 +#define NVM_CFG_ID_ISCSI_DID_SUFFIX 120 +#define NVM_CFG_ID_DEFAULT_ENABLED_PROTOCOLS 122 +#define NVM_CFG_ID_POWER_DISSIPATED_BB 123 +#define NVM_CFG_ID_POWER_CONSUMED_BB 124 +#define NVM_CFG_ID_AUX_MODE 125 +#define NVM_CFG_ID_PORT_TYPE 126 +#define NVM_CFG_ID_TX_DISABLE 127 +#define NVM_CFG_ID_MAX_LINK_WIDTH 128 +#define NVM_CFG_ID_ASPM_L1_MODE 130 +#define NVM_CFG_ID_ON_CHIP_SENSOR_MODE 131 +#define NVM_CFG_ID_PREBOOT_VLAN_VALUE 132 +#define NVM_CFG_ID_PREBOOT_VLAN 133 +#define NVM_CFG_ID_TEMPERATURE_PERIOD_BETWEEN_CHECKS 134 +#define NVM_CFG_ID_SHUTDOWN_THRESHOLD_TEMPERATURE 135 +#define NVM_CFG_ID_MAX_COUNT_OPER_THRESHOLD 136 +#define NVM_CFG_ID_DEAD_TEMP_TH_TEMPERATURE 137 +#define NVM_CFG_ID_TEMPERATURE_MONITORING_MODE 139 +#define NVM_CFG_ID_AN_25G_50G_OUI 140 +#define NVM_CFG_ID_PLDM_SENSOR_MODE 141 +#define NVM_CFG_ID_EXTERNAL_THERMAL_SENSOR 142 +#define NVM_CFG_ID_EXTERNAL_THERMAL_SENSOR_ADDRESS 143 +#define NVM_CFG_ID_FAN_FAILURE_DURATION 144 +#define NVM_CFG_ID_FEC_FORCE_MODE 145 +#define NVM_CFG_ID_MULTI_NETWORK_MODES_CAPABILITY 146 +#define NVM_CFG_ID_MNM_10G_DRV_SPEED_CAPABILITY_MASK 147 +#define NVM_CFG_ID_MNM_10G_MFW_SPEED_CAPABILITY_MASK 148 +#define NVM_CFG_ID_MNM_10G_DRV_LINK_SPEED 149 +#define NVM_CFG_ID_MNM_10G_MFW_LINK_SPEED 150 +#define NVM_CFG_ID_MNM_10G_PORT_TYPE 151 +#define NVM_CFG_ID_MNM_10G_SERDES_NET_INTERFACE 152 +#define NVM_CFG_ID_MNM_10G_FEC_FORCE_MODE 153 +#define NVM_CFG_ID_MNM_10G_ETH_DID_SUFFIX 154 +#define NVM_CFG_ID_MNM_25G_DRV_SPEED_CAPABILITY_MASK 155 +#define NVM_CFG_ID_MNM_25G_MFW_SPEED_CAPABILITY_MASK 156 +#define NVM_CFG_ID_MNM_25G_DRV_LINK_SPEED 157 +#define NVM_CFG_ID_MNM_25G_MFW_LINK_SPEED 158 +#define NVM_CFG_ID_MNM_25G_PORT_TYPE 159 +#define NVM_CFG_ID_MNM_25G_SERDES_NET_INTERFACE 160 +#define NVM_CFG_ID_MNM_25G_ETH_DID_SUFFIX 161 +#define NVM_CFG_ID_MNM_25G_FEC_FORCE_MODE 162 +#define NVM_CFG_ID_MNM_40G_DRV_SPEED_CAPABILITY_MASK 163 +#define NVM_CFG_ID_MNM_40G_MFW_SPEED_CAPABILITY_MASK 164 +#define NVM_CFG_ID_MNM_40G_DRV_LINK_SPEED 165 +#define NVM_CFG_ID_MNM_40G_MFW_LINK_SPEED 166 +#define NVM_CFG_ID_MNM_40G_PORT_TYPE 167 +#define NVM_CFG_ID_MNM_40G_SERDES_NET_INTERFACE 168 +#define NVM_CFG_ID_MNM_40G_ETH_DID_SUFFIX 169 +#define NVM_CFG_ID_MNM_40G_FEC_FORCE_MODE 170 +#define NVM_CFG_ID_MNM_50G_DRV_SPEED_CAPABILITY_MASK 171 +#define NVM_CFG_ID_MNM_50G_MFW_SPEED_CAPABILITY_MASK 172 +#define NVM_CFG_ID_MNM_50G_DRV_LINK_SPEED 173 +#define NVM_CFG_ID_MNM_50G_MFW_LINK_SPEED 174 +#define NVM_CFG_ID_MNM_50G_PORT_TYPE 175 +#define NVM_CFG_ID_MNM_50G_SERDES_NET_INTERFACE 176 +#define NVM_CFG_ID_MNM_50G_ETH_DID_SUFFIX 177 +#define NVM_CFG_ID_MNM_50G_FEC_FORCE_MODE 178 +#define NVM_CFG_ID_MNM_100G_DRV_SPEED_CAP_MASK_BB 179 +#define NVM_CFG_ID_MNM_100G_MFW_SPEED_CAP_MASK_BB 180 +#define NVM_CFG_ID_MNM_100G_DRV_LINK_SPEED_BB 181 +#define NVM_CFG_ID_MNM_100G_MFW_LINK_SPEED_BB 182 +#define NVM_CFG_ID_MNM_100G_PORT_TYPE_BB 183 +#define NVM_CFG_ID_MNM_100G_SERDES_NET_INTERFACE_BB 184 +#define NVM_CFG_ID_MNM_100G_ETH_DID_SUFFIX_BB 185 +#define NVM_CFG_ID_MNM_100G_FEC_FORCE_MODE_BB 186 +#define NVM_CFG_ID_FUNCTION_HIDE 187 +#define NVM_CFG_ID_BAR2_TOTAL_BUDGET_BB 188 +#define NVM_CFG_ID_CRASH_DUMP_TRIGGER_ENABLE 189 +#define NVM_CFG_ID_MPS25_LANE_SWAP_K2_E5 190 +#define NVM_CFG_ID_BAR2_SIZE_K2_E5 191 +#define NVM_CFG_ID_EXT_PHY_RESET 192 +#define NVM_CFG_ID_EEE_POWER_SAVING_MODE 193 +#define NVM_CFG_ID_OVERRIDE_PCIE_PRESET_EQUAL_BB 194 +#define NVM_CFG_ID_PCIE_PRESET_VALUE_BB 195 +#define NVM_CFG_ID_MAX_MSIX 196 +#define NVM_CFG_ID_NVM_CFG_VERSION 197 +#define NVM_CFG_ID_NVM_CFG_NEW_OPTION_SEQ 198 +#define NVM_CFG_ID_NVM_CFG_REMOVED_OPTION_SEQ 199 +#define NVM_CFG_ID_NVM_CFG_UPDATED_VALUE_SEQ 200 +#define NVM_CFG_ID_EXTENDED_SERIAL_NUMBER 201 +#define NVM_CFG_ID_RDMA_ENABLEMENT 202 +#define NVM_CFG_ID_MAX_CONT_OPERATING_TEMP 203 +#define NVM_CFG_ID_RUNTIME_PORT_SWAP_GPIO 204 +#define NVM_CFG_ID_RUNTIME_PORT_SWAP_MAP 205 +#define NVM_CFG_ID_THERMAL_EVENT_GPIO 206 +#define NVM_CFG_ID_I2C_INTERRUPT_GPIO 207 +#define NVM_CFG_ID_DCI_SUPPORT 208 +#define NVM_CFG_ID_PCIE_VDM_ENABLED 209 +#define NVM_CFG_ID_OEM1_NUMBER 210 +#define NVM_CFG_ID_OEM2_NUMBER 211 +#define NVM_CFG_ID_FEC_AN_MODE_K2_E5 212 +#define NVM_CFG_ID_NPAR_ENABLED_PROTOCOL 213 +#define NVM_CFG_ID_MPS25_ACTIVE_TXFIR_PRE 214 +#define NVM_CFG_ID_MPS25_ACTIVE_TXFIR_MAIN 215 +#define NVM_CFG_ID_MPS25_ACTIVE_TXFIR_POST 216 +#define NVM_CFG_ID_ALOM_FAN_ON_AUX_GPIO 217 +#define NVM_CFG_ID_ALOM_FAN_ON_AUX_VALUE 218 +#define NVM_CFG_ID_SLOT_ID_GPIO 219 +#define NVM_CFG_ID_PMBUS_SCL_GPIO 220 +#define NVM_CFG_ID_PMBUS_SDA_GPIO 221 +#define NVM_CFG_ID_RESET_ON_LAN 222 +#define NVM_CFG_ID_NCSI_PACKAGE_ID_IO 223 +#define NVM_CFG_ID_TX_RX_EQ_25G_HLPC 224 +#define NVM_CFG_ID_TX_RX_EQ_25G_LLPC 225 +#define NVM_CFG_ID_TX_RX_EQ_25G_AC 226 +#define NVM_CFG_ID_TX_RX_EQ_10G_PC 227 +#define NVM_CFG_ID_TX_RX_EQ_10G_AC 228 +#define NVM_CFG_ID_TX_RX_EQ_1G 229 +#define NVM_CFG_ID_TX_RX_EQ_25G_BT 230 +#define NVM_CFG_ID_TX_RX_EQ_10G_BT 231 +#define NVM_CFG_ID_PF_MAPPING 232 +#define NVM_CFG_ID_RECOVERY_MODE 234 +#define NVM_CFG_ID_PHY_MODULE_DEAD_TEMP_TH 235 +#define NVM_CFG_ID_PHY_MODULE_ALOM_FAN_ON_TEMP_TH 236 +#define NVM_CFG_ID_PREBOOT_DEBUG_MODE_STD 237 +#define NVM_CFG_ID_PREBOOT_DEBUG_MODE_EXT 238 +#define NVM_CFG_ID_SMARTLINQ_MODE 239 +#define NVM_CFG_ID_PREBOOT_LINK_UP_DELAY 242 +#define NVM_CFG_ID_VOLTAGE_REGULATOR_TYPE 243 +#define NVM_CFG_ID_MAIN_CLOCK_FREQUENCY 245 +#define NVM_CFG_ID_MAC_CLOCK_FREQUENCY 246 +#define NVM_CFG_ID_STORM_CLOCK_FREQUENCY 247 +#define NVM_CFG_ID_PCIE_RELAXED_ORDERING 248 +#define NVM_CFG_ID_EXT_PHY_MDI_PAIR_SWAP 249 +#define NVM_CFG_ID_UID_LED_MODE_MASK 250 +#define NVM_CFG_ID_NCSI_AUX_LINK 251 +#define NVM_CFG_ID_SMARTAN_FEC_OVERRIDE 272 +#define NVM_CFG_ID_LLDP_DISABLE 273 +#define NVM_CFG_ID_SHORT_PERST_PROTECTION_K2_E5 274 +#define NVM_CFG_ID_TRANSCEIVER_RATE_SELECT_0 275 +#define NVM_CFG_ID_TRANSCEIVER_RATE_SELECT_1 276 +#define NVM_CFG_ID_TRANSCEIVER_MODULE_TX_FAULT 277 +#define NVM_CFG_ID_TRANSCEIVER_QSFP_MODULE_RESET 278 +#define NVM_CFG_ID_TRANSCEIVER_QSFP_LP_MODE 279 +#define NVM_CFG_ID_TRANSCEIVER_POWER_ENABLE 280 +#define NVM_CFG_ID_LASI_INTERRUPT_INPUT 281 +#define NVM_CFG_ID_EXT_PHY_PGOOD_INPUT 282 +#define NVM_CFG_ID_TRACE_LEVEL 283 +#define NVM_CFG_ID_TRACE_MODULES 284 +#define NVM_CFG_ID_EMULATED_TMP421 285 +#define NVM_CFG_ID_WARNING_TEMPERATURE_GPIO 286 +#define NVM_CFG_ID_WARNING_TEMPERATURE_THRESHOLD 287 +#define NVM_CFG_ID_PERST_INDICATION_GPIO 288 +#define NVM_CFG_ID_PCIE_CLASS_CODE_FCOE_K2_E5 289 +#define NVM_CFG_ID_PCIE_CLASS_CODE_ISCSI_K2_E5 290 +#define NVM_CFG_ID_NUMBER_OF_PROVISIONED_MAC 291 +#define NVM_CFG_ID_NUMBER_OF_PROVISIONED_VF_MAC 292 +#define NVM_CFG_ID_PROVISIONED_BMC_MAC 293 +#define NVM_CFG_ID_OVERRIDE_AGC_THRESHOLD_K2 294 +#define NVM_CFG_ID_WARNING_TEMPERATURE_DELTA 295 +#define NVM_CFG_ID_ALOM_FAN_ON_AUX_DELTA 296 +#define NVM_CFG_ID_DEAD_TEMP_TH_DELTA 297 +#define NVM_CFG_ID_PHY_MODULE_WARNING_TEMP_TH 298 +#define NVM_CFG_ID_DISABLE_PLDM 299 +#define NVM_CFG_ID_DISABLE_MCTP_OEM 300 #endif /* NVM_CFG_H */ -- 2.18.0