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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: a247d5cb-8d53-4b64-79f5-08d7463a5ea0 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Oct 2019 06:41:20.7756 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: yxo5xm1PKssHdevdPZKWJBL1IzKVG/3WaCHeZYpOH1/ghGAl7zDgbOffcBgYyF3SK2wIidLvj6Jqx7WXmGnJbpwrtZyQwMaIrShTwd0GpdM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB3375 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-01_03:2019-09-30,2019-10-01 signatures=0 Subject: [dpdk-dev] [PATCH v7 1/8] crypto/nitrox: add Nitrox PMD library X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add bare minimum Nitrox PMD library which handles pci probe, remove and hardware initialization. Add logs, documentation and update maintainers file. Signed-off-by: Nagadheeraj Rottela --- MAINTAINERS | 7 ++ config/common_base | 5 + doc/guides/cryptodevs/index.rst | 1 + doc/guides/cryptodevs/nitrox.rst | 30 ++++++ drivers/crypto/Makefile | 1 + drivers/crypto/meson.build | 4 +- drivers/crypto/nitrox/Makefile | 30 ++++++ drivers/crypto/nitrox/meson.build | 15 +++ drivers/crypto/nitrox/nitrox_csr.h | 28 ++++++ drivers/crypto/nitrox/nitrox_device.c | 111 +++++++++++++++++++= ++++ drivers/crypto/nitrox/nitrox_device.h | 18 ++++ drivers/crypto/nitrox/nitrox_hal.c | 85 +++++++++++++++++ drivers/crypto/nitrox/nitrox_hal.h | 37 ++++++++ drivers/crypto/nitrox/nitrox_logs.c | 14 +++ drivers/crypto/nitrox/nitrox_logs.h | 15 +++ drivers/crypto/nitrox/rte_pmd_nitrox_version.map | 3 + mk/rte.app.mk | 1 + 17 files changed, 403 insertions(+), 2 deletions(-) create mode 100644 doc/guides/cryptodevs/nitrox.rst create mode 100644 drivers/crypto/nitrox/Makefile create mode 100644 drivers/crypto/nitrox/meson.build create mode 100644 drivers/crypto/nitrox/nitrox_csr.h create mode 100644 drivers/crypto/nitrox/nitrox_device.c create mode 100644 drivers/crypto/nitrox/nitrox_device.h create mode 100644 drivers/crypto/nitrox/nitrox_hal.c create mode 100644 drivers/crypto/nitrox/nitrox_hal.h create mode 100644 drivers/crypto/nitrox/nitrox_logs.c create mode 100644 drivers/crypto/nitrox/nitrox_logs.h create mode 100644 drivers/crypto/nitrox/rte_pmd_nitrox_version.map diff --git a/MAINTAINERS b/MAINTAINERS index b3d9aaddd..c881fd023 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -963,6 +963,13 @@ F: drivers/crypto/mvsam/ F: doc/guides/cryptodevs/mvsam.rst F: doc/guides/cryptodevs/features/mvsam.ini =20 +Nitrox +M: Nagadheeraj Rottela +M: Srikanth Jampala +F: drivers/crypto/nitrox/ +F: doc/guides/cryptodevs/nitrox.rst +F: doc/guides/cryptodevs/features/nitrox.ini + Null Crypto M: Declan Doherty F: drivers/crypto/null/ diff --git a/config/common_base b/config/common_base index 8ef75c203..92ecb4a68 100644 --- a/config/common_base +++ b/config/common_base @@ -664,6 +664,11 @@ CONFIG_RTE_LIBRTE_PMD_CCP=3Dn CONFIG_RTE_LIBRTE_PMD_MVSAM_CRYPTO=3Dn =20 # +# Compile PMD for NITROX crypto device +# +CONFIG_RTE_LIBRTE_PMD_NITROX=3Dy + +# # Compile generic security library # CONFIG_RTE_LIBRTE_SECURITY=3Dy diff --git a/doc/guides/cryptodevs/index.rst b/doc/guides/cryptodevs/index.= rst index 83610e64f..d1e0d3203 100644 --- a/doc/guides/cryptodevs/index.rst +++ b/doc/guides/cryptodevs/index.rst @@ -21,6 +21,7 @@ Crypto Device Drivers octeontx openssl mvsam + nitrox null scheduler snow3g diff --git a/doc/guides/cryptodevs/nitrox.rst b/doc/guides/cryptodevs/nitro= x.rst new file mode 100644 index 000000000..cb7f92755 --- /dev/null +++ b/doc/guides/cryptodevs/nitrox.rst @@ -0,0 +1,30 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(C) 2019 Marvell International Ltd. + +Marvell NITROX Crypto Poll Mode Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The Nitrox crypto poll mode driver provides support for offloading +cryptographic operations to the NITROX V security processor. Detailed +information about the NITROX V security processor can be obtained here: + +* https://www.marvell.com/security-solutions/nitrox-security-processors/ni= trox-v/ + +Installation +------------ + +For compiling the Nitrox crypto PMD, please check if the +CONFIG_RTE_LIBRTE_PMD_NITROX setting is set to `y` in config/common_base f= ile. + +* ``CONFIG_RTE_LIBRTE_PMD_NITROX=3Dy`` + +Initialization +-------------- + +Nitrox crypto PMD depend on Nitrox kernel PF driver being installed on the +platform. Nitrox PF driver is required to create VF devices which will +be used by the PMD. Each VF device can enable one cryptodev PMD. + +Nitrox kernel PF driver is available as part of CNN55XX-Driver SDK. The SD= K +and it's installation instructions can be obtained from: +`Marvell Technical Documentation Portal `_. diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 009f8443d..7129bcfc9 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -25,5 +25,6 @@ DIRS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) +=3D caam_jr endif # CONFIG_RTE_LIBRTE_PMD_DPAA_SEC endif # CONFIG_RTE_LIBRTE_SECURITY DIRS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) +=3D virtio +DIRS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) +=3D nitrox =20 include $(RTE_SDK)/mk/rte.subdir.mk diff --git a/drivers/crypto/meson.build b/drivers/crypto/meson.build index 83e78860e..1a358ff8b 100644 --- a/drivers/crypto/meson.build +++ b/drivers/crypto/meson.build @@ -2,8 +2,8 @@ # Copyright(c) 2017 Intel Corporation =20 drivers =3D ['aesni_gcm', 'aesni_mb', 'caam_jr', 'ccp', 'dpaa_sec', 'dpaa2= _sec', - 'kasumi', 'mvsam', 'null', 'octeontx', 'openssl', 'qat', 'scheduler', - 'snow3g', 'virtio', 'zuc'] + 'kasumi', 'mvsam', 'nitrox', 'null', 'octeontx', 'openssl', 'qat', + 'scheduler', 'snow3g', 'virtio', 'zuc'] =20 std_deps =3D ['cryptodev'] # cryptodev pulls in all other needed deps config_flag_fmt =3D 'RTE_LIBRTE_@0@_PMD' diff --git a/drivers/crypto/nitrox/Makefile b/drivers/crypto/nitrox/Makefil= e new file mode 100644 index 000000000..7681a6603 --- /dev/null +++ b/drivers/crypto/nitrox/Makefile @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB =3D librte_pmd_nitrox.a + +# build flags +CFLAGS +=3D -O3 +CFLAGS +=3D $(WERROR_FLAGS) +CFLAGS +=3D -DALLOW_EXPERIMENTAL_API + +# library version +LIBABIVER :=3D 1 + +# versioning export map +EXPORT_MAP :=3D rte_pmd_nitrox_version.map + +# external library dependencies +LDLIBS +=3D -lrte_eal -lrte_mbuf -lrte_mempool +LDLIBS +=3D -lrte_pci -lrte_bus_pci +LDLIBS +=3D -lrte_cryptodev + +# library source files +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) +=3D nitrox_device.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) +=3D nitrox_hal.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) +=3D nitrox_logs.c + +include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/crypto/nitrox/meson.build b/drivers/crypto/nitrox/meso= n.build new file mode 100644 index 000000000..ad81f8cd8 --- /dev/null +++ b/drivers/crypto/nitrox/meson.build @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(C) 2019 Marvell International Ltd. + +if not is_linux + build =3D false + reason =3D 'only supported on Linux' +endif + +deps +=3D ['bus_pci'] +allow_experimental_apis =3D true +sources =3D files( + 'nitrox_device.c', + 'nitrox_hal.c', + 'nitrox_logs.c', + ) diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nit= rox_csr.h new file mode 100644 index 000000000..879104515 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_csr.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_CSR_H_ +#define _NITROX_CSR_H_ + +#include +#include + +#define CSR_DELAY 30 + +/* AQM Virtual Function Registers */ +#define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000)) + +static inline uint64_t +nitrox_read_csr(uint8_t *bar_addr, uint64_t offset) +{ + return rte_read64(bar_addr + offset); +} + +static inline void +nitrox_write_csr(uint8_t *bar_addr, uint64_t offset, uint64_t value) +{ + rte_write64(value, (bar_addr + offset)); +} + +#endif /* _NITROX_CSR_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_device.c b/drivers/crypto/nitrox/= nitrox_device.c new file mode 100644 index 000000000..a73528211 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_device.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include + +#include "nitrox_device.h" +#include "nitrox_hal.h" + +#define PCI_VENDOR_ID_CAVIUM 0x177d +#define NITROX_V_PCI_VF_DEV_ID 0x13 + +TAILQ_HEAD(ndev_list, nitrox_device); +static struct ndev_list ndev_list =3D TAILQ_HEAD_INITIALIZER(ndev_list); + +static struct nitrox_device * +ndev_allocate(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + ndev =3D rte_zmalloc_socket("nitrox device", sizeof(*ndev), + RTE_CACHE_LINE_SIZE, + pdev->device.numa_node); + if (!ndev) + return NULL; + + TAILQ_INSERT_TAIL(&ndev_list, ndev, next); + return ndev; +} + +static void +ndev_init(struct nitrox_device *ndev, struct rte_pci_device *pdev) +{ + enum nitrox_vf_mode vf_mode; + + ndev->pdev =3D pdev; + ndev->bar_addr =3D pdev->mem_resource[0].addr; + vf_mode =3D vf_get_vf_config_mode(ndev->bar_addr); + ndev->nr_queues =3D vf_config_mode_to_nr_queues(vf_mode); +} + +static struct nitrox_device * +find_ndev(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + TAILQ_FOREACH(ndev, &ndev_list, next) + if (ndev->pdev =3D=3D pdev) + return ndev; + + return NULL; +} + +static void +ndev_release(struct nitrox_device *ndev) +{ + if (!ndev) + return; + + TAILQ_REMOVE(&ndev_list, ndev, next); + rte_free(ndev); +} + +static int +nitrox_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, + struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + /* Nitrox CSR space */ + if (!pdev->mem_resource[0].addr) + return -EINVAL; + + ndev =3D ndev_allocate(pdev); + if (!ndev) + return -ENOMEM; + + ndev_init(ndev, pdev); + return 0; +} + +static int +nitrox_pci_remove(struct rte_pci_device *pdev) +{ + struct nitrox_device *ndev; + + ndev =3D find_ndev(pdev); + if (!ndev) + return -ENODEV; + + ndev_release(ndev); + return 0; +} + +static struct rte_pci_id pci_id_nitrox_map[] =3D { + { + /* Nitrox 5 VF */ + RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, NITROX_V_PCI_VF_DEV_ID) + }, + {.device_id =3D 0}, +}; + +static struct rte_pci_driver nitrox_pmd =3D { + .id_table =3D pci_id_nitrox_map, + .drv_flags =3D RTE_PCI_DRV_NEED_MAPPING, + .probe =3D nitrox_pci_probe, + .remove =3D nitrox_pci_remove, +}; + +RTE_PMD_REGISTER_PCI(nitrox, nitrox_pmd); +RTE_PMD_REGISTER_PCI_TABLE(nitrox, pci_id_nitrox_map); diff --git a/drivers/crypto/nitrox/nitrox_device.h b/drivers/crypto/nitrox/= nitrox_device.h new file mode 100644 index 000000000..0d0167de2 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_device.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_DEVICE_H_ +#define _NITROX_DEVICE_H_ + +#include +#include + +struct nitrox_device { + TAILQ_ENTRY(nitrox_device) next; + struct rte_pci_device *pdev; + uint8_t *bar_addr; + uint16_t nr_queues; +}; + +#endif /* _NITROX_DEVICE_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_hal.c b/drivers/crypto/nitrox/nit= rox_hal.c new file mode 100644 index 000000000..ed1882016 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_hal.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include +#include +#include +#include + +#include "nitrox_hal.h" +#include "nitrox_csr.h" + +#define MAX_VF_QUEUES 8 +#define MAX_PF_QUEUES 64 + +int +vf_get_vf_config_mode(uint8_t *bar_addr) +{ + union aqmq_qsz aqmq_qsz; + uint64_t reg_addr; + int q, vf_mode; + + aqmq_qsz.u64 =3D 0; + aqmq_qsz.s.host_queue_size =3D 0xDEADBEEF; + reg_addr =3D AQMQ_QSZX(0); + nitrox_write_csr(bar_addr, reg_addr, aqmq_qsz.u64); + rte_delay_us_block(CSR_DELAY); + + aqmq_qsz.u64 =3D 0; + for (q =3D 1; q < MAX_VF_QUEUES; q++) { + reg_addr =3D AQMQ_QSZX(q); + aqmq_qsz.u64 =3D nitrox_read_csr(bar_addr, reg_addr); + if (aqmq_qsz.s.host_queue_size =3D=3D 0xDEADBEEF) + break; + } + + switch (q) { + case 1: + vf_mode =3D NITROX_MODE_VF128; + break; + case 2: + vf_mode =3D NITROX_MODE_VF64; + break; + case 4: + vf_mode =3D NITROX_MODE_VF32; + break; + case 8: + vf_mode =3D NITROX_MODE_VF16; + break; + default: + vf_mode =3D 0; + break; + } + + return vf_mode; +} + +int +vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode) +{ + int nr_queues; + + switch (vf_mode) { + case NITROX_MODE_PF: + nr_queues =3D MAX_PF_QUEUES; + break; + case NITROX_MODE_VF16: + nr_queues =3D 8; + break; + case NITROX_MODE_VF32: + nr_queues =3D 4; + break; + case NITROX_MODE_VF64: + nr_queues =3D 2; + break; + case NITROX_MODE_VF128: + nr_queues =3D 1; + break; + default: + nr_queues =3D 0; + break; + } + + return nr_queues; +} diff --git a/drivers/crypto/nitrox/nitrox_hal.h b/drivers/crypto/nitrox/nit= rox_hal.h new file mode 100644 index 000000000..6184211a5 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_hal.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_HAL_H_ +#define _NITROX_HAL_H_ + +#include +#include + +#include "nitrox_csr.h" + +union aqmq_qsz { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER =3D=3D RTE_BIG_ENDIAN + uint64_t raz : 32; + uint64_t host_queue_size : 32; +#else + uint64_t host_queue_size : 32; + uint64_t raz : 32; +#endif + } s; +}; + +enum nitrox_vf_mode { + NITROX_MODE_PF =3D 0x0, + NITROX_MODE_VF16 =3D 0x1, + NITROX_MODE_VF32 =3D 0x2, + NITROX_MODE_VF64 =3D 0x3, + NITROX_MODE_VF128 =3D 0x4, +}; + +int vf_get_vf_config_mode(uint8_t *bar_addr); +int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode); + +#endif /* _NITROX_HAL_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_logs.c b/drivers/crypto/nitrox/ni= trox_logs.c new file mode 100644 index 000000000..007056cb4 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_logs.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#include + +int nitrox_logtype; + +RTE_INIT(nitrox_init_log) +{ + nitrox_logtype =3D rte_log_register("pmd.crypto.nitrox"); + if (nitrox_logtype >=3D 0) + rte_log_set_level(nitrox_logtype, RTE_LOG_NOTICE); +} diff --git a/drivers/crypto/nitrox/nitrox_logs.h b/drivers/crypto/nitrox/ni= trox_logs.h new file mode 100644 index 000000000..50e52f396 --- /dev/null +++ b/drivers/crypto/nitrox/nitrox_logs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2019 Marvell International Ltd. + */ + +#ifndef _NITROX_LOGS_H_ +#define _NITROX_LOGS_H_ + +#define LOG_PREFIX "NITROX: " +#define NITROX_LOG(level, fmt, args...) \ + rte_log(RTE_LOG_ ## level, nitrox_logtype, \ + LOG_PREFIX "%s:%d " fmt, __func__, __LINE__, ## args) + +extern int nitrox_logtype; + +#endif /* _NITROX_LOGS_H_ */ diff --git a/drivers/crypto/nitrox/rte_pmd_nitrox_version.map b/drivers/cry= pto/nitrox/rte_pmd_nitrox_version.map new file mode 100644 index 000000000..0a539ae48 --- /dev/null +++ b/drivers/crypto/nitrox/rte_pmd_nitrox_version.map @@ -0,0 +1,3 @@ +DPDK_19.08 { + local: *; +}; diff --git a/mk/rte.app.mk b/mk/rte.app.mk index ba5c39e01..fb496692b 100644 --- a/mk/rte.app.mk +++ b/mk/rte.app.mk @@ -279,6 +279,7 @@ _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CAAM_JR) +=3D -lrte_p= md_caam_jr endif # CONFIG_RTE_LIBRTE_DPAA_BUS endif # CONFIG_RTE_LIBRTE_SECURITY _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_VIRTIO_CRYPTO) +=3D -lrte_pmd_virtio_crypt= o +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_NITROX) +=3D -lrte_pmd_nitrox endif # CONFIG_RTE_LIBRTE_CRYPTODEV =20 ifeq ($(CONFIG_RTE_LIBRTE_COMPRESSDEV),y) --=20 2.13.6