From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id DE060A00BE; Thu, 31 Oct 2019 03:05:11 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 07C1F1C19F; Thu, 31 Oct 2019 03:05:10 +0100 (CET) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id DC5CA1C000 for ; Thu, 31 Oct 2019 03:05:07 +0100 (CET) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 19:05:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,249,1569308400"; d="scan'208";a="194168634" Received: from yexl-server.sh.intel.com (HELO localhost) ([10.67.117.17]) by orsmga008.jf.intel.com with ESMTP; 30 Oct 2019 19:05:05 -0700 Date: Thu, 31 Oct 2019 10:01:29 +0800 From: Ye Xiaolong To: Andy Pei Cc: dev@dpdk.org, rosen.xu@intel.com, tianfei.zhang@intel.com, ferruh.yigit@intel.com Message-ID: <20191031020129.GJ11315@intel.com> References: <1571917119-149534-2-git-send-email-andy.pei@intel.com> <1572252623-96127-1-git-send-email-andy.pei@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1572252623-96127-1-git-send-email-andy.pei@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [PATCH v14 00/19] add PCIe AER disable and IRQ support for ipn3ke X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 10/28, Andy Pei wrote: >This patch set adds PCIe AER disable and FPGA interrupt support for >ipn3ke. It also provides a small rework for port bonding between FPGA >line side port and I40e PF port. > >What is the PCI Express AER(Advanced Error Reporting)? >Advanced Error Reporting capability is implemented with a PCI Express >advanced error reporting extended capability structure providing more >robust error reporting. It's also one of PCI Express error reporting >paradigms. AER is supported by most of PCIe devices. > >In PAC N3000 card, some uncertainty errors will cause FPGA reload, >such as temperature is higher than threshold. From Software point of >view, FPGA reload means FPGA unplug and plug. For avoiding system >crash we need to clear AER register before these errors occur. > >Currently PAC N3000 card FME and AFU all provide interrupts, in ifpga >rawdev driver, we implement a FME interrupt function to notify errors >reported by FME. Besides this, OPAE share code also provide a common >AFU interrupt API for users to register their own interrupt functions. > Series applied to dpdk-next-net-intel. Thanks.