From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 06801A04B5; Mon, 2 Dec 2019 09:06:40 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C01E41C117; Mon, 2 Dec 2019 08:59:19 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 4BB2E1BFBB for ; Mon, 2 Dec 2019 08:59:09 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Dec 2019 23:58:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,268,1571727600"; d="scan'208";a="207993620" Received: from dpdk_yexl_af_xdp.sh.intel.com ([10.67.119.186]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2019 23:58:55 -0800 From: Xiaolong Ye To: Beilei Xing , Qi Zhang Cc: dev@dpdk.org, Xiaolong Ye , Doug Dziggel Date: Mon, 2 Dec 2019 15:49:13 +0800 Message-Id: <20191202074935.97629-48-xiaolong.ye@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202074935.97629-1-xiaolong.ye@intel.com> References: <20191202074935.97629-1-xiaolong.ye@intel.com> Subject: [dpdk-dev] [PATCH 47/69] net/i40e/base: add Flow Director defines X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add defines for creating Flow Director flows as defined in datasheet section 7.1.5.4 for field vectors. Signed-off-by: Doug Dziggel Reviewed-by: Brandeburg Jesse Reviewed-by: Kirsher Jeffrey T Reviewed-by: Michael Alice Signed-off-by: Xiaolong Ye --- drivers/net/i40e/base/i40e_register.h | 81 +++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h index 6804aba51..f6b0cd585 100644 --- a/drivers/net/i40e/base/i40e_register.h +++ b/drivers/net/i40e/base/i40e_register.h @@ -5286,6 +5286,87 @@ #define I40E_GLGEN_STAT_HALT 0x00390000 /* Reset: CORER */ #define I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT 0 #define I40E_GLGEN_STAT_HALT_HALT_CELLS_MASK I40E_MASK(0x3FFFFFFF, I40E_GLGEN_STAT_HALT_HALT_CELLS_SHIFT) +/* Flow Director */ +#define I40E_REG_INSET_L2_DMAC_SHIFT 60 +#define I40E_REG_INSET_L2_DMAC_MASK I40E_MASK(0xEULL, I40E_REG_INSET_L2_DMAC_SHIFT) +#define I40E_REG_INSET_L2_SMAC_SHIFT 56 +#define I40E_REG_INSET_L2_SMAC_MASK I40E_MASK(0x1CULL, I40E_REG_INSET_L2_SMAC_SHIFT) +#define I40E_REG_INSET_L2_OUTER_VLAN_SHIFT 26 +#define I40E_REG_INSET_L2_OUTER_VLAN_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L2_OUTER_VLAN_SHIFT) +#define I40E_REG_INSET_L2_INNER_VLAN_SHIFT 55 +#define I40E_REG_INSET_L2_INNER_VLAN_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L2_INNER_VLAN_SHIFT) +#define I40E_REG_INSET_TUNNEL_VLAN_SHIFT 56 +#define I40E_REG_INSET_TUNNEL_VLAN_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_TUNNEL_VLAN_SHIFT) +#define I40E_REG_INSET_L3_SRC_IP4_SHIFT 47 +#define I40E_REG_INSET_L3_SRC_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_L3_SRC_IP4_SHIFT) +#define I40E_REG_INSET_L3_DST_IP4_SHIFT 35 +#define I40E_REG_INSET_L3_DST_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_L3_DST_IP4_SHIFT) +#define I40E_X722_REG_INSET_L3_SRC_IP4_SHIFT 49 +#define I40E_X722_REG_INSET_L3_SRC_IP4_MASK I40E_MASK(0x3ULL, I40E_X722_REG_INSET_L3_SRC_IP4_SHIFT) +#define I40E_X722_REG_INSET_L3_DST_IP4_SHIFT 41 +#define I40E_X722_REG_INSET_L3_DST_IP4_MASK I40E_MASK(0x3ULL, I40E_X722_REG_INSET_L3_DST_IP4_SHIFT) +#define I40E_X722_REG_INSET_L3_IP4_PROTO_SHIFT 52 +#define I40E_X722_REG_INSET_L3_IP4_PROTO_MASK I40E_MASK(0x1ULL, I40E_X722_REG_INSET_L3_IP4_PROTO_SHIFT) +#define I40E_X722_REG_INSET_L3_IP4_TTL_SHIFT 52 +#define I40E_X722_REG_INSET_L3_IP4_TTL_MASK I40E_MASK(0x1ULL, I40E_X722_REG_INSET_L3_IP4_TTL_SHIFT) +#define I40E_REG_INSET_L3_IP4_TOS_SHIFT 54 +#define I40E_REG_INSET_L3_IP4_TOS_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP4_TOS_SHIFT) +#define I40E_REG_INSET_L3_IP4_PROTO_SHIFT 50 +#define I40E_REG_INSET_L3_IP4_PROTO_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP4_PROTO_SHIFT) +#define I40E_REG_INSET_L3_IP4_TTL_SHIFT 50 +#define I40E_REG_INSET_L3_IP4_TTL_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP4_TTL_SHIFT) +#define I40E_REG_INSET_L3_SRC_IP6_SHIFT 43 +#define I40E_REG_INSET_L3_SRC_IP6_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_L3_SRC_IP6_SHIFT) +#define I40E_REG_INSET_L3_DST_IP6_SHIFT 35 +#define I40E_REG_INSET_L3_DST_IP6_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_L3_DST_IP6_SHIFT) +#define I40E_REG_INSET_L3_IP6_TC_SHIFT 54 +#define I40E_REG_INSET_L3_IP6_TC_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP6_TC_SHIFT) +#define I40E_REG_INSET_L3_IP6_NEXT_HDR_SHIFT 51 +#define I40E_REG_INSET_L3_IP6_NEXT_HDR_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP6_NEXT_HDR_SHIFT) +#define I40E_REG_INSET_L3_IP6_HOP_LIMIT_SHIFT 51 +#define I40E_REG_INSET_L3_IP6_HOP_LIMIT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L3_IP6_HOP_LIMIT_SHIFT) +#define I40E_REG_INSET_L4_SRC_PORT_SHIFT 34 +#define I40E_REG_INSET_L4_SRC_PORT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L4_SRC_PORT_SHIFT) +#define I40E_REG_INSET_L4_DST_PORT_SHIFT 33 +#define I40E_REG_INSET_L4_DST_PORT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_L4_DST_PORT_SHIFT) +#define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG_SHIFT 31 +#define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG_SHIFT) +#define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC_SHIFT 22 +#define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC_MASK I40E_MASK(0x7ULL, I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC_SHIFT) +#define I40E_REG_INSET_TUNNEL_L2_INNER_SRC_MAC_SHIFT 11 +#define I40E_REG_INSET_TUNNEL_L2_INNER_SRC_MAC_MASK I40E_MASK(0x7ULL, I40E_REG_INSET_TUNNEL_L2_INNER_SRC_MAC_SHIFT) +#define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT_SHIFT 21 +#define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT_SHIFT) +#define I40E_REG_INSET_TUNNEL_ID_SHIFT 18 +#define I40E_REG_INSET_TUNNEL_ID_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_TUNNEL_ID_SHIFT) +#define I40E_REG_INSET_LAST_ETHER_TYPE_SHIFT 14 +#define I40E_REG_INSET_LAST_ETHER_TYPE_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_LAST_ETHER_TYPE_SHIFT) +#define I40E_REG_INSET_TUNNEL_L3_SRC_IP4_SHIFT 8 +#define I40E_REG_INSET_TUNNEL_L3_SRC_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_TUNNEL_L3_SRC_IP4_SHIFT) +#define I40E_REG_INSET_TUNNEL_L3_DST_IP4_SHIFT 6 +#define I40E_REG_INSET_TUNNEL_L3_DST_IP4_MASK I40E_MASK(0x3ULL, I40E_REG_INSET_TUNNEL_L3_DST_IP4_SHIFT) +#define I40E_REG_INSET_TUNNEL_L3_DST_IP6_SHIFT 6 +#define I40E_REG_INSET_TUNNEL_L3_DST_IP6_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_TUNNEL_L3_DST_IP6_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD1_SHIFT 13 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD1_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD1_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD2_SHIFT 12 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD2_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD2_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD3_SHIFT 11 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD3_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD3_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD4_SHIFT 10 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD4_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD4_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD5_SHIFT 9 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD5_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD5_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD6_SHIFT 8 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD6_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD6_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD7_SHIFT 7 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD7_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD7_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD8_SHIFT 6 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORD8_MASK I40E_MASK(0x1ULL, I40E_REG_INSET_FLEX_PAYLOAD_WORD8_SHIFT) +#define I40E_REG_INSET_FLEX_PAYLOAD_WORDS_SHIFT 6 +#define I40E_REG_INSET_FLEX_PAYLOAD_WORDS_MASK I40E_MASK(0xFFULL, I40E_REG_INSET_FLEX_PAYLOAD_WORDS_SHIFT) +#define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL + #endif /* PF_DRIVER */ #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 #define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT) -- 2.17.1