From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A242A04FA; Thu, 6 Feb 2020 05:27:31 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 273721C1E9; Thu, 6 Feb 2020 05:27:30 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 287A41C1D9; Thu, 6 Feb 2020 05:27:28 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0164QWg5031320; Wed, 5 Feb 2020 20:27:28 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=pfpt0818; bh=Q09sDRl15WCfPhuXY4kg8BlQHXlR9xdFWRsssrIeSEw=; b=fHL6uXkxSsHljXHNfNmcD9GDlE+9KO/LDo+zwy7zVAxgOsDlGrL4tb8nYyeWHclyRhFA xMAIuYFiqmbvcKLLJ1qy8fSdoQ5Ja2nRTiJH84bsWCkAuCbyIyBTC8enmRvhb9zbqhdd qBtrzq+/X6mAel3quNxnZjqv2D4lawwzy/ws52ZrF6qYQOVIueT9Tkis6N0grIB134+Q EtBew8oFEDWfYKCF97Bvk8IcUCQl4IjdMk2QZVZ07ggYUgAGHUV3euEYHDfRKyg8kxOF PfhoPYL8CLLAD5lDk0MvemYL75NaIysRYtkxYREFYuXEsoa4jUXN9/OlCPaCMJ/rqtl3 /Q== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2xyhmte20f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 05 Feb 2020 20:27:28 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 5 Feb 2020 20:27:26 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 5 Feb 2020 20:27:26 -0800 Received: from hyd1vattunuru-dt.caveonetworks.com (unknown [10.29.52.72]) by maili.marvell.com (Postfix) with ESMTP id 295A53F73BA; Wed, 5 Feb 2020 20:27:24 -0800 (PST) From: To: CC: , Vamsi Attunuru , Date: Thu, 6 Feb 2020 09:57:13 +0530 Message-ID: <20200206042713.6761-1-vattunuru@marvell.com> X-Mailer: git-send-email 2.8.4 MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-05_06:2020-02-04, 2020-02-05 signatures=0 Subject: [dpdk-dev] [PATCH v1 1/1] net/octeontx2: fix flow control initial state X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Vamsi Attunuru Currently when application requests for RTE_FC_NONE earlier than PMD's internal fc mode update, flow control set routine is returning without updating the flow control state. Patch updates the PMD's internal fc mode details during dev_configure to ensure any flow control set requests issued later are handled properly. Fixes: 609945f1ce90 ("net/octeontx2: support flow control") Cc: stable@dpdk.org Signed-off-by: Vamsi Attunuru --- drivers/net/octeontx2/otx2_ethdev.c | 6 ++++++ drivers/net/octeontx2/otx2_ethdev.h | 2 ++ drivers/net/octeontx2/otx2_flow_ctrl.c | 35 ++++++++++++++++++++++++++++++---- 3 files changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c index 1ec234b..25b1c5c 100644 --- a/drivers/net/octeontx2/otx2_ethdev.c +++ b/drivers/net/octeontx2/otx2_ethdev.c @@ -1727,6 +1727,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev) goto cq_fini; } + rc = otx2_nix_flow_ctrl_init(eth_dev); + if (rc) { + otx2_err("Failed to init flow ctrl mode %d", rc); + goto cq_fini; + } + rc = otx2_nix_mc_addr_list_install(eth_dev); if (rc < 0) { otx2_err("Failed to install mc address list rc=%d", rc); diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index 49fed95..4b3ad95 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -509,6 +509,8 @@ int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *addr); /* Flow Control */ +int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev); + int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev, struct rte_eth_fc_conf *fc_conf); diff --git a/drivers/net/octeontx2/otx2_flow_ctrl.c b/drivers/net/octeontx2/otx2_flow_ctrl.c index 1c6929e..76bf481 100644 --- a/drivers/net/octeontx2/otx2_flow_ctrl.c +++ b/drivers/net/octeontx2/otx2_flow_ctrl.c @@ -200,16 +200,14 @@ int otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev) { struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct otx2_fc_info *fc = &dev->fc_info; struct rte_eth_fc_conf fc_conf; if (otx2_dev_is_lbk(dev) || otx2_dev_is_sdp(dev)) return 0; memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf)); - /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW - * by AF driver, update those info in PMD structure. - */ - otx2_nix_flow_ctrl_get(eth_dev, &fc_conf); + fc_conf.mode = fc->mode; /* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */ if (otx2_dev_is_Ax(dev) && @@ -223,3 +221,32 @@ otx2_nix_update_flow_ctrl_mode(struct rte_eth_dev *eth_dev) return otx2_nix_flow_ctrl_set(eth_dev, &fc_conf); } + +int +otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev) +{ + struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev); + struct otx2_fc_info *fc = &dev->fc_info; + struct rte_eth_fc_conf fc_conf; + int rc; + + if (otx2_dev_is_lbk(dev) || otx2_dev_is_sdp(dev)) + return 0; + + memset(&fc_conf, 0, sizeof(struct rte_eth_fc_conf)); + /* Both Rx & Tx flow ctrl get enabled(RTE_FC_FULL) in HW + * by AF driver, update those info in PMD structure. + */ + rc = otx2_nix_flow_ctrl_get(eth_dev, &fc_conf); + if (rc) + goto exit; + + fc->mode = fc_conf.mode; + fc->rx_pause = (fc_conf.mode == RTE_FC_FULL) || + (fc_conf.mode == RTE_FC_RX_PAUSE); + fc->tx_pause = (fc_conf.mode == RTE_FC_FULL) || + (fc_conf.mode == RTE_FC_TX_PAUSE); + +exit: + return rc; +} -- 2.8.4