From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id EC101A0542; Thu, 13 Feb 2020 13:43:56 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C84911BFD3; Thu, 13 Feb 2020 13:43:56 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 7CF541BFD3; Thu, 13 Feb 2020 13:43:55 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E3ADD1FB; Thu, 13 Feb 2020 04:43:54 -0800 (PST) Received: from net-arm-thunderx2-04.shanghai.arm.com (net-arm-thunderx2-04.shanghai.arm.com [10.169.40.184]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D3FA73F6CF; Thu, 13 Feb 2020 04:43:48 -0800 (PST) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com, stable@dpdk.org Date: Thu, 13 Feb 2020 20:38:49 +0800 Message-Id: <20200213123854.203566-2-gavin.hu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com> References: <20200213123854.203566-1-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH RFC v1 1/6] net/mlx5: relax the barrier for UAR write X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The UAR is part of PCI address space that is mapped for direct access to the HCA from the CPU. Read-Write accesses to this space are strongly ordered thus a compiler barrier is sufficient for all arches. This patch set is based on the following aarch64 architecural facts: 1. The PCI BAR space is mapped as nGnRE device memory, not cachable nor write-combine. 2. io accesses to a single device is total ordered. Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems") Cc: stable@dpdk.org Signed-off-by: Gavin Hu Reviewed-by: Phil Yang --- drivers/net/mlx5/mlx5_rxtx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 939778aa5..50b3cc3c9 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -546,7 +546,7 @@ __mlx5_uar_write64_relaxed(uint64_t val, void *addr, static __rte_always_inline void __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock) { - rte_io_wmb(); + rte_compiler_barrier(); __mlx5_uar_write64_relaxed(val, addr, lock); } -- 2.17.1