From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 23C05A0524; Tue, 25 Feb 2020 10:46:53 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 011AB1BFB5; Tue, 25 Feb 2020 10:46:53 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A7BB61BC24 for ; Tue, 25 Feb 2020 10:46:51 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 01P9fItY021116; Tue, 25 Feb 2020 01:46:50 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=CiazbzdsLZFep5DzhD6BY8PZNdDYtVcG8tBumfJ3+/I=; b=vnB5c0dbLdosQoqdsnn6WBllCKMkYj0fhjDxQWbv8StxeL49PCCmcEh1cAR+MbYVx7GU t5n+vLHrRlS6ECDDySJRoKi8qQge5NrP5kA+0p4kK7fdoXbr4ofpAGx4hFr/ac9qL8r0 P80vRyZesBwf1ExbGmtokX+aCFharNQg9Jak3V1cVbYLNS4KpoiWY8HYrlOtD3YNVV6n ZVATuQzQPBhv4aODr4F53DXH8Og9hJ5h79pzLyu4zoE++tnQaL8fk7jrzSAENpUXw/P7 KGShvXy45XToqCG/Wn307riBviDrrv5UjI9PP7v6M26BOtyPC62+whqlNgwx9jejLO1v CA== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2yb2hvbeme-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 25 Feb 2020 01:46:50 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Feb 2020 01:46:49 -0800 Received: from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 25 Feb 2020 01:46:48 -0800 Received: from hyd1399.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 25 Feb 2020 01:46:45 -0800 From: Nagadheeraj Rottela To: , CC: , , Nagadheeraj Rottela Date: Tue, 25 Feb 2020 15:16:41 +0530 Message-ID: <20200225094642.29239-1-rnagadheeraj@marvell.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200220110431.30074-1-rnagadheeraj@marvell.com> References: <20200220110431.30074-1-rnagadheeraj@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-02-25_02:2020-02-21, 2020-02-25 signatures=0 Subject: [dpdk-dev] [PATCH v2 1/2] crypto/nitrox: fix invalid CSR register address generation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" If the NPS_PKT ring/port is greater than 8191 the NPS_PKT*() macros will evaluate to incorrect values due to unintended sign extension from int to unsigned long. To fix this, add UL suffix to the constants in these macros. Coverity issue: 349899, 349905, 349911, 349921, 349923 Fixes: 32e4930d5a3b ("crypto/nitrox: add hardware queue management") Signed-off-by: Nagadheeraj Rottela --- drivers/crypto/nitrox/nitrox_csr.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h index 8cd92e38b..b4c969b26 100644 --- a/drivers/crypto/nitrox/nitrox_csr.h +++ b/drivers/crypto/nitrox/nitrox_csr.h @@ -12,15 +12,15 @@ #define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset)) /* NPS packet registers */ -#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000)) -#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000)) -#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000)) -#define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000)) -#define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000)) -#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000)) +#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078UL + ((_i) * 0x40000UL)) +#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088UL + ((_i) * 0x40000UL)) +#define NPS_PKT_SLC_CTLX(_i) (0x10000UL + ((_i) * 0x40000UL)) +#define NPS_PKT_SLC_CNTSX(_i) (0x10008UL + ((_i) * 0x40000UL)) +#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010UL + ((_i) * 0x40000UL)) /* AQM Virtual Function Registers */ #define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000)) -- 2.13.6