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Fri, 28 Feb 2020 14:21:12 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.156.251] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: e761536f-9bc2-4e01-c5d1-08d7bc59772f X-MS-TrafficTypeDiagnostic: MN2PR12MB3599:|MN2PR12MB3599: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:478; X-Forefront-PRVS: 0327618309 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(396003)(39860400002)(136003)(376002)(346002)(366004)(199004)(189003)(5660300002)(2906002)(81166006)(2616005)(6666004)(956004)(16526019)(186003)(478600001)(66556008)(4326008)(66946007)(1076003)(66476007)(26005)(316002)(6486002)(36756003)(8936002)(81156014)(8676002)(7696005)(6916009)(52116002)(86362001)(9686003); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR12MB3599; H:MN2PR12MB3021.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Dy/h2DNRCzLzzjIKzpzhSMYNChcremDcJc2T7cZ9D2VSp0snLRYh8OaeJ6ruC19dbKDEmQ2cgvZCqxQjXdqAFfd2S/5Y0Gwk8BUQfS40BWOGZn3SwSrlE5hapoUMXtdhXeTMc6uLUAFSEnPyfpCG0wKcmOjxsFFAYUc+6O9tG3wFHD4oFgcm0P6xL6K+0ctD/dJiNYcIo7JkikIkavxqy5B895XGjdWx6Tm4RX1WuXP52ftkelJx8eaM2zZ9t4TNJkMpx9vpvNGImguOKrYEdIAYLCDDKAJvcNy+tqdUrgPU+V4acz88DVofxnyeOR+i4svJkWVK/1WGadyqCX78U8vKJ2zSW1j/4BtAe6QsU1u+0cjisL8f/lsvbyGgUNlUi+d6AR20syiTzuor92QsZgsY/PgLiSiDzO/Nwhyn7UmzMC6cVGhUEVB35RU0524Z X-MS-Exchange-AntiSpam-MessageData: ylBfU/8okcM82mVuBLUuTkZaN9D/+0Kvjm/PI5WqmncmcYX5MWpVYIBIOv+OYMINtvqjUAUynDJadwqvF1Aq0+4FNUFrKObul7N6t9rgZ5qjzbD8ji5dLPzHldEEy+32bppYdA8tzznCSFgYDjzQ6A== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e761536f-9bc2-4e01-c5d1-08d7bc59772f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Feb 2020 14:21:13.7513 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: sMOrVzw75jqLYccRmNrnc7pghMWSpiUEyjCB45XjyLE/XWfnw6I13KsMW7UrN/fUXwHCrjdZr4cL5B4cprw84g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3599 Subject: [dpdk-dev] [PATCH v1 2/2] net/axgbe: add unicast hash table for mac address X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Chandu Babu N implement eth_dev_ops uc_hash_table_set and uc_all_hash_table_set Signed-off-by: Chandu Babu N --- drivers/net/axgbe/axgbe_common.h | 2 + drivers/net/axgbe/axgbe_dev.c | 60 ++++++++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.c | 79 ++++++++++++++++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.h | 10 +++- 4 files changed, 150 insertions(+), 1 deletion(-) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index 2ac4d8946..72683aa65 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -292,6 +292,8 @@ #define MAC_MACAHR(i) (MAC_MACA0HR + ((i) * 8)) #define MAC_MACALR(i) (MAC_MACA0LR + ((i) * 8)) +#define MAC_HTR(i) (MAC_HTR0 + ((i) * MAC_HTR_INC)) + /* MAC register entry bit positions and sizes */ #define MAC_HWF0R_ADDMACADRSEL_INDEX 18 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5 diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index f830b7230..5f0f19592 100644 --- a/drivers/net/axgbe/axgbe_dev.c +++ b/drivers/net/axgbe/axgbe_dev.c @@ -1008,6 +1008,50 @@ static void axgbe_enable_mtl_interrupts(struct axgbe_port *pdata) } } +static uint32_t bitrev32(uint32_t x) +{ + x = (x >> 16) | (x << 16); + x = (((x & 0xff00ff00) >> 8) | ((x & 0x00ff00ff) << 8)); + x = (((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4)); + x = (((x & 0xcccccccc) >> 2) | ((x & 0x33333333) << 2)); + x = (((x & 0xaaaaaaaa) >> 1) | ((x & 0x55555555) << 1)); + return x; +} + +static uint32_t crc32_le(uint32_t crc, uint8_t *p, uint32_t len) +{ + int i; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0); + } + return crc; +} + +void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add) +{ + uint32_t crc, htable_index, htable_bitmask; + + crc = bitrev32(~crc32_le(~0, addr, RTE_ETHER_ADDR_LEN)); + crc >>= pdata->hash_table_shift; + htable_index = crc >> 5; + htable_bitmask = 1 << (crc & 0x1f); + + if (add) { + pdata->uc_hash_table[htable_index] |= htable_bitmask; + pdata->uc_hash_mac_addr++; + } else { + pdata->uc_hash_table[htable_index] &= ~htable_bitmask; + pdata->uc_hash_mac_addr--; + } + PMD_DRV_LOG(DEBUG, "%s MAC hash table Bit %d at Index %#x\n", + add ? "set" : "clear", (crc & 0x1f), htable_index); + + AXGMAC_IOWRITE(pdata, MAC_HTR(htable_index), + pdata->uc_hash_table[htable_index]); +} + void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t index) { unsigned int mac_addr_hi, mac_addr_lo; @@ -1051,6 +1095,21 @@ static int axgbe_set_mac_address(struct axgbe_port *pdata, u8 *addr) return 0; } +static void axgbe_config_mac_hash_table(struct axgbe_port *pdata) +{ + struct axgbe_hw_features *hw_feat = &pdata->hw_feat; + + pdata->hash_table_shift = 0; + pdata->hash_table_count = 0; + pdata->uc_hash_mac_addr = 0; + memset(pdata->uc_hash_table, 0, sizeof(pdata->uc_hash_table)); + + if (hw_feat->hash_table_size) { + pdata->hash_table_shift = 26 - (hw_feat->hash_table_size >> 7); + pdata->hash_table_count = hw_feat->hash_table_size / 32; + } +} + static void axgbe_config_mac_address(struct axgbe_port *pdata) { axgbe_set_mac_address(pdata, pdata->mac_addr.addr_bytes); @@ -1129,6 +1188,7 @@ static int axgbe_init(struct axgbe_port *pdata) axgbe_enable_mtl_interrupts(pdata); /* Initialize MAC related features */ + axgbe_config_mac_hash_table(pdata); axgbe_config_mac_address(pdata); axgbe_config_jumbo_enable(pdata); axgbe_config_flow_control(pdata); diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index 34cc0fbb8..a1d048a9d 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -30,6 +30,11 @@ static void axgbe_dev_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); static int axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, struct rte_ether_addr *mc_addr_set, uint32_t nb_mc_addr); +static int axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, + struct rte_ether_addr *mac_addr, + uint8_t add); +static int axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, + uint8_t add); static int axgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete); static int axgbe_dev_get_regs(struct rte_eth_dev *dev, @@ -174,6 +179,8 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = { .mac_addr_add = axgbe_dev_mac_addr_add, .mac_addr_remove = axgbe_dev_mac_addr_remove, .set_mc_addr_list = axgbe_dev_set_mc_addr_list, + .uc_hash_table_set = axgbe_dev_uc_hash_table_set, + .uc_all_hash_table_set = axgbe_dev_uc_all_hash_table_set, .link_update = axgbe_dev_link_update, .get_reg = axgbe_dev_get_regs, .stats_get = axgbe_dev_stats_get, @@ -452,6 +459,65 @@ axgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev, return 0; } +static int +axgbe_dev_uc_hash_table_set(struct rte_eth_dev *dev, + struct rte_ether_addr *mac_addr, uint8_t add) +{ + struct axgbe_port *pdata = dev->data->dev_private; + struct axgbe_hw_features *hw_feat = &pdata->hw_feat; + + if (!hw_feat->hash_table_size) { + PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); + return -ENOTSUP; + } + + axgbe_set_mac_hash_table(pdata, (u8 *)mac_addr, add); + + if (pdata->uc_hash_mac_addr > 0) { + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); + } else { + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); + } + return 0; +} + +static int +axgbe_dev_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t add) +{ + struct axgbe_port *pdata = dev->data->dev_private; + struct axgbe_hw_features *hw_feat = &pdata->hw_feat; + uint32_t index; + + if (!hw_feat->hash_table_size) { + PMD_DRV_LOG(ERR, "MAC Hash Table not supported\n"); + return -ENOTSUP; + } + + for (index = 0; index < pdata->hash_table_count; index++) { + if (add) + pdata->uc_hash_table[index] = ~0; + else + pdata->uc_hash_table[index] = 0; + + PMD_DRV_LOG(DEBUG, "%s MAC hash table at Index %#x\n", + add ? "set" : "clear", index); + + AXGMAC_IOWRITE(pdata, MAC_HTR(index), + pdata->uc_hash_table[index]); + } + + if (add) { + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); + } else { + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 0); + AXGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 0); + } + return 0; +} + /* return 0 means link status changed, -1 means not changed */ static int axgbe_dev_link_update(struct rte_eth_dev *dev, @@ -892,6 +958,7 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) dev_info->min_rx_bufsize = AXGBE_RX_MIN_BUF_SIZE; dev_info->max_rx_pktlen = AXGBE_RX_MAX_BUF_SIZE; dev_info->max_mac_addrs = pdata->hw_feat.addn_mac + 1; + dev_info->max_hash_mac_addrs = pdata->hw_feat.hash_table_size; dev_info->speed_capa = ETH_LINK_SPEED_10G; dev_info->rx_offload_capa = @@ -1206,6 +1273,18 @@ eth_axgbe_dev_init(struct rte_eth_dev *eth_dev) return -ENOMEM; } + /* Allocate memory for storing hash filter MAC addresses */ + len = RTE_ETHER_ADDR_LEN * AXGBE_MAX_HASH_MAC_ADDRS; + eth_dev->data->hash_mac_addrs = rte_zmalloc("axgbe_hash_mac_addr", + len, 0); + + if (eth_dev->data->hash_mac_addrs == NULL) { + PMD_INIT_LOG(ERR, + "Failed to allocate %d bytes needed to " + "store MAC addresses", len); + return -ENOMEM; + } + if (!rte_is_valid_assigned_ether_addr(&pdata->mac_addr)) rte_eth_random_addr(pdata->mac_addr.addr_bytes); diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index 781d170e5..3969317fd 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -17,6 +17,7 @@ #define AXGBE_RX_MAX_BUF_SIZE (0x3fff & ~(64 - 1)) #define AXGBE_RX_MIN_BUF_SIZE (RTE_ETHER_MAX_LEN + VLAN_HLEN) #define AXGBE_MAX_MAC_ADDRS 32 +#define AXGBE_MAX_HASH_MAC_ADDRS 256 #define AXGBE_RX_BUF_ALIGN 64 @@ -83,7 +84,7 @@ (((_x) < 1024) ? 0 : ((_x) / AXGMAC_FLOW_CONTROL_UNIT) - 2) #define AXGMAC_FLOW_CONTROL_MAX 33280 -/* Maximum MAC address hash table size (256 bits = 8 bytes) */ +/* Maximum MAC address hash table size (256 bits = 8 dword) */ #define AXGBE_MAC_HASH_TABLE_SIZE 8 /* Receive Side Scaling */ @@ -625,6 +626,12 @@ struct axgbe_port { uint32_t rx_csum_enable; struct axgbe_mmc_stats mmc_stats; + + /* Hash filtering */ + unsigned int hash_table_shift; + unsigned int hash_table_count; + unsigned int uc_hash_mac_addr; + unsigned int uc_hash_table[AXGBE_MAC_HASH_TABLE_SIZE]; }; void axgbe_init_function_ptrs_dev(struct axgbe_hw_if *hw_if); @@ -633,5 +640,6 @@ void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if); void axgbe_init_function_ptrs_i2c(struct axgbe_i2c_if *i2c_if); void axgbe_set_mac_addn_addr(struct axgbe_port *pdata, u8 *addr, uint32_t index); +void axgbe_set_mac_hash_table(struct axgbe_port *pdata, u8 *addr, bool add); #endif /* RTE_ETH_AXGBE_H_ */ -- 2.17.1