From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 70D5EA0568; Mon, 2 Mar 2020 10:01:59 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BEBD81C0B6; Mon, 2 Mar 2020 10:00:28 +0100 (CET) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id 07B8C1C067 for ; Mon, 2 Mar 2020 10:00:22 +0100 (CET) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E07B21A0FDC; Mon, 2 Mar 2020 10:00:21 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 206861A0FB1; Mon, 2 Mar 2020 10:00:19 +0100 (CET) Received: from bf-netperf1.ap.com (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id C2D96402FA; Mon, 2 Mar 2020 17:00:15 +0800 (SGT) From: Hemant Agrawal To: ferruh.yigit@intel.com Cc: dev@dpdk.org, g.singh@nxp.com, Alex Marginean Date: Mon, 2 Mar 2020 20:02:08 +0530 Message-Id: <20200302143209.11854-10-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200302143209.11854-1-hemant.agrawal@nxp.com> References: <20200302143209.11854-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH 09/10] net/enetc: improve prefetch in Rx ring clean X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Alex Marginean LS1028A does not have platform cache so any reads following a hardware write will go directly to DDR. Latency of such a read is in excess of 100 core cycles, so try to prefetch more in advance to mitigate this. How much is worth prefetching really depends on traffic conditions. With congested Rx this could go up to 4 cache lines or so. But if software keeps up with hardware and follows behind Rx PI by a cache line then it's harmful in terms of performance to cache more. We would only prefetch data that's yet to be written by ENETC, which will be evicted again anyway. Signed-off-by: Alex Marginean --- drivers/net/enetc/enetc_rxtx.c | 38 +++++++++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 5 deletions(-) diff --git a/drivers/net/enetc/enetc_rxtx.c b/drivers/net/enetc/enetc_rxtx.c index 1acc43a08..e57ecf2d4 100644 --- a/drivers/net/enetc/enetc_rxtx.c +++ b/drivers/net/enetc/enetc_rxtx.c @@ -14,6 +14,8 @@ #include "enetc.h" #include "enetc_logs.h" +#define ENETC_CACHE_LINE_RXBDS (RTE_CACHE_LINE_SIZE / \ + sizeof(union enetc_rx_bd)) #define ENETC_RXBD_BUNDLE 16 /* Number of buffers to allocate at once */ static int @@ -321,18 +323,37 @@ enetc_clean_rx_ring(struct enetc_bdr *rx_ring, int work_limit) { int rx_frm_cnt = 0; - int cleaned_cnt, i; + int cleaned_cnt, i, bd_count; struct enetc_swbd *rx_swbd; + union enetc_rx_bd *rxbd; - cleaned_cnt = enetc_bd_unused(rx_ring); /* next descriptor to process */ i = rx_ring->next_to_clean; + /* next descriptor to process */ + rxbd = ENETC_RXBD(*rx_ring, i); + rte_prefetch0(rxbd); + bd_count = rx_ring->bd_count; + /* LS1028A does not have platform cache so any software access following + * a hardware write will go directly to DDR. Latency of such a read is + * in excess of 100 core cycles, so try to prefetch more in advance to + * mitigate this. + * How much is worth prefetching really depends on traffic conditions. + * With congested Rx this could go up to 4 cache lines or so. But if + * software keeps up with hardware and follows behind Rx PI by a cache + * line or less then it's harmful in terms of performance to cache more. + * We would only prefetch BDs that have yet to be written by ENETC, + * which will have to be evicted again anyway. + */ + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS) % bd_count)); + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS * 2) % bd_count)); + + cleaned_cnt = enetc_bd_unused(rx_ring); rx_swbd = &rx_ring->q_swbd[i]; while (likely(rx_frm_cnt < work_limit)) { - union enetc_rx_bd *rxbd; uint32_t bd_status; - rxbd = ENETC_RXBD(*rx_ring, i); bd_status = rte_le_to_cpu_32(rxbd->r.lstatus); if (!bd_status) break; @@ -353,11 +374,18 @@ enetc_clean_rx_ring(struct enetc_bdr *rx_ring, i = 0; rx_swbd = &rx_ring->q_swbd[i]; } + rxbd = ENETC_RXBD(*rx_ring, i); + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS) % + bd_count)); + rte_prefetch0(ENETC_RXBD(*rx_ring, + (i + ENETC_CACHE_LINE_RXBDS * 2) % + bd_count)); - rx_ring->next_to_clean = i; rx_frm_cnt++; } + rx_ring->next_to_clean = i; enetc_refill_rx_ring(rx_ring, cleaned_cnt); return rx_frm_cnt; -- 2.17.1