From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 831BCA0576; Fri, 13 Mar 2020 19:07:59 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D864B2BE3; Fri, 13 Mar 2020 19:07:58 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id BFEEE1AFF for ; Fri, 13 Mar 2020 19:07:56 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Mar 2020 11:07:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,549,1574150400"; d="scan'208";a="278317292" Received: from akusztax-mobl.ger.corp.intel.com ([10.104.121.22]) by fmsmga002.fm.intel.com with ESMTP; 13 Mar 2020 11:07:53 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: akhil.goyal@nxp.com, fiona.trahe@intel.com, Arek Kusztal Date: Fri, 13 Mar 2020 19:07:50 +0100 Message-Id: <20200313180751.2068-1-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.19.1.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 1/2] crypto/qat: add aes-gcm J0 handling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds J0 capability to Intel QuickAssist Technology driver Signed-off-by: Arek Kusztal --- drivers/crypto/qat/qat_sym_capabilities.h | 8 ++++---- drivers/crypto/qat/qat_sym_session.c | 11 ++++++++--- drivers/crypto/qat/qat_sym_session.h | 5 +++++ 3 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h index 028a56c..36be80a 100644 --- a/drivers/crypto/qat/qat_sym_capabilities.h +++ b/drivers/crypto/qat/qat_sym_capabilities.h @@ -227,9 +227,9 @@ .increment = 1 \ }, \ .iv_size = { \ - .min = 12, \ + .min = 0, \ .max = 12, \ - .increment = 0 \ + .increment = 12 \ }, \ }, } \ }, } \ @@ -252,9 +252,9 @@ .increment = 4 \ }, \ .iv_size = { \ - .min = 12, \ + .min = 0, \ .max = 12, \ - .increment = 0 \ + .increment = 12 \ } \ }, } \ }, } \ diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 4359f2f..b7ca846 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -653,6 +653,9 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, uint8_t key_length = auth_xform->key.length; session->aes_cmac = 0; + session->auth_iv.offset = auth_xform->iv.offset; + session->auth_iv.length = auth_xform->iv.length; + switch (auth_xform->algo) { case RTE_CRYPTO_AUTH_SHA1_HMAC: session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1; @@ -684,6 +687,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128; + if (session->auth_iv.length == 0) + session->auth_iv.length = AES_GCM_J0_LEN; break; case RTE_CRYPTO_AUTH_SNOW3G_UIA2: @@ -723,9 +728,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, return -EINVAL; } - session->auth_iv.offset = auth_xform->iv.offset; - session->auth_iv.length = auth_xform->iv.length; - if (auth_xform->algo == RTE_CRYPTO_AUTH_AES_GMAC) { if (auth_xform->op == RTE_CRYPTO_AUTH_OP_GENERATE) { session->qat_cmd = ICP_QAT_FW_LA_CMD_CIPHER_HASH; @@ -808,6 +810,9 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev, } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128; + if (session->cipher_iv.length == 0) + session->cipher_iv.length = AES_GCM_J0_LEN; + break; case RTE_CRYPTO_AEAD_AES_CCM: if (qat_sym_validate_aes_key(aead_xform->key.length, diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index 98985d6..5a01c81 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -20,6 +20,11 @@ #define KASUMI_F8_KEY_MODIFIER_4_BYTES 0x55555555 +/* + * AES-GCM J0 length + */ +#define AES_GCM_J0_LEN 16 + /* 3DES key sizes */ #define QAT_3DES_KEY_SZ_OPT1 24 /* Keys are independent */ #define QAT_3DES_KEY_SZ_OPT2 16 /* K3=K1 */ -- 2.1.0