From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 532DBA0563; Mon, 23 Mar 2020 08:19:37 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A5E201C19F; Mon, 23 Mar 2020 08:16:00 +0100 (CET) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by dpdk.org (Postfix) with ESMTP id C322C1C130 for ; Mon, 23 Mar 2020 08:15:34 +0100 (CET) IronPort-SDR: AZ8TFq9Ba+7M5W7LJBnQDHpUSavv8re0L6N0lxfpqcAPvtvI851kepZWeCMAYIunkWxoAxghOC xMGm1Tnep8pw== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Mar 2020 00:15:34 -0700 IronPort-SDR: a432yjE39of2t4Hf4l1Me1021woPTHSLaffk1JwD2vZut3Cw4uonB7Q77IMaKrK2cHop/2cfqH Hzx36h7KZOFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,295,1580803200"; d="scan'208";a="246111781" Received: from dpdk51.sh.intel.com ([10.67.110.245]) by orsmga003.jf.intel.com with ESMTP; 23 Mar 2020 00:15:32 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Haiyue Wang , Paul M Stillwell Jr Date: Mon, 23 Mar 2020 15:17:51 +0800 Message-Id: <20200323071759.13075-29-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200323071759.13075-1-qi.z.zhang@intel.com> References: <20200309114357.31800-1-qi.z.zhang@intel.com> <20200323071759.13075-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH v2 28/36] net/ice/base: don't access some hardware registers in DCF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" DCF runs as a VF so it can't access PF registers. And export the filter management list static functions as public for make DCF initialization. Signed-off-by: Haiyue Wang Signed-off-by: Paul M Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 7 +++++-- drivers/net/ice/base/ice_common.h | 3 ++- drivers/net/ice/base/ice_flex_pipe.c | 8 ++++++-- drivers/net/ice/base/ice_type.h | 1 + 4 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 61973286f..0d5a4e3e4 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -463,12 +463,13 @@ ice_aq_set_mac_cfg(struct ice_hw *hw, u16 max_frame_size, struct ice_sq_cd *cd) * ice_init_fltr_mgmt_struct - initializes filter management list and locks * @hw: pointer to the HW struct */ -static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) +enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) { struct ice_switch_info *sw; hw->switch_info = (struct ice_switch_info *) ice_malloc(hw, sizeof(*hw->switch_info)); + sw = hw->switch_info; if (!sw) @@ -483,7 +484,7 @@ static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw) * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks * @hw: pointer to the HW struct */ -static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) +void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw) { struct ice_switch_info *sw = hw->switch_info; struct ice_vsi_list_map_info *v_pos_map; @@ -1914,6 +1915,8 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count, dev_p->num_flow_director_fltr); } if (func_p) { + if (hw->dcf_enabled) + break; reg_val = rd32(hw, GLQF_FD_SIZE); val = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >> GLQF_FD_SIZE_FD_GSIZE_S; diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index c7095e727..8f6a33b91 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -19,7 +19,8 @@ enum ice_fw_modes { }; enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw); - +enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw); +void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw); enum ice_status ice_init_hw(struct ice_hw *hw); void ice_deinit_hw(struct ice_hw *hw); enum ice_status diff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c index fa4e90b08..dd0c18324 100644 --- a/drivers/net/ice/base/ice_flex_pipe.c +++ b/drivers/net/ice/base/ice_flex_pipe.c @@ -1253,6 +1253,8 @@ static void ice_init_pkg_regs(struct ice_hw *hw) #define ICE_SW_BLK_INP_MASK_L 0xFFFFFFFF #define ICE_SW_BLK_INP_MASK_H 0x0000FFFF #define ICE_SW_BLK_IDX 0 + if (hw->dcf_enabled) + return; /* setup Switch block input mask, which is 48-bits in two parts */ wr32(hw, GL_PREEXT_L2_PMASK0(ICE_SW_BLK_IDX), ICE_SW_BLK_INP_MASK_L); @@ -3602,7 +3604,8 @@ void ice_free_hw_tbls(struct ice_hw *hw) ice_free(hw, r); } ice_destroy_lock(&hw->rss_locks); - ice_shutdown_all_prof_masks(hw); + if (!hw->dcf_enabled) + ice_shutdown_all_prof_masks(hw); ice_memset(hw->blk, 0, sizeof(hw->blk), ICE_NONDMA_MEM); } @@ -3682,7 +3685,8 @@ enum ice_status ice_init_hw_tbls(struct ice_hw *hw) ice_init_lock(&hw->rss_locks); INIT_LIST_HEAD(&hw->rss_list_head); - ice_init_all_prof_masks(hw); + if (!hw->dcf_enabled) + ice_init_all_prof_masks(hw); for (i = 0; i < ICE_BLK_COUNT; i++) { struct ice_prof_redir *prof_redir = &hw->blk[i].prof_redir; struct ice_prof_tcam *prof = &hw->blk[i].prof; diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index 478940225..c14188f4c 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -822,6 +822,7 @@ struct ice_hw { int (*aq_send_cmd_fn)(void *param, struct ice_aq_desc *desc, void *buf, u16 buf_size); void *aq_send_cmd_param; + u8 dcf_enabled; /* Device Config Function */ u8 api_branch; /* API branch version */ u8 api_maj_ver; /* API major version */ -- 2.13.6